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M. Balaguer
a
, B. Iiguez
b,
, J.B. Roldn
a
a
Departamento de Electrnica y Tecnologa de Computadores, Facultad de Ciencias, Universidad de Granada, Avda. Fuente Nueva S/N, 18071 Granada, Spain
b
Departament dEnginyeria Electrnica, Elctrica y Automatica, Universitat Rovira i Virgili, 43007 Tarragona, Spain
a r t i c l e i n f o
Article history:
Received 22 June 2011
Accepted 27 June 2011
Available online 9 August 2011
The review of this paper was arranged by
Prof. S. Cristoloveanu
Keywords:
Double-gate MOSFETs
Schottky-barrier SOI MOSFETs
Compact modeling
Semiconductor device MOSFETs
SOI MOSFETs
a b s t r a c t
An analytical and explicit compact model for undoped symmetrical silicon double gate MOSFETs
(DGMOSFETs) with Schottky barrier (SB) source and drain is presented. The SB MOSFET can be studied
as a traditional MOSFET where the doped source/drain regions have been replaced by a metal contact.
Due to particular features of this new structure, the main transport mechanisms of these devices differ
from those found in traditional MOSFETs. The model developed in this paper is based on a previously
published DGMOSFET model which has been extended to include the characteristic tunneling transport
mechanisms of SB MOSFET.
The proposed model reproduces the well known ambipolar behavior found in SB MOSFET for a wide
range of metal source and drain contacts specied through different values of their work function. The
model has been validated with numerical data obtained by means of the 2D ATLAS simulator, where a
SB DGMOSFET structure has been dened and characterized in order to obtain the transfer and output
characteristics for several bias congurations. Devices with two channel lengths (2 lm and 3 lm) has
been simulated and modeled.
2011 Elsevier Ltd. All rights reserved.
1. Introduction
As it is well known, conventional bulk MOSFETs are approach-
ing the end of the technology roadmap, therefore new alternatives
are being investigated [1]. SOI devices [2], strained substrates, IIIV
materials and multi-gate structures [310] are under continuous
study to explore their possibilities of being considered the basic
components of the future integrated circuit technology, with nodes
under 22 nm.
DGMOSFETs are among the most promising devices in order to
increase the integration capacity of silicon technology [35]. The
use of two gates has demonstrated good electrostatic control of
the channel charge and therefore the possibility of a higher reduc-
tion in channel length compared to traditional bulk MOSFETs
[4,5,9]. Drain-induced barrier-height lowering (DIBL) and thresh-
old voltage roll-off are greatly reduced in these devices [5,9,10].
The characteristic sharp DGMOSFET subthreshold slopes (close to
60 mV/dec at room temperature) lead to a larger gate overdrive
for the same power supply and the same off-current. In addition,
DGMOSFET low-eld mobility is enhanced as a consequence of vol-
ume inversion and channel doping reduction [69].
One of the problems that DGMOSFETs present is related to the
high series resistance of the drain and source contacts. In future
technologies, as the channel lengths are reduced, the silicon layer
thickness of these devices will have to be reduced in order to con-
trol short channel effects, this reduction will also diminish the area
between the source/drain contacts and the silicon substrate, and
consequently increase the source and drain series resistance. One
of the technological alternatives available to overcome this draw-
back is connected to the use of metalsemiconductor contacts in-
stead of the usual silicon highly doped source/drain regions.
These devices, Schottky barrier MOSFETs (SB MOSFETs) were intro-
duced some time ago [11].
SB MOSFETs present several important advantages with respect
to their conventional MOSFETs counterparts [12,13] like low para-
sitic S/D resistance, as explained before, low temperature process-
ing for S/D formation, elimination of parasitic bipolar action, and
the possibility of reducing channel lengths by taking advantage
of the abruptness of the metallic junctions.
One of the problems observed in bulk SB MOSFET is related to
the large leakage current through the body in the OFF state, what
leads to a low I
on
/I
off
ratio. Recently, ultrathin Schottky barrier
SOI MOSFETs have been studied [14] and a good device operation
at nanoscale dimensions has been found, obtaining higher I
on
/I
off
ratio than in bulk SB MOSFET [15].
It has been shown that for a body thickness small enough the
electrostatic control by the gate causes a signicant reduction in
the Schottky barrier, thus increasing drive current and improving
the subthreshold swing [14]. For these devices, there is no need
for extra doping in the channel and therefore scattering can be de-
creased and, consequently, mobility can be enhanced [8].
0038-1101/$ - see front matter 2011 Elsevier Ltd. All rights reserved.
doi:10.1016/j.sse.2011.06.045
Corresponding author.
E-mail addresses: mbalaguer@ugr.es (M. Balaguer), benjamin.iniguez@urv.cat
(B. Iiguez).
Solid-State Electronics 64 (2011) 7884
Contents lists available at ScienceDirect
Solid-State Electronics
j our nal homepage: www. el sevi er . com/ l ocat e/ sse
One of the main features of these devices is that they show an
ambipolar behavior, meaning that two IV characteristics are ob-
tained with a single device depending on the applied voltages, as
can be seen in Fig. 1.
The transport mechanisms in SB MOSFETs can be described con-
sidering the band structure shown in Fig. 2 [17].
As for a conventional MOSFET, the gate bias modies the chan-
nel surface potential via capacitive coupling. The OFF state is pre-
sented in Fig. 2a. In this case there are neither gate nor drain
source voltages applied.
An important parameter in SB MOSFETs is the barrier for
electrons (/
bn
) between the metal Fermi level in source and drain
and the conduction band in the channel which prevents electrons
from entering and traversing the channel. This barrier is calculated
as follows:
/
bn
WF v
Si
1
where WF is the metal work function. An analog barrier (/
bp
) is
identied for holes, formed between metal Fermi level in the metal
contact and the valence band in the channel.
/
bp
v
Si
E
g
WF 2
In Fig. 2c, the valence band is pushed up as the gate voltages drops
off so that the SB width at the drain contact shrinks and becomes
increasingly transparent for holes. Some energetic holes are then al-
lowed to tunnel the low Schottky barrier for holes /
bp
. These carri-
ers will then drift to the source end of the channel and exit towards
the source metal. In the state depicted in Fig. 2b, the conduction
band is pushed down as the gate voltage rises, reducing the SB
width at the source contact and increasing electron tunneling prob-
ability. We have used different metal work functions to validate our
model; in this respect, in sweeping this parameter we have indi-
rectly included the effects connected with image force and dipole
barrier lowering [17].
In the SB MOSFETs drain current calculation, driftdiffusion
mechanisms can be applied in the channel region, but also a tun-
neling current which injects carriers into and out of the channel
can be identied. As it will be shown below, both current compo-
nents need to be taken into account to accurately model the de-
vices under study. Actually, in the deep subthreshold operation
regime the total current seems to be a combination of the diffusion
and thermionic emission current components.
Furthermore, leakage can be induced via gate-to-drain coupling
at large drain biases and a relatively low or zero gate bias [13], if
the magnitude of the surface potential in the channel-end region
near the drain is large enough to induce band-to-band tunneling
(BTBT). It is also important to highlight that for negative gate volt-
ages holes accumulate at drain/channel interface. In this case the
barrier width for holes decreases and hole tunneling from the drain
side occurs, hence, this mechanism contributes in OFF-state to the
current enhancement.
2. Simulation data
The simulation data presented in this work have been ob-
tained using ATLAS from the Silvaco set of TCAD tools [18]. A
SB DGMOSFET structure has been studied including metallic con-
tacts at the source and drain regions. To make sure the source
and drain contacts behave as Schottky contacts instead of as oh-
mic contacts, a suitable work function has been dened for source
and drain electrodes. The device under study is a NMOS lightly
doped.
In order to avoid convergence problems a ne grid was placed
underneath these contacts. The SB DGMOSFET structure studied
has been simulated considering both electrons and holes. The uni-
versal Schottky tunneling and the band-to-band tunneling mecha-
nisms have been included in the simulations.
3. Model and results
In this paper we have developed a model for long channel SB
DGMOSFETs in order to characterize and model both the electron
and hole currents in the device for the usual operation regimes.
10
-13
10
-12
10
-11
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
10
-4
10
-3
S/D wf = 4.5 eV
-3,0 -2,5 -2,0 -1,5 -1,0 -0,5 0,0 0,5 1,0 1,5 2,0 2,5
V
gs
(V)
L = 3 m t
si
= 30 nm
V
ds
= 0.5 V
V
ds
= 1.0 V
V
ds
= 1.5 V
I
d
s
(
A
)
Fig. 1. Ambipolar behavior in SB MOSFETs. The simulation data have been obtained
from ATLAS for a SB DGMOSFET with the following technological parameters:
t
Si
= 30 nm, L = 3 lm, N
A
= 10
14
cm
3
and S/D metal contact whose work function is
equal to 4.5 eV.
Drain Source
E
c
E
v
E
f d
E
f s
E
c
Drain
Source
E
f d
e
-
E
v
Drain
Source
E
c
E
v
E
f d
E
f s
(a) V
gs
=V
ds
= 0
(b) V
gs
>0 V
ds
> 0
(c) V
gs
<0 V
ds
> 0
h
+
Fig. 2. Energy band diagrams for a SB MOSFET loosely illustrating three different
operation regimes: (a) no drain bias, (b) V
gs
> 0 and V
ds
> 0, (c) V
gs
< 0 and V
ds
> 0.
M. Balaguer et al. / Solid-State Electronics 64 (2011) 7884 79
In this respect, we have identied and modeled the main current
components that contribute to the calculation of the total cur-
rent. The inclusion of the quantum, velocity saturation and short
channel effects needed for the correct description of thin silicon
layers and short channel devices will be considered in future
works as an extension of the model presented here. The use of
a long channel device is the best option to identify and analyze
the different current mechanisms involved in the charge trans-
port since short channel effects can be neglected. All parameters
used in the model presented in this paper do not depend on the
channel length. The short channel version of the model, where
the dependencies on the channel length will show up, is to be
done in the future.
In our case, we present an explicit and analytical model much
more useful from the compact modeling viewpoint. This model dif-
fers from most of the models published so far for SB MOSFETs
[19,14] due to the fact that they are, in general, numerical models
where iterative algorithms have to be used in order to obtain the
main device magnitudes, such us the current and the characteristic
capacitances.
The modeling of SB DGMOSFETs current was performed by sep-
arately modeling the contribution of electrons and holes. For the
electron current calculation we have used as a starting point an
analytical and explicit expression previously published for an un-
doped DGMOSFET [20] (the assumptions considered in the deduc-
tion of this equation are given in [20], among them it is supposed
that we are dealing with long channel lengths):
I
drift diffusion n
Wl
n
L
Q
2
s n
Q
2
d n
4C
ox
2bQ
s n
Q
d n
_ _
b
2
8C
Si
ln
8bC
Si
Q
d n
8bC
Si
Q
s n
_ _
__
3
where b = KT/q. Following a modeling procedure similar to the one
presented in Ref. [20] for the calculation of the electron current, we
have obtained an analog analytical expression for the hole current.
Several investigations have demonstrated that SB MOSFETs
threshold voltage depends on the height of the barrier formed be-
tween the Si and the S/D metallic contact [21]. In order to model
this behavior, we have used as a starting point the threshold volt-
age model presented in Ref. [20] and modied it by introducing a
parameter to account for the barrier height dependence. In this
way, the expressions to model the threshold voltages for electrons
and holes are the following:
V
th n
V
0n
K
n
/
bn
q
2b ln 1
Q
0
n
2Q
0
_ _
4
V
th p
V
0p
K
p
/
bp
q
2b ln 1
Q
0
p
2Q
0
_ _
5
where /
bn
and /
bp
are the Schottky barrier for electrons and holes
calculated in (1) and (2). The values found for the tting parameters
were K
n
= 0.6 and K
p
= 1.
In Eq. (4) the charge Q
0
n
for electrons is calculated as follows
[20]:
Q
0
n
2C
ox
2C
ox
b
2
Q
0
_ _ _
2C
ox
b
2
Q
0
_ _
2
4b
2
log
2
1 exp
V
gs
V
0n
V
2b
_ _ _ _
_
_
6
where b has the same value as presented previously and Q
0
and V
0n
are calculated as follows:
Q
0
4
KT
q
_ _
C
Si
V
0n
D/ bln
qn
i
t
Si
2Q
0
7
In a similar way, Q
0
p
for holes can be obtained as given below:
Q
0
p
2C
ox
2C
ox
b
2
Q
o
_ _ _
2C
ox
b
2
Q
o
_ _
2
4b
2
log
2
1 exp
V
gs
V
0p
V
2b
_ _ _ _
_
_
8
where b and Q
0
are calculated as given before for electrons and V
0p
as follows:
V
0p
D/ b log
qn
i
t
Si
2Q
0
_ _
9
The charges Q
s_p
and Q
d_p
for the drain current calculation are ana-
lytically computed using the following expression by evaluating Q
p
at the source (V = 0, corresponding to Q
s_p
) and at the drain (V = V
ds
,
corresponding to Q
d_p
):
Q
p
2C
ox
2C
ox
b
2
Q
0
_ _ _
2C
ox
b
2
Q
0
_ _
2
4b
2
log
2
1exp
V
gs
V
th p
DV
th p
V
2b
_ _ _ _
_
_
_
_
10
where V
th_p
is given in (5) and DV
th_p
is calculated as follows:
DV
th p
Coxb
2
Q
0
_ _
Q
0
p
Q
0
p
2
Q
0
11
The electron charge calculation follows a similar procedure as de-
scribed in [20].
Once the driftdiffusion components of the current for electrons
and holes have been obtained, we can add them to obtain an ambi-
polar current model accounting only for driftdiffusion mecha-
nisms which will t simulation data well above the threshold
voltage.
We have adapted the driftdiffusion current model to the SB
transistor, to do so, a parameter has been added to the electrons
and holes mobility models (l
n
, l
p
) for the driftdiffusion current
equations to take into account the effect of the Schottky barrier
formed for both type of carriers. In this respect, the electrons and
holes mobilities can then be calculated as follows:
l
SB
n
/
bn
l
n
C
n
D
n
/
bn
l
SB
p
/
bp
l
p
C
p
expd
p
/
bp
12
where C
n
, D
n
, C
p
, d
p
are tting parameters that have the following
values C
n
= 1.62, D
n
= 2.08 (1/eV), C
p
= 194.11 and d
p
= 24.54
(1/eV).
In order to model the subthreshold and near threshold behavior,
we had to introduce further transport mechanisms. Following the
previous modeling scheme, we focus on electrons and holes mech-
anisms separately.
To model the electrons behavior in subthreshold region, we
introduce the tunneling current model [17]:
I
tunneling n
areaAT
2
exp
/
bn
E
00
_ _
exp
V
gs
nkT
_ _
1
_ _
13
80 M. Balaguer et al. / Solid-State Electronics 64 (2011) 7884
A is the Richardson constant (1.20173 10
2
A cm
2
K
2
) [22,23]
and E
00
(eV) is a constant of the material and it is associated with
the WKB expression for the transmission of the barrier for carriers
of energy E = 0). This parameter [24,25] is calculated as:
E
00
a/
bn
q
h
2
N
A
m
e
Si
14
where m