Faculty of Electric and Electronic Engineering

Electronic Engineering Laboratory IV BEE31101 Instruction Sheet

Lab 7 Investigating Instruction Pipelines

Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

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Table of Content
Table of Content Outcomes Instructions Pre-Lab Lab Activities Overview Example Code Assignment1 Assignment2 Observations Questions References ii 1 1 2 3 3 3 5 6 7 9 10

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Outcomes
At the end of this lab, you should be able to: 1. Demonstrate the difference between pipelined and sequential processing of the CPU instructions 2. Explain pipeline data dependency and data hazard 3. Describe a pipeline technique to eliminate data hazard 4. Demonstrate compiler loop unrolling optimizations benefits for instruction pipelining.

Instructions
1. Grouping: Lab group is not predetermine and consists with at most two team members.

2. Pre-Lab: Must be submitted to the instructor at the beginning of lab sessions. Verified by the instructor and returned to the students at the end of lab session. The verified pre-lab will be attached with the final report for submission. 3. Lab Activities: All lab activities such as sample code, examples and lab assignments must be held in the respective lab location and completed within the given times. 4. Demonstration: Student must demonstrate the successful sample code, examples and lab assignments to the respective instructor. Verification only will be given upon completion of all lab activities and initialized by the instructor on the cover page. 5. Report Organization: Report must be organized according to given report template. 6. Report Submission: Report must be received by respective technical staff (at respective lab) before 4.00pm; not later than three (3) days upon completion of lab session.

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Pre-Lab
1. What is the function of instruction pipelines in a computer (2 marks) 2. What are pipeline bubble and data hazards? (3 marks)

Checked by:

Date:

Signature & Lab. Stamp

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Lab Activities
Overview
Modern CPUs incorporate instruction pipelines which are able to process different stages of multi-stages of multiple instructions in parallel thus improving the overall performance of the CPUs. However, most programs include instructions that do not readily lend themselves to smooth pipelining thus causing pipeline hazards and effectively reducing the CPU performance.

Example 1 : Difference between the sequential and pipelined execution of CPU instructions
1. In order to be able to do the following exercises, you need to enter a program which the OS simulator can run.Click on the COMPILER button in the Advanced tab.

2. Enter the following program in the edit window and compile.

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

3. When the above program is successfully compiled, load it in the CPUs memory by clicking on the LOAD IN MEMORY button. This will take to the CPU simulator.

4. Open the CPU pipeline window by clicking on the SHOW PIPELINE button in the CPU simulators window. This window simulates the behavior of CPU pipelined. This pipelined has five stages which are colour-coded as shown in the key for the Pipelines Stages. 5. Check the box title Stay on top and No instruction pipeline.

6. RUN the program and observe the pipeline. Make a note of values in table 1.1.

7. Uncheck the No instruction pipeline checkbox, FLUSH and RUN. Make a note of values in table 1.1.

Table 1.1 No pipeline CPI (Clock Per Instruction) SF (Speed-up Factor) With pipeline

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Assignment 1 : CPU pipeline data hazard, bubbles and NOP instruction

A data hazard is caused by unavailability of an operand value when it is needed. In order to demonstrate this: 1. Create a program (call assignment1) and enter the following set instructions in CPU INSTRUCTION IN MEMORY. MOV #1, R01 MOV #5, R03 MOV #3, R01 ADD R01, R03 HLT 2. Make a note of the expected value in register R03 at the end of the above instructions. Write the value in table 2.1. 3. RUN the instruction, and make sure No instruction pipeline is NOT checked and Do not insert bubbles is checked. Write the value of register R03 in table 2.1. 4. Insert a NOP instruction (use the Miscellaneous tab) as this following instructions. Reset the registers and RUN the instruction. Write the value of register R03 in table 2.1. MOV MOV MOV NOP ADD HLT #1, R01 #5, R03 #3, R01 R01, R03

5. Delete the NOP instruction from above program and uncheck Do not insert bubbles. Reset the registers, RUN and write the value of R03 in table 2.1 6. Have you seen the bubble? What colour is it? Make a note of values in table 2.2.

_______________________________________________________ 7. Check the box Enable operand forwarding, reset the register and run. Make a note of values in table 2.2. 8. What happen to the bubble? __________________________________________________________________

Table 2.1
Predict Without bubble With NOP, without bubble Without NOP, with bubble

R03 value

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Table 2.2 Without operand forwarding CPI (Clock Per Instruction) SF (Speed-up Factor) Data hazard With operand forwarding

Assignment 2: Loop unrolling optimization minimizing control dependencies

One method of compiler optimization called loop unrolling. This method essentially duplicates the inner code of a loop as many times as the number of loops, removing some redundant code as well as the loops compare and jump instructions. We will see if loop unrolling technique can affected the CPU performance. 1. Enter the following code, check enable optimizer, select optimization option Remove Redundant Code and compile and load this code in memory. Write the size of the code generated in table 2.3. program assignment2 for n = 1 to 8 t = t +1 next end 2. In the CPU simulator window select program assignment2 from the Program list frame, then click Reset button. Make sure the speed of simulation is set at maximum. 3. Click Show pipeline button and make sure the pipeline window stay on top, Uncheck boxes of No instruction pipeline, Enable operand forwarding and Enable jump prediction. 4. Write the result in table 2.3 5. Change the program name to assignment 2b, follow the step 1 to 3. BUT in step 1, check the boxes enable optimizer, select optimization option Remove Redundant Code and Apply loop unrolling on loop. Write the result in table 2.4

Table 2.3 Program Assignment 2 CPI (clock Per Instruction) SF (Speed-up Factor) No. of Instruction Executed Size of the code generated FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Table 2.4 Program Assignment 2b CPI (clock Per Instruction) SF (Speed-up Factor) No. of Instruction Executed Size of the code generated

Observations
1. Explain why there is difference in the two sets of values in table 1.1 of Example 1.

(4 marks) 2. Refer to the assignment 1, briefly comment on your observation the four value of the register R03 in table 2.1.

(4 marks) 3. What is the effect of operand forwarding method on the CPU performance as refer the result in table 2.2.

(3 marks) FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

4. Give the comment on your observations making reference to the code sizes and number of instruction executed for Assignment 2.

(3 marks) Conclusion (write the conclusion for this lab)

(5 marks)

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

Questions
1. Write a program for the following arithmetic operation and predict the value of register R01. R01 = 4 * (5+2) 3 Instruction Set

(5 marks)

R01 : ________________________________________ (2 marks) 2. By using Instruction Memory View: a) Create the program arithmetic operation above and RUN. Prove the content of register R01 is the same with the prediction value.

(print screen the code and Register R01) (4 marks)

b) Find the value of data hazard for: i) Instruction pipeline with bubbles and without operand forwarding method

(print screen the pipeline result)

(2 marks)

ii)

Instruction pipeline with bubble and operand forwarding method

(print screen the pipeline result)

(2 marks)

FKEE, Sem02 Session 2012/13

Electronic Engineering Laboratory IV (BEE31101)

Lab 7: Investigating Instruction Pipelines

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References
1. W. Stalling (2013). Computer Organization & Architecture;Designing for Performance. 9th Edition. Pearson Prentice Hall. 2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Nraig Manjikian (2012). Computer Organization and Embedded Systems. 6th Edition. The McGraw-Hill Companies.

FKEE, Sem02 Session 2012/13