CA3160, CA3160A

Data Sheet October 2002 FN976.4

4MHz, BiMOS Operational Amplifier with MOSFET Input/CMOS Output

The CA3160A and CA3160 are integrated circuit operational amplifiers that combine the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA3160 series are frequency compensated versions of the popular CA3130 series. Gate protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common-mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A complementary symmetry MOS (CMOS) transistor-pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA3160 Series circuits operate at supply voltages ranging from 5V to 16V, or 2.5V to 8V when using split supplies, and have terminals for adjustment of offset voltage for applications requiring offset null capability. Terminal provisions are also made to permit strobing of the output stage. The CA3160A offers superior input characteristics over those of the CA3160.

Features
MOSFET Input Stage Provides: - Very High ZI = 1.5T (1.5 x 1012) (Typ) - Very Low II . . . . . . . . . . . . . 5pA (Typ) at 15V Operation . . . . . . . . . . . . . . . . . . . . . . . 2pA (Typ) at 5V Operation Common-Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can Be Swung 0.5V Below Negative Supply Rail CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails

Applications
Ground Referenced Single Supply Amplifiers Fast Sample Hold Amplifiers Long Duration Timers/Monostables High Input Impedance Wideband Amplifiers Voltage Followers (e.g., Follower for Single Supply D/A Converter) Wien-Bridge Oscillators Voltage Controlled Oscillators Photo Diode Sensor Amplifiers

Pinout
CA3160 (PDIP) TOP VIEW
OFFSET NULL INV. INPUT NON-INV. INPUT V-

Ordering Information
PART NUMBER CA3160AE CA3160E TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 8 Ld PDIP 8 Ld PDIP PKG. NO. E8.3 E8.3
1 2 3 4

STROBE V+ OUTPUT OFFSET NULL

7 6 5

NOTE: CA3160 Series devices have an on-chip frequency compensation network. Supplementary phase compensation or frequency roll-off (if desired) can be connected externally between Terminals 1 and 8.

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002. All Rights Reserved

CA3160, CA3160A
Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) . . . . . . . . . . . .+16V Differential Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . .8V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V) Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA Output Short Circuit Duration (Note 2). . . . . . . . . . . . . . . . Indefinite Operating Conditions Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 115 N/A Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

NOTES: 1. JA is measured with the component mounted on an evaluation PC board in free air. 2. Short Circuit may be applied to ground or to either supply.

Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Large-Signal Voltage Gain

TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified CA3160 SYMBOL |VIO| |IIO| II AOL TEST CONDITIONS VS = 7.5V VS = 7.5V VS = 7.5V VO = 10VP-P , RL = 2k MIN 50 94 TYP 6 0.5 5 320 110 90 -0.5 to 12 32 13.3 0.002 15 0 22 20 10 2 8 MAX 15 30 50 10 320 0.01 0.01 45 45 15 3 MIN 50 94 80 0 12 14.99 12 12 CA3160A TYP 2 0.5 5 320 110 95 -0.5 to 12 32 13.3 0.002 15 0 22 20 10 2 6 MAX 5 20 30 10 150 0.01 0.01 45 45 15 3 UNITS mV pA pA kV/V dB dB V V/V V V V V mA mA mA mA V/oC

Common-Mode Rejection Ratio Common-Mode Input-Voltage Range Power-Supply Rejection Ratio Maximum Output Voltage

CMRR VlCR PSRR VOM+ VOMVOM+ VOMRL = VIO/VS, VS = 7.5V RL = 2k

70 0 12 14.99 VO = 0V (Source) VO = 15V (Sink) VO = 7.5V, R L = VO = 0V, R L = 12 12 -

Maximum Output Current

IOM+ IOM-

Supply Current (Note 3)

I+

Input Offset Voltage Temperature Drift

VIO/T

Electrical Specifications
PARAMETER

For Design Guidance, VSUPPLY = 7.5V, TA = 25oC, Unless Otherwise Specified CA3160 SYMBOL TEST CONDITIONS 10k Across Terminals 4 and 5 or Terminals 4 and 1 RI CI eN f = 1MHz BW = 0.2MHz RS = 1M RS = 10M TYP 22 1.5 4.3 40 50 72 30 CA3160A TYP 22 1.5 4.3 40 50 72 30 UNITS mV T pF V V nV/Hz nV/Hz

Input Offset Voltage Adjustment Range Input Resistance Input Capacitance Equivalent Input Noise Voltage

Equivalent Input Noise Voltage

eN

RS = 100

1kHz 10kHz

CA3160, CA3160A
Electrical Specifications
PARAMETER Unity Gain Crossover Frequency Slew Rate Transient Response Rise and Fall Time Overshoot Settling Time For Design Guidance, VSUPPLY = 7.5V, TA = 25oC, Unless Otherwise Specified (Continued) CA3160 SYMBOL fT SR tr OS tS CL = 25pF, RL = 2k , (Voltage Follower) To <0.1%, VIN = 4VP-P CL = 25pF, RL = 2k , (Voltage Follower) TEST CONDITIONS TYP 4 10 0.09 10 1.8 CA3160A TYP 4 10 0.09 10 1.8 UNITS MHz V/s s % s

Electrical Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Current Common-Mode Rejection Ratio Large Signal Voltage Gain

For Design Guidance, V+ = +5V, V- = 0V, TA = 25oC, Unless Otherwise Specified CA3160 SYMBOL VIO IIO Il CMRR AOL VO = 4VP-P , RL = 5k TEST CONDITIONS TYP 6 0.1 2 80 100 100 CA3160A TYP 2 0.1 2 90 100 100 0 to 2.8 300 500 200 UNITS mV pA pA dB kV/V dB V A A V/V

Common-Mode Input Voltage Range Supply Current

VlCR I+ VO = 5V, RL = VO = 2.5V, RL =

0 to 2.8 300 500 200

Power Supply Rejection Ratio NOTE:

PSRR

VIO/V+

3. ICC typically increases by 1.5mA/MHz during operation.

Block Diagram
7 200A 1.35mA 200A 8mA (NOTE 4) 0mA (NOTE 5) V+

NOTES: 4. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 5. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail.

BIAS CKT.

+ 3 INPUT 2 AV 5X AV 6000X AV 30X

OUTPUT 6

4 CC 5 1 COMPENSATION (WHEN DESIRED) 8 STROBE

V-

OFFSET NULL

CA3160, CA3160A Schematic Diagram

BIAS CURRENT CURRENT SOURCE FOR Q6 AND Q7 CURRENT SOURCE LOAD FOR Q11 Q3 7 V+

Q1 D1 D2 D3 R1 40k R2 5k D4

Q2

Z1 8.3V

Q4

Q5

INPUT STAGE D5 NON-INV. INPUT 3 2 + Q6

D6

D7

SECOND STAGE OUTPUT STAGE

Q8 OUTPUT 6

Q7

2k R4 1k Q10 30 pF Q11 Q12

R3 1k Q9

INV. INPUT

R5 1k

R6 1k SUPPLEMENTARY COMP IF DESIRED

5 OFFSET NULL

8 STROBING

NOTE: Diodes D5 Through D7 Provide Gate Oxide Protection For MOSFET Input Stage.

Application Information
Circuit Description
Refer to the Block Diagram of the CA3160 series CMOS Operational Amplifiers. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA3160 series circuits are ideal for single supply operation. Three class A amplifier stages, having the individual gain capability and current consumption shown in the Block Diagram provide the total gain of the CA3160. A biasing circuit provides two potentials for common use in the first and second stages. Terminals 8 and 1 can be used to supplement the internal phase compensation network if additional phase compensation or frequency roll-off is desired. Terminals 8 and 4 can also be used to strobe the output stage into a low quiescent current state. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supplyrail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed OFF condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g., when the amplifier output is used to drive MOS digital circuits in comparator applications). Input Stage - The circuit of the CA3160 is shown in the Schematic Diagram. It consists of a differential-input stage using PMOS field-effect transistors (Q6, Q7) working into a mirror-pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirrorpair transistors also function as a differential-to-single-ended converter to provide base drive to the second-stage bipolar transistor (Q11). Offset nulling, when desired, can be effected by connecting a 100,000 potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascode-connected PMOS transistors Q2, Q4, are the constant-current source for the input stage. The biasing circuit for the constant-current source is subsequently described. The small diodes D5 through D7 provide gate-oxide protection against high-voltage transients, including static electricity during handling for Q6 and Q7. Second-Stage - Most of the voltage gain in the CA3160 is provided by the second amplifier stage, consisting of bipolar

CA3160, CA3160A
transistor Q11 and its cascode-connected load resistance provided by PMOS transistors Q3 and Q5. The source of bias potentials for these PMOS transistors is described later. Miller Effect compensation (roll off) is accomplished by means of the 30pF capacitor and 2k resistor connected between the base and collector of transistor Q11. These internal components provide sufficient compensation for unity gain operation in most applications. However, additional compensation, if desired, may be used between Terminals 1 and 8. Bias-Source Circuit - At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series-connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate-bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode-connected PMOS transistor Q1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q3. It should be noted that Q1 is mirror-connected to both Q2 and Q3. Since transistors Q1, Q2, Q3 are designed to be identical, the approximately 200A current in Q1 establishes a similar current in Q2 and Q3 as constant-current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series-connected R1, D1 - D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q5 and Q2, Q3 varies in accordance with supplyvoltage variations. This variation results in deterioration of the power-supply-rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance. Output Stage - The output stage consists of a drain-loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance loads, the output can be swung within millivolts of either supply rail. Because the output stage is a drain-loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 17. Typical op amp loads are readily driven by the output stage. Because largesignal excursions are non-linear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail.

Input Current Variation with Common Mode Input Voltage

As shown in the Electrical Specifications, the input current for the CA3160 Series Op Amps is typically 5pA at TA = 25oC when Terminals 2 and 3 are at a common-mode potential of +7.5V with respect to negative supply Terminal 4. Figure 23 contains data showing the variation of input current as a function of common-mode input voltage at TA = 25oC. These data show that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common-mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate-protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gateprotection network functions as if it is connected to Terminal 4 potential, and the metal can case of the CA3160 is also internally tied to Terminal 4, input Terminal 3 is essentially guarded from spurious leakage currents.

Input-Current Variation with Temperature

The input current of the CA3160 Series circuits is typically 5pA at 25oC. The major portion of this input current is due to leakage current through the gate-protective diodes in the input circuit. As with any semiconductor junction device, including op amps with a junction-FET input stage, the leakage current approximately doubles for every 10oC increase in temperature. Figure 24 provides data on the typical variation of input bias current as a function of temperature in the CA3160. In applications requiring the lowest practical input current and incremental increases in current because of warm-up effects, it is suggested that an appropriate heat sink be used with the CA3160. In addition, when sinking or sourcing significant output current the chip temperature increases, causing an increase in the input current. In such cases, heat-sinking can also very markedly reduce and stabilize input current variations.

Input Offset Voltage (VIO) Variation with DC Bias vs Device Operating Life
It is well known that the characteristics of a MOSFET device can change slightly when a DC gate-source bias potential is applied to the device for extended time periods. The magnitude of the change is increased at high temperatures. Users of the CA3160 should be alert to the possible impacts of this effect if the application of the device involves extended operation at high temperatures with a significant differential DC bias voltage applied across Terminals 2 and 3. Figure 25 shows typical data pertinent to shifts in offset voltage encountered with CA3160 devices in metal can packages during life testing. At lower temperatures (metal can and plastic) for example at 85oC, this change in voltage is considerably less. In typical linear applications where the differential voltage is small and symmetrical, these incremental changes are of about the same

Offset Nulling
Offset-voltage nulling is usually accomplished with a 100,000 potentiometer connected across Terminals 1 and 5 and with the potentiometer slider arm connected to Terminal 4. A fine offset-null adjustment usually can be effected with the slider arm positioned in the mid-point of the potentiometer's total range.

CA3160, CA3160A
magnitude as those encountered in an operational amplifier employing a bipolar transistor input stage. The 2V differential voltage example represents conditions when the amplifier output state is toggled, e.g., as in comparator applications. voltages. Figure 17 shows the voltage transfer characteristics of the output stage for several values of load resistance.

Wideband Noise
From the standpoint of low-noise performance considerations, the use of the CA3160 is most advantageous in applications where in the source resistance of the input signal is on the order of 1M or more. In this case, the total input-referred noise voltage is typically only 40V when the test circuit amplifier of Figure 2 is operated at a total supply voltage of 15V. This value of total input-referred noise remains essentially constant, even though the value of source resistance is raised by an order of magnitude. This characteristic is due to the fact that reactance of the input capacitance becomes a significant factor in shunting the source resistance. It should be noted, however, that for values of source resistance very much greater than 1M, the total noise voltage generated can be dominated by the thermal noise contributions of both the feedback and source resistors.

Power Supply Considerations

Because the CA3160 is very useful in single supply applications, it is pertinent to review some considerations relating to power supply current consumption under both single and dual supply service. Figures 1A and 1B show the CA3160 connected for both dual and single supply operation. Dual-supply operation: When the output voltage at Terminal 6 is 0V, the currents supplied by the two power supplies are equal. When the gate terminals of Q8 and Q12 are driven increasingly positive with respect to ground, current flow through Q12 (from the negative supply) to the load is increased and current flow through Q8 (from the positive supply) decreases correspondingly. When the gate terminals of Q8 and Q12 are driven increasingly negative with respect to ground, current flow through Q8 is increased and current flow through Q12 is decreased accordingly. Single supply operation: Initially, let it be assumed that the value of RL is very high (or disconnected), and that the inputterminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2, i.e., the voltage-drops across Q8 and Q12 are of equal magnitude. Figure 18 shows typical quiescent supply-current vs supply voltage for the CA3160 operated under these conditions. Since the output stage is operating as a Class A amplifier, the supply current will remain constant under dynamic operating conditions as long as the transistors are operated in the linear portion of their voltage-transfer characteristics (see Figure 17). If either Q8 or Q12 are swung out of their linear regions toward cutoff (a non-linear region), there will be a corresponding reduction in supply-current. In the extreme case, e.g., with Terminal 8 swung down to ground potential (or tied to ground), NMOS transistor Q12 is completely cut off and the supply current to series connected transistors Q8, Q12 goes essentially to zero. The two preceding stages in the CA3160, however, continue to draw modest supply-current (see the lower curve in Figure 18) even though the output stage is strobed off. Figure 1A shows a dual-supply arrangement for the output stage that can also be strobed off, assuming RL = , by pulling the potential of Terminal 8 down to that of Terminal 4. Let it now-be assumed that a load resistance of nominal value (e.g., 2k) is connected between Terminal 6 and ground in the circuit of Figure 1B. Let it further be assumed again that the input-terminal bias (Terminals 2 and 3) is such that the output terminal (No. 6) voltage is at V+/2. Since PMOS transistor Q8 must now supply quiescent current to both RL and transistor Q12, it should be apparent that under these conditions the supply current must increase as an inverse function of the RL magnitude. Figure 20 shows the voltage-drop across PMOS transistor Q8 as a function of load current at several supply 6

7 3 + Q8 CA3160

V+

OUTPUT Q12 STAGE

RL 2

4 VNEGATIVE SUPPLY

FIGURE 1A. DUAL POWER SUPPLY OPERATION

V+ 7 3 + Q8 CA3160 OUTPUT Q12 STAGE 6 RL 2

FIGURE 1B. SINGLE POWER SUPPLY OPERATION FIGURE 1. CA3160 OUTPUT STAGE IN DUAL AND SINGLE POWER SUPPLY OPERATION

CA3160, CA3160A
+7.5V 0.01F 3 1M 2 7 + CA3160 6 4 0.01 F -7.5V BW (3dB) = 200kHz TOTAL NOISE VOLTAGE (INPUT REFERRED = 40V (TYP) 1k 30.1k NOISE VOLTAGE OUTPUT

RS

FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENTS

Typical Performance Curves

+7.5V 0.01F 3 10k 2 7 + CA3160 6 4 0.01 F -7.5V 2k BW (-3dB) = 4MHz SR = 10V/s 25pF SIMULATED LOAD CAPACITANCE

2k

0.1F

FIGURE 3A.

Top Trace: Output Bottom Trace: Input FIGURE 3B. SMALL SIGNAL RESPONSE

Top Trace: Output Signal Center Trace: Difference Signal 5mV/Div. Bottom Trace: Input Signal FIGURE 3C. INPUT-OUTPUT DIFFERENCE SIGNAL SHOWING SETTLING TIME

FIGURE 3. DUAL SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS

CA3160, CA3160A Typical Applications

Voltage Followers
Operational amplifiers with very high input resistances, like the CA3160, are particularly suited to service as voltage followers. Figure 3 shows the circuit of a classical voltage follower, together with pertinent waveforms using the CA3160 in a split-supply configuration. A voltage follower, operated from a single supply, is shown in Figure 4 together with related waveforms. This follower circuit is linear over a wide dynamic range, as illustrated by the reproduction of the output waveform in Figure 4B with inputsignal ramping. The waveforms in Figure 4C show that the follower does not lose its input-to-output phase-sense, even though the input is being swung 7.5V below ground potential. This unique characteristic is an important attribute in both operational amplifier and comparator applications. Figure 4C also shows the manner in which the COS/MOS output stage permits the output signal to swing down to the negative supply-rail potential (i.e., ground in the case shown). The digital-to-analog converter (DAC) circuit, described in the following section, illustrates the practical use of the CA3160 in a single supply voltage follower application.
3 10k 2 7 + CA3160 6 4 5 1 OFFSET ADJUST 2k BW (-3dB) = 4MHz SR = 10V/s 0.1F +15V 0.01F

FIGURE 4A.

9-Bit CMOS DAC

A typical circuit of a 9-bit Digital-to-Analog Converter (DAC) (see Note 6) is shown in Figure 5. This system combines the concepts of multiple-switch CMOS lCs, a low-cost ladder network of discrete metal-oxide-film resistors, a CA3160 op amp connected as a follower, and an inexpensive monolithic regulator in a simple single power-supply arrangement. An additional feature of the DAC is that it is readily interfaced with CMOS input logic, e.g., 10V logic levels are used in the circuit of Figure 5. The circuit uses an R/2R voltage-ladder network, with the outputpotential obtained directly by terminating the ladder arms at either the positive or the negative power supply terminal. Each CD4007A contains three inverters, each inverter functioning as a single-pole double-throw switch to terminate an arm of the R/2R network at either the positive or negative power-supply terminal. The resistor ladder is an assembly of 1% tolerance metal-oxide film resistors. The five arms requiring the highest accuracy are assembled with series and parallel combinations of 806,000 resistors from the same manufacturing lot. A single 15V supply provides a positive bus for the CA3160 follower amplifier and feeds the CA3085 voltage regulator. A scale-adjust function is provided by the regulator output control, set to a nominal 10V level in this system. The line-voltage regulation (approximately 0.2%) permits a 9-bit accuracy to be maintained with variations of several volts in the supply. The flexibility afforded by the CMOS building blocks simplifies the design of DAC systems tailored to particular needs.
NOTE: 6. Digital-to-Analog Conversion Using the Intersil CD4007A COS/MOS lC, Application Note AN6080.

Top Trace: Output Bottom Trace: Input FIGURE 4B. OUTPUT WAVEFORM WITH GROUND REFERENCE SINE WAVE INPUT

FIGURE 4C. OUTPUT SIGNAL WITH INPUT SIGNAL RAMPING FIGURE 4. SINGLE SUPPLY VOLTAGE FOLLOWER WITH ASSOCIATED WAVEFORMS. (E.G., FOR USE IN SINGLE SUPPLY D/A CONVERTER; SEE FIGURE 9 IN AN6080)

CA3160, CA3160A
10V LOGIC INPUTS +10.010V LSB 9 6 8 3 CD4007A SWITCHES 9 7 4 13 8 806K 1% 806K 1% VOLTAGE REGULATOR 2 CA3085 3 7 + 2F 25V 4 0.001F 6 1 8 22.1K 1% 1K REGULATED VOLTAGE ADJUST 3.83K 1% 1 5 402K 1% 200K 1% 12 13 8 100K 1% 806K 1% 7 10 2 CD4007A SWITCHES 1 5 1% 806K 1% 750K 1% 806K 1% 12 806K 13 8 (2) 806K 1% CD4007A SWITCHES 1 5 (4) 806K 1% (8) 806K 1% +15V PARALLELED RESISTORS OUTPUT 6 4 5 LOAD 100K OFFSET NULL 1 7 + CA3160 3 VOLTAGE FOLLOWER 2 10K 12 14 11 6 6 5 3 4 10 3 6 2 3 MSB 1 10

+15V

62 +10.010V

BIT 1 2 3 4 5 6-9

REQUIRED RATIO-MATCH Standard 0.1% 0.2% 0.4% 0.8% 1% ABS.

2K 0.1F

FIGURE 5. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3160

Error-Amplifier in Regulated Power Supplies

The CA3160 is an ideal choice for error-amplifier service in regulated power supplies since it can function as an erroramplifier when the regulated output voltage is required to approach zero. The circuit shown in Figure 6 uses a CA3160 as an error amplifier in a continuously adjustable 1A power supply. One of the key features of this circuit is its ability to regulate down to the vicinity of 0V with only one DC power supply input. An RC network, connected between the base of the output drive transistor and the input voltage, prevents turn-on overshoot, a condition typical of many operational amplifier regulator circuits. As the amplifier becomes operational, this RC network ceases to have any influence on the regulator performance.

conditions such that EAVG = V1. This circuit condition is accomplished by feeding an output signal from Terminal 6 of A2 through R4, D4 to the inverting terminal (Terminal 2) of A1, thereby adjusting the multivibrator interval, T3.

Voltmeter With High Input Resistance

The voltmeter circuit shown in Figure 8 illustrates an application in which a number of the CA3160 characteristics are exploited. Range-switch SW1 is ganged between input and output circuitry to permit selection of the proper output voltage for feedback to Terminal 2 via 10k current-limiting resistor. The circuit is powered by a single 8.4V mercury battery. With zero input signal, the circuit consumes somewhat less than 500A plus the meter current required to indicate a given voltage. Thus, at full scale input, the total supply current rises to slightly more than 1500A.

Precision Voltage-Controlled Oscillator

The circuit diagram of a precision voltage-controlled oscillator is shown in Figure 7. The oscillator operates with a tracking error in the order of 0.02% and a temperature coefficient of 0.01%/oC. A multivibrator (A1) generates pulses of constant amplitude (V) and width (T2). Since the output (Terminal 6) of A1 (a CA3130) can swing within about 10mV of either supplyrail, the output pulse amplitude (V) is essentially equal to V+. The average output voltage (EAVG = V T2/T1) is applied to the non-inverting Input terminal of comparator A2 via an integrating network R3, C2. Comparator A2 operates to establish circuit 9

Function Generator
A function generator having a wide tuning range is shown in Figure 9. The adjustment range, in excess of 1,000,000/1, is accomplished by a single potentiometer. Three operational amplifiers are utilized: a CA3160 as a voltage follower, a CA3080 as a high speed comparator, and a second CA3080A as a programmable current source. Three variable capacitors C1, C2, and C3 shape the triangular signal between 500kHz and 1MHz. Capacitors C4, C5, and the trimmer potentiometer in series with C5 maintain essentially constant (+10%) amplitude up to 1MHz.

CA3160, CA3160A
2N6385 POWER DARLINGTON 2 0.2F 2.4k 1W TURN ON DELAY 1 10k 1k OUTPUT 0V TO 35V AT 1A

3 40V INPUT +

SHORT-CIRCUIT CURRENT LIMIT ADJUSTMENT

100k

1.5k 1W

1k

2N2102 56pF 43k + 100F

1N914 2.2k 100F 25V + 7 + 5F 10 CA3086 11 2 2k 6 2N2102 9 7 6 3 5 4 1k 62k 5 1 12 14 13 50k 100k 10k 4.7k 4 8

10k + CA3160 3

2 8.2k

0.01F

Hum and Noise Output <250VRMS; Regulation (No Load to Full Load) <0.005%; Input Regulation <0.01%/V FIGURE 6. VOLTAGE REGULATOR CIRCUIT (0.1V TO 35V AT 1A)
T2 V +15V D1 T1 10K +15V 100K 3 R6 100K C1 500pF 2 D2 + MULTIVIBRATOR CA3130 7 +15V 0.1 F 6 R3 1M 4 C2 0.01F R1 182K R2 10K 3 2 EAVG = V T2/T1 T3 fO VCO CONTROL VOLTAGE (VI) (0V - 10V) (SENSITIVITY = 1kHz/V) 1M 0.01F R5 100K

7 6

COMPARATOR CA3160 + 4 5 1 R7 100K

0.01F

D3 D5

D4

R4 3K

D1 - D5 = 1N914

FIGURE 7. VOLTAGE CONTROLLED OSCILLATOR

10

CA3160, CA3160A
BATTERY TEST OFF ON 3 POSITION SLIDE SWITCH + 500 F M 0-1mA 2.7k 6 4 5 1 300V 100V 30V 10V 100k ZERO ADJUST 9.1k SW1C 3V 1V 300mV 100mV 10k 30mV 10mV 100 900 9k 820 200 1V CAL. 3V CAL. 500 300V 100V 30V 10V 3V 1V 300mV 100mV 30mV 10mV SW1D

300V 100V 30V 10V

100M

300V 100V 30V

1.02 M

10V

9.9k

3V 1V 300V 100V 30V 10V SW1B 3 22M 0.001F 2 +9V BATTERY 7 + CA3160 BATTERY

SW1A 3V INPUT 1V 300V 100V 30V 10V

FIGURE 8. HIGH INPUT RESISTANCE DC VOLTMETER

20pF

8.2k +7.5V VOLTAGE-CONTROLLED CURRENT SOURCE 7 3 1k 1k 2 2M SYMMETRY -7.5V 100k +7.5V + CA3080A 6 4 5 -7.5V 4.7k 10-80pF C2 6.2k 0.9 - 7pF C1

BUFFER VOLTAGE FOLLOWER +7.5V HIGH FREQ. SHAPE 3 + 6 0.1F

CENTERING 100k -7.5V 430pF 6.8M

THRESHOLD DETECTOR +7.5V +7.5V 30k

5 10k 2 7

4 - 60pF CA3160 C3 2 4

CA3080 6 -7.5V +

EXTERNAL SWEEPING INPUT -7.5V

0.1F C4 4 - 60pF 2k HIGH FREQ LEVEL ADJUST

10k

50k C5 15 - 115pF

2-1N914

MAX FREQ SET +7.5V 10k 6.2k

MIN FREQ.SET 500 FREQ ADJUST -7.5V 500

FIGURE 9A. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz

11

CA3160, CA3160A

NOTE: A square wave signal modulates the external sweeping input to produce 1Hz and 1MHz, showing the 1,000,000/1 frequency range of the Function Generator. FIGURE 9B. TWO-TONE OUTPUT SIGNAL FROM THE FUNCTION GENERATOR

NOTE: The bottom trace is the sweeping signal and the top trace is the actual generator output. The center trace displays the 1MHz signal via delayed oscilloscope triggering of the upper swept output signal. FIGURE 9C. TRIPLE-TRACE OF THE FUNCTION GENERATOR SWEEPING TO 1MHz

FIGURE 9. 1,000,000/1 SINGLE CONTROL FUNCTION GENERATOR: 1Hz to 1MHz

5.1k +15V +15V 100 k 100 k 1M 7 + CA3130 2 15 - 115pF FREQ ADJUST 6 8 STEP HEIGHT ADJUST 4 - 60pF 8.2k 2 1N914 3 4 +15V 7 7 470pF STAIRCASE OUTPUT +15V

1N914

3 100 k

CA3160 + 4 6 2k

10k 3 +15V 1.5 M 2 + CA3130 6 8 4

MULTIVIBRATOR

CHARGE COMMUTATING NETWORK MULTIVIBRATOR RETRACE INHIBIT

INTEGRATOR HYSTERESIS SWITCH 51k 100k

+15mV TO +10V

FIGURE 10A. STAIRCASE GENERATOR CIRCUIT

12

CA3160, CA3160A
Terminals 2 and 4 of the CA3160 at ground potential, the CA3160 input is operated in the guarded mode. Under this operating condition, even slight leakage resistance present between Terminals 3 and 2 or between Terminals 3 and 4 would result in zero voltage across this leakage resistance, thus substantially reducing the leakage current. If the CA3160 is operated with the same voltage on input Terminals 3 and 2 as on Terminal 4, a further reduction in the input current to the less than one picoampere level can be achieved as shown in Figure 23. To further enhance the stability of this circuit, the CA3160 can be operated with its output (Terminal 6) near ground, thus markedly reducing the dissipation by reducing the supply current to the device. The CA3140 stage serves as a X100 gain stage to provide the required plus and minus output swing for the meter and feedback network. A 100-to-1 voltage divider network consisting of a 9.9k resistor in series with a 100 resistor sets the voltage at the 10G resistor (in series with Terminal 3) to 30mV full-scale deflection. This 30mV signal results from 3V appearing at the top of the voltage divider network which also drives the meter circuitry. By utilizing a switching technique in the meter circuit and in the 9.9k and 100 network similar to that used in voltmeter circuit shown in Figure 8, a current range of 3pA to 1nA full scale can be handled with the single 10G resistor.

STAIRCASE OUTPUT 2V STEPS

COMPARATOR OSCILLATOR

Top Trace: Staircase Output 2V Steps Center Trace: Comparator Bottom Trace: Oscillator FIGURE 10B. STAIRCASE GENERATOR WAVEFORM FIGURE 10. STAIRCASE GENERATOR CIRCUIT

Staircase Generator
Figure 10 shows a staircase generator circuit utilizing three CMOS operational amplifiers. Two CA3130s are used; one as a multivibrator, the other as a hysteresis switch. The third amplifier, a CA3160, is used as a linear staircase generator.

Picoammeter Circuit
Figure 11 is a current-to-voltage converter configuration utilizing a CA3160 and CA3140 to provide a picoampere meter for 13pA full scale meter deflection. By placing
10G

+15V 0.1F 10M 3 + CA3160 2 6 4 5 1 100k 9.1k 7

1M 10pF +15V 7 10k 2

CA3140 6 9.9k 0.1F 4 500 100 M 500-0-500A 5.6k +

3 560k

-15V

-15V

FIGURE 11. CURRENT-TO-VOLTAGE CONVERTER TO PROVIDE A PICOAMMETER WITH 3pA FULL SCALE DEFLECTION

13

CA3160, CA3160A
+15V 100k +15V 2200pF 30pF 1M 3 + CA3160 2 6 8 4 5 1 100k OFFSET VOLTAGE ADJUST 9.1k 8.2k 0.1F 27k 500A STROBE INPUT 2k SAMPLE = 15V HOLD = 0V 5 DROOP ZERO ADJUST 39k 3 2 7 0.1F 0.1F 39k 7 6 100k 1M 3 0.1F 2 8.2 +15V

0.1F 7

1N914 +

CA3080A 4

CA3140 + 4 6

FIGURE 12A. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V

SAMPLED OUTPUT

SAMPLED OUTPUT 0VINPUT 0V-

INPUT SIGNAL

SAMPLING PULSES

SAMPLING PULSES

Top Trace: Sampled Output Center Trace: Input Signal Bottom Trace: Sampling Pulses FIGURE 12B. SAMPLE AND HOLD WAVEFORM

Top Trace: Sampled Output Center Trace: Input Signal Bottom Trace: Sampling Pulses FIGURE 12C. SAMPLE AND HOLD WAVEFORM

FIGURE 12. SINGLE SUPPLY SAMPLE AND HOLD SYSTEM, INPUT 0V TO 10V

Single Supply Sample-and-Hold System

Figure 12 shows a single supply sample-and-hold system using a CA3160 to provide a high input impedance and an input voltage range of 0V to 10V. The output from the input buffer integrator network is coupled to a CA3080A. The CA3080A functions as a strobeable current source for the CA3140 output integrator and storage capacitor. The CA3140 was chosen because of its low output impedance and constant gain-bandwidth product. Pulse droop during the hold interval can be reduced to zero by adjusting the 100k bias-voltage potentiometer on the positive input of the CA3140. This zero adjustment sets the CA3080A output voltage at its zero current position. In this sample-and-hold circuit it is essential that the amplifier bias current be reduced to zero to minimize output signal current during the

hold mode. Even with 320mV at the amplifier bias circuit terminal (5) at least 1100pA of output current will be available.

Wien Bridge Oscillator

A simple, single supply Wien Bridge oscillator using a CA3160 is shown in Figure 13. A pair of parallel-connected 1N914 diodes comprise the gain-setting network which standardizes the output voltage at approximately 1.1V. The 500 potentiometer is adjusted so that the oscillator will always start and the oscillation will be maintained. Increasing the amplitude of the voltage may lower the threshold level for starting and for sustaining the oscillation, but will introduce more distortion.

14

CA3160, CA3160A
Operation with Output Stage Power Booster
R1 100k R3 51k C2 51pF 3 2 + CA3160 R2 100k C1 10-80 pF 6 4 2k 2-1N914 0.01F 680 f= 1 2 (R1 || R2) C1 R3 C2 500 7 +15V 0.1 F OUTPUT f = 100kHz 2% THD AT 1.1VP-P

The current sourcing and sinking capability of the CA3160 output stage is easily supplemented to provide power-boost capability. In the circuit of Figure 14, three CMOS transistorpairs in a single CA3600 lC array are shown parallel-connected with the output stage in the CA3160. In the Class A mode of CA3600E shown, a typical device consumes 20mA of supply current at 15V operation. This arrangement boosts the currenthandling capability of the CA3160 output stage by about 2.5X. The amplifier circuit in Figure 14 employs feedback to establish a closed-loop gain of 20dB. The typical largesignal-bandwidth (-3dB) is 190kHz.

FIGURE 13. SINGLE SUPPLY WEIN BRIDGE OSCILLATOR

+15V 0.01F 1M 1F CA3600 + 7 680k 3 INPUT 1F 2k 2 + CA3160 6 8 4 8 A = 20dB LARGE SIGNAL BW (-3dB) = 190kHz QN1 5 QN2 QN3 6 13 1 500F 3 10 12 50 100mW AT 10% THD QP1 QP2 QP3

14

11

7 20k

FIGURE 14. CMOS TRANSISTOR ARRAY (CA3600E) CONNECTED AS POWER BOOSTER IN THE OUTPUT STAGE OF THE CA3160

15

CA3160, CA3160A Typical Performance Curves

OPEN LOOP VOLTAGE GAIN (dB) OPEN LOOP VOLTAGE GAIN (dB) VS = 7.5V TA = 25oC OPEN LOOP PHASE (DEGREES) 120 100 150 140 130 120 110 100 90 80 -100 0 50 100 80 RL = 2k

OL

150 200

60

40

CL = 30pF RL = 2k

20

0 101 102 103 104 105 106 FREQUENCY (Hz) 107 108

-50

50

100

TEMPERATURE (oC)

FIGURE 15. OPEN LOOP VOLTAGE GAIN AND PHASE SHIFT vs FREQUENCY

FIGURE 16. OPEN LOOP GAIN vs TEMPERATURE

OUTPUT VOLTAGE [TERMS. 4 AND 6] (V)

17.5 15 12.5 10 7.5 5 2.5 0 0 RL = 5k 2k 1k 500

15.0 QUIESCENT SUPPLY CURRENT (mA) V+ = 15V, V- = 0V TA = 25oC

12.5

TA = 25oC RL = V- = 0

10.0

BALANCED VO = V+/2

7.5

5.0

HIGH VO = V+ OR LOW VO = V-

2.5

0 2.5 5 7.5 10 12.5 15 17.5 20 GATE VOLTAGE [TERMINALS 4 AND 8] (V) 22.5 6 8 10 12 14 16 18 POSITIVE SUPPLY VOLTAGE (V)

FIGURE 17. VOLTAGE TRANSFER CHARACTERISTICS OF CMOS OUTPUT STAGE

FIGURE 18. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE

16

CA3160, CA3160A Typical Performance Curves

14 QUIESCENT SUPPLY CURRENT (mA) 12 10 TA = -55oC 8 6 4 2 0 0 2 4 6 8 10 12 14 POSITIVE SUPPLY VOLTAGE (V) 16 18 25oC 125oC VO = V+ / 2 V- = 0

(Continued)
VOLTAGE DROP ACROSS PMOS OUTPUT STAGE TRANSISTOR (Q8) (V)

50 10

V- = 0V TA = 25oC

V+ = 15V 10V 5V

0.1

0.01

0.001 0.001

0.01 0.1 1 10 MAGNITUDE OF LOAD CURRENT (mA)

100

FIGURE 19. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE

VOLTAGE DROP ACROSS NMOS OUTPUT STAGE TRANSISTOR (Q12) (V)

FIGURE 20. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR (Q8) vs LOAD CURRENT
1000 TA = 25oC VS = 7.5V

50 10 V- = 0V TA = 25oC V+ = 15V 10V 5V

100 EN (nV/Hz) 10 0.01 1 0.01 0.1 1 10 100 1 101 MAGNITUDE OF LOAD CURRENT (mA) 102 103 FREQUENCY (Hz) 104 105 1

0.1

0.001 0.001

FIGURE 21. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR (Q12) vs LOAD CURRENT

FIGURE 22. EQUIVALENT NOISE VOLTAGE vs FREQUENCY

17

CA3160, CA3160A Typical Performance Curves

10 TA = 25oC

(Continued)

4000

VS = 7.5V

1000 7.5 INPUT VOLTAGE (V) V+ 15V TO 5V 7 CA3160 3 2.5 VIN 4 8 0V TO V- -10V -1 0 1 2 3 4 5 6 INPUT CURRENT (pA) 7 6 INPUT CURRENT (pA)

100

5 PA

10

1 -80 -60 -40 -20

0 20 40 60 80 TEMPERATURE (oC)

100 120 140

FIGURE 23. INPUT CURRENT vs COMMON MODE VOLTAGE

FIGURE 24. INPUT CURRENT vs TEMPERATURE

7 OFFSET VOLTAGE SHIFT (mV) 6 5 4 3 2 1 0 0 500 1000 1500 2000 2500 3000 3500 4000 TIME (HOURS) DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 0V OUTPUT VOLTAGE = V+ / 2 DIFFERENTIAL DC VOLTAGE (ACROSS TERMINALS 2 AND 3) = 2V OUTPUT STAGE TOGGLED TA = 125oC FOR METAL CAN PACKAGES

FIGURE 25. TYPICAL INCREMENTAL OFFSET VOLTAGE SHIFT vs OPERATING LIFE

18

CA3160, CA3160A Dual-In-Line Plastic Packages (PDIP)

N E1 INDEX AREA 1 2 3 N/2

E8.3 (JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL
-B-

MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 9.01 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 10.16 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93

MIN 0.015 0.115 0.014 0.045 0.008 0.355 0.005 0.300 0.240

MAX 0.210 0.195 0.022 0.070 0.014 0.400 0.325 0.280

-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E

A A1 A2 B B1 C D D1 E

-C-

eA eC
C

C A B S

eB

NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the MO Series Symbol List in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E1 e eA eB L N

0.100 BSC 0.300 BSC 0.115 8 0.430 0.150 -

2.54 BSC 7.62 BSC 10.92 3.81 8

2.93

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