A COURSE ON COMPUTER AIDED PCB DESIGN USING

PROTEL

INTRODUCTION
Protel 99 is designed as a "client - server application, i.e. the main application program of Protel 99 , called Client99.exe, provides the basic infrastructure and user interface for Protel 99 , while specific services, such as editing a schematic or PCB are provided by a series of plug-in "servers". When you click on the Protel 99 icon in the Windows Start menu, Client99.exe is the application that is started. You do not then need to launch a schematic editor, PCB editor, etc. as separated programs - all your Protel EDA tools are available from within the Protel 99 desktop. The use of a "client server" architecture for Protel 99 means that you can easily expand the capabilities of the software. As well as the servers supplied with Protel 99 , various add-on servers are available from both Protel and numerous third-party vendors. To use Protel 99 it is not necessary to understand how the client server architecture works, however a basic knowledge of servers will help you get the most from Protel 99.

Creating a new DDB Using the Design Explorer

To create a new Design Database select File New Design from the menus. The New Design Database dialog will pop up. Complete the following steps: 1. 2. 3. Select the Storage Type Enter the Database name Set the location as required

If you would like to password-protect the Design Database now, click on the Password tab and enter the password. This password is assigned to the default user name Admin.You can password-protect a Design Database at any time, by going to the Members folder and entering a password for the Admin member. To unprotect a Database remove the password from the Admin member. Note that you can only password-protect a design database whose storage type is MS Access database. Once the new design database is created an icon for it will appear in the navigation tree of the Design Explorer, and its corresponding design window will open in the work area.

Working with SCH. Documents

A schematic is a diagrammatic representation of an electronic circuit, and schematic capture is the process of capturing a design as a schematic in a computer-aided design environment. A computer-based schematic is more than a simple drawing of the circuit. It also contains information about the connectivity of the circuit and the parts that make up the circuit. In Protel, the basic workspace for capturing a schematic is called a schematic sheet. Electrical, drawing and directive objects are placed on a schematic sheet to design the circuit and produce working schematic drawings. A complete circuit design can use just a single sheet, or it can comprise a number of electrically linked sheets. Protel allows you to create complex hierarchical and modular designs by linking any number of sheets to form a complete project. ______________________________ Schematic design topics Schematic electrical design objects Schematic drawing objects Schematic design directives Setting schematic workspace preferences Setting schematic document options Using schematic sheet templates Managing schematic components Editing schematic component libraries Repositioning design objects on a schematic Wiring up a schematic Workspace editing techniques Creating projects with multiple schematic sheets Schematic design verification - the ERC Printing and plotting a schematic Generating schematic reports Preparing a schematic for PCB layout Interfacing from a schematic to third-party tools Default schematic shortcut keys 3

Open Printed Circuit Board File To begin the PCB design phase of a project, create a new PCB document in your design database (see the Adding a new document or folder to a design topic in the Links section below). Before bringing design information from the schematic, you should first create the mechanical and electrical board outline for your board, and configure the layer stack. The mechanical outline defines the physical shape and size of the board, and also includes items such as dimension detail, photo tool targets and other company and fabrication specific information. This information is usually placed on the four Mechanical layers. Tile electrical board outline defines the routing and component placement limits of the board. This is done by defining an outline of the board on the Keep Out layer. The Keep Out layer is a special layer that allows you to define "legitimate" placement and routing areas in the PCB workspace. Generally you would define an area which is the same as the physical board outline. All signal-layer objects and routing would then be confined within this area. You could also define areas on the Keep Out layer within the board outline to act as "no go" areas for placement and routing. The layer stack defines what signal and plane layers are available. Part of the layer stack definition process is to define the drill-pairs. Protel 99 includes a powerful Board Wizard that guides you through the complete process off creating a new PCB document and board definition. The Wizard includes a number of predefined board templates, and allows you to create your own templates.

PCB Definition Topics

Defining the PCB layer stack Defining the drill pairs Creating the mechanical definition of a PCB 4

 Defining the PCB placement & routing outline Using the Board Wizard to create a new PCB Loading a schematic design into a PCB document

Open Schematic File

A schematic is a diagrammatic representation of an electronic circuit, and schematic capture is the process of capturing a design as a schematic in a computer-aided design environment. A computer-based schematic is more than a simple drawing of the circuit. It also contains information about the connectivity of the circuit and the parts that make up the circuit. In Protel, the basic workspace for capturing a schematic is called a schematic sheet. Electrical, drawing and directive objects are placed on a schematic sheet to design the circuit and produce working schematic drawings. A complete circuit design can use just a single sheet, or it can comprise an number of electrically linked sheets. Protel allows you to create complex hierarchical and modular designs by linking any number of sheets to form a complete project.

Creating a new schematic Symbols

To create a new schematic component; from a schematic library document select Tools New Component from the menus. A new component will be created in the library and you will be presented with an empty component sheet. Rename the component by selecting Tools Rename Component from the menus. Initially the schematic component sheet is shown fully zoomed out. The origin for the sheet is marked by the intersection of the crossed guide lines. Before drawing your component, you should zoom in [shortcut Page Up] until the grid becomes visible. You should also draw your component based around the component sheet origin. Select Edit Jump Origin [shortcut JO] to center the origin in the workspace. To define your new component, complete the following steps: 1. Define the component body using the various drawing objects available from the Place menu, or from the SchLib Drawing Tools toolbar. These tools provide the same drawing object available in schematic sheets. 5

2. Place the component pins by selecting Place Pins from the menu [shortcut P P]. When you enter Pin placement mode, the pin will appear floating on the cursor. Note that you hold" the pin by its non-electrical end, which goes against the component body. Press SPACEBAR to rotate the pin while it is floating on the cursor. Press the TAB key during placement to edit the pin's properties before placing it. 3. If you are creating a multipart component, select Tools New Part to add another part to the component and repeat the above steps to create the symbols for all parts in the component. 4. Set the component's properties by selecting Tools Description from the menus. This opens the Component Text Fields dialog in which you set the component's default designator and PCB footprint, a description of the component, and set up the various part fields and library fields that are displayed when the component properties are edited from a schematic sheet. 5. Save the component sheet to save the component in the library. Note: The IEEE symbols can be resized during placement. Press the + and - keys to enlarge and shrink the symbols as you place them.

Aligning schematic design objects

There are a number of alignment options available for lining up design objects on a schematic. The alignment options work on all selected objects. To align selected objects on both axes, from the schematic select Edit Align Align to open the Align Objects dialog [shortcut A A]. Select the desired vertical and horizontal alignment from the option buttons and click OK to have all selected objects moved to the chosen horizontal alignments. Enable the Move Primitives to Grid option to constrain alignment to the nearest grid point. The following single-axis alignments are available from the Edit Align submenu [shortcut A] or via shortcut keys: Align Left Align Right Center Horizontal Distribute Horizontally Align Top Align Bottom CTRL+L CTRL+R CTRL+H CTRL+SHIFT+H CTRL+T CTRL+B 6

Center Vertical

CTRL+V

Distribute Vertically

CTRL+SHIFT+V

Note: The alignment options affect ALL selected objects. Before using any alignment command, ensure that only the objects that you wish to align are selected. If necessary, use the shortcut X A to deselect all objects before selecting the objects you want to align. Note: Connectivity is not preserved during alignment.

Customizing menus, toolbars & shortcut tables

Within the Protel environment menus, toolbars and keyboard shortcut tables are referred to as resources. Whenever you open or activate a document in the Design Explorer, Protel automatically initiates the appropriate editor for that document type and displays the appropriate menus and toolbars, as well as activating the appropriate shortcut keys. You can configure the resources assigned to each document editor available in the system. Each document editor can have one menu and keyboard shortcut table active at a time, and assigned any number of toolbars. The following topics detail the resource customization process.

Power port (Schematic electrical design object)

Description: A power port is a special schematic object that lets you easily define a power or ground net. Seven graphical styles of power port are available, and can be set by editing the objects properties

Please Note: The graphical symbol selected for a power port does not determine which net it is assigned to. You must explicitly set the net name in the object's properties dialog. To place: Once in power port placement mode, a power port symbol will appear "floating" on the cursor. Use the SPACEBAR key to rotate this to the desired orientation. Press TAB to change the properties of the port. Position the object and left-click or press ENTER to place the bus entry. Continue placing further power ports, or right-click or press ESC to exit placement mode. Graphical editing: When a power port is in focus, the following editing handles are available Click anywhere within the dashed box to "pick up" the power port and reposition it.

Creating a new PCB component

To create a new component, you must first open the library that will hold the component (see Opening a PCB library for editing in the Links section below) Once the desired PCB library file is open and active, select the Tools New Component menu item. The Component Wizard will automatically start to guide you through the process of building a new PCB component. If you do not want to use the Component Wizard, press Cancel to manually create a component. You will be presented with an empty component footprint workspace. Select Tools Rename Component to give your new component a name (255 characters maximum). Creating a component footprint uses the same tools and design objects that are used to design a PCB. Place tracks and arcs in the footprint sheet to create the body of the component, then place pads to form the component pin connections. As with PCB design, design objects can be placed on any layer. When you subsequently place the footprint on a PCB document, all objects that make up the footprint will be assigned to their defined layers. 8

____________________________________________

Links Opening a PCB library for editing Editing footprints in PCB libraries

You can browse for schematic components in the schematic panel, using the Mini Viewer that appears at the bottom of the panel when the Browse mode is set to Libraries. You can also browse schematic component libraries in the Browse Components dialog (Design Browse Library).

Placing design objects in documents

The method for placing objects is similar for both schematic and PCB documents. The basic placement steps are outlined below. For help on placing specific objects, use the See also... link at the bottom of the page 1.Select the object that you want to place - You can do this by selecting an object from the Place menu or by clicking on one of buttons from the various placement toolbars. For components and footprints, you can also click the Place button in the Panel when browsing libraries. 2. When an object is selected for placement, the cursor will change to a crosshair, indicating that you are in editing mode, and, if relevant, the object will appear "floating" on the cursor. 3. Press the TAB key to edit the properties of the object before placing it. This will open the property dialog for the particular object, allowing you to change various options. Once you have finished setting the properties, close the dialog to return to placement mode. 4. Position the cursor and left-click or press ENTER to place the object. For complex objects such as wires, tracks, polygons, etc. you must continue the position and click procedure to place all vertices of the object. Note: If auto panning is active, you can move around the document by simply moving the cursor past the edge of the editing window in the direction that you wish to go. 5. After placing an object you will remain in placement mode (indicated by the crosshair cursor), allowing you to place another object of the same type immediately.

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6. To end placement mode, right-click or press the ESC key (in some cases, such as placing a polygon, you may need to do this twice; once to finish placing the object and once to exit placement mode). When you exit placement mode, the cursor will return its default shape.

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Connecting schematic objects using net identifiers

In connectivity terms, a net defines electrically connected points in a circuit. By placing a wire between two nodes in a schematic, you effectively assign the two points to the same net. In a schematic, Protel internally assigns a unique name to each net in the circuit, but you can manually define net names to create connectivity between nodes on the schematic. To manually assign a net name (or net identifier) to a point in your schematic, place a Net Label on that point. The net name is the name given to the Net Label. If you assign the same net name two or more points on a schematic, these points are effectively connected electrically. You do not need to manually connect them using a wire. The diagram (left) shows two electrically equivalent circuits. The top shows two resistors connected in parallel using wires to make the connections the connections. The bottom shows two resistors connected in parallel using net labels to define

A typical use of connections using net identifiers is connecting to power nets. When you place a power port on a schematic it defines a net which has a net name equivalent to the power object's name (VCC, GND, etc.). You can then place net labels on any schematic circuit nodes which have the same net name as the power port to automatically connect these nodes. You do not need to physically wire the nodes to the power port.

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2 VCC C4 CAP

P1 PORT1 D 8 7 6 5 4 3 2 1

RP1 RP8

1 2 3 4 5 VCC 6 7 SW1 TACKSW R1 10K C1 10UF/16V 8 9 10 11 12 13 14 15 16 17 B C2 22PF 18 X1 19 CRYSTAL 20 + U1 IC 89C2052 a b c d e f g

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

P2 1 2 3 4 5 6 7 8 PORT2

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LCD 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 L1

C3 22PF

Title Size A4 Da te: File: 1 2 3

CIRCUIT DIAGRAM FOR MC

Number 2-May-2009 G:\Previous Bac kup of VIKAS P.DDB Sheet of Drawn By: 4 Re vision

VIKAS SH ARMA

Sheet 1
Part Type 10K 22PF 10UF16V RP8 CRYSTAL 22PF CAP PORT1 PORT2 IC 89C2052 LCD SW Designator R1 C3 C1 RP1 X1 C2 C4 P1 P2 U1 L1 SW1 Footprint RES1OP2WS CAP5P2WS EC5P6W RP8 CRYSTAL CAP5P2WS CAP5P2WS 8CONN2.5P 8CONN2.5P DIP40 16CONN2.5P TACKSW 13 Description RESISTOR CAPACITOR ELE.CAPACITOR COM.RESISTOR CRYSTAL CAPACITOR CAPACITOR CONNECTOR CONNECTOR IC LCD SWITCH

Schematic sheet with simple hierarchy

This model is referred to as simple hierarchy. It supports multi-level or block design, where the design hierarchy can be represented by a tree- like structure. A sheet symbol represents a child sheet, which descends from the parent All the inter-sheet connections are vertical; the sheet entries in each sheet symbol are connected to similarly named ports on the respective subsheets. The sheet symbol-to-sheet symbol wiring is included on the parent sheet. This model is a true hierarchy because the inter-sheet connections follow the hierarchy of the sheets themselves, and the design can be as many levels deep as you like. To use this model for multi-sheet schematic designs, set the Net Identifier Scope to Sheet Symbols / Port Connections when performing an ERC, running a simulation, creating a net list, compiling a schematic-based PLD, or synchronizing between schematic and PCB documents.

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Generating schematic reports

A range of reports on the currently active schematic sheet can be generated. Reports are generated by selecting the appropriate item on the Reports menu. The following options are available:Selected Pins:- Lists all pins connecting to the selected net(s). Choose Select >> Net, then click on a net. Bill of Materials:- When you select Reports >> Bill of Materials the schematic BOM Wizard will start, which guides you through the process of creating a bill of materials from your schematic. Cross Reference:- When you select Reports >> Cross Reference, an ASCII text report is generated giving a listing of part designators, type and the sheet location for each part. The report is named filename. XRF and is stored in the same folder as the schematic sheet. Project hierarchy:- When you select Reports >> Project Hierarchy, an ASCII text report is generated giving a listing of project files for the active design. The report is named filename. REP and is stored in the same folder as the schematic sheet. Netlist Compare:- When you select Reports >> Netlist Compare, an ASCII text report is generated that lists the differences between two netlists. Use this report to document changes made to a project from one revision to another. This feature works with Protel, Protel 2 and Tango format netlists. Among other details, the report lists matched nets, partially matched nets, extra nets in the first or second netlist, and total nets in each netlist. The report is named filename. REP and is stored in the same folder as the schematic sheet. Add Port References (Flat):- Select this to include a string next to each port, detailing the sheet name and grid reference of all other ports of the same name in the project. The location of each port reference is determined by the location of the port on the sheet and the position of the connecting wire. Port references are a calculated attribute of the port; they can not be edited and are not stored with the design. Add Port References (Hierarchical):- Select this to include a string next to each port, detailing the sheet name and grid reference of the sheet entry that this port connects to. Remove Port References:- Select to remove all Port references in the project.

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Preparing a schematic for making a PCB layout

In Protel 99 , creating a PCB layout from a schematic is a fully automated process handled by Protel's design synchronizer. The synchronizer allows you to initially transfer the design to a PCB, maintaining full connectivity, and subsequently update design changes from the schematic to the PCB and vice versa. Before you can use Protel's synchronization features, you must create a PCB document based on your schematic design. To do this, create a new PCB document in the design database, draw the board outline and then run the design synchronizer to transfer the schematic information to the PCB. For information on creating a new PCB document, see the topic Adding a new document or folder to a design in the Links section below. For information on creating the board outline, see the topic creating a PCB outline in the Links section below. For information on using the design synchronizer, see the topic Synchronizing schematic & PCB documents in the Links section below. Note: It is advisable to perform an ERC on your schematic and fix and errors before starting the PCB layout process. The following topics detail the steps necessary to prepare a schematic for transfer to a PCB layout: Reassigning part designators in a schematic design Checking schematic parts for missing PCB footprints Including PCB layout information in a schematic

Component Footprint (PCB design object)

Toolbar: Placement ToolsMenu: Place Component [P C] Valid layers:- Top or Bottom signal layers Can be connected to a net?: No (Component pads, however, can be assigned to net)

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Description: A component footprint is the representation of a physical device on a PCB. A footprint may contain pads for connecting to the pins of a device, a physical outline of the package, device mounting features, etc. To place: When you enter component placement mode the Place Component dialog will open. In this dialog, type the name or browse for a component footprint from a loaded PCB library. Set the appropriate designator and any comment text, then click OK to close the dialog. You will return to the PCB document and an outline of the component will be "floating" on the cursor. Position the component and left-click or press ENTER to place it. The Place Component dialog will re-open, allowing you place another component. Press Cancel to exit component placement mode. Graphical editing:- A component footprint cannot be focused and graphically edited directly. To edit the graphical attributes of a component you must open it the relevant PCB library. Notes: Generally when you start a new PCB you will load information from a schematic. This process is known as synchronization. When the PCB is synchronized with the schematic project, the necessary PCB footprints are placed on the board ready for positioning, and the connectivity of the schematic is preserved on the PCB. Component footprints can be converted to a set of primitive objects by selecting Tools Convert Explode Component to Free Primitives from the menus. Once a component is exploded it can no longer be manipulated as a group object.

Using PCB design rules

You design your PCB by placing components, tracks, vias and other design objects. These objects must be placed in the workspace with regard to each other. Components must not overlap, nets must not short, power nets must be kept clear of signal nets, etc. To allow you to remain focused on the task of designing the board, Protel 99 SE can monitor these design requirements for you. You instruct the PCB editor of your requirements by setting up a series of design rules. These design rules are monitored as you layout the PCB. As soon as an object is placed in violation of a design rule it is highlighted. Also, during the board verification process you can run the integrated Design Rule Checker, which will generate a report of any design rule violations in you PCB. 17

Protel allows a wide range of design rules to be defined for a PCB. These include clearances, object geometry, parallelism, impedance control, routing priority and topology, placement rules, and signal integrity rules. Each rule has a Rule Scope that defines how it is applied. The scope allows you to apply a rule to objects, nets, net classes, components, component classes, layers, regions, through to the whole board. Design rules are set up and configured in the Design Rules dialog box (from the PCB document select Design Rules).

Design rule topics

Creating and editing PCB design rules Setting the scope of a PCB design rule Situations where PCB design rules are applied Checking which rules apply to an object PCB design rule definitions PCB design rule examples Importing and exporting design rules

PCB connectivity
When you load a schematic design into a PCB document, the pin-to-pin connections in each net are displayed as a series of thin connection lines. The line that connects each pin in the net to another pin in the net is called a from-To, going FROM one pin in the net TO another pin. The From-Tos are collectively referred to as the Ratsnest. The pattern or arrangement of the From-Tos in a net is called the net topology. If a net has not been assigned a user-defined topology then From-Tos are arranged to give the shortest possible connection distances for the entire net, based on the current arrangement of the components.

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if the net has a user-defined topology applied the connection line is added to maintain the topology, and is shown as a dotted line (called a Broken Net Marker), indicating that the net should be routed between these two points to maintain the topology.

A specific topology can applied to a net by either defining a Topology Rule, or by defining fixed From-Tos in the Form-To editor. ____________________________________ PCB connectivity topics Specifying PCB topology in the From-Tos editor Display/hide connection lines in a PCB document Changing the properties of a net in a PCB Managing the netlist _____________________________________ Links Loading a schematic design into a PCB document Using PCB design rules Working in PCB documents

Working in PCB documents

A printed circuit board (PCB), sometimes referred to as printed wiring board (PWB), is the foundation of circuit construction. Components are soldered onto the PCB, and the PCB provides the electrical connection pathways between components to form the physical circuit. Connections are made using copper tracks etched onto the various layers of the PCB. A PCB document is displayed as a set of superimposed layers, with each layer corresponding to an individual "phototool" used to fabricate the board. In general, a PCB is derived from a schematic representation of the circuit. When a schematic is loaded into a PCB document, schematic part symbols are translated to corresponding board component footprints and the connectivity of the schematic is preserved and displayed as connection lines in the PCB document.

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SINGAL SIDE PCB LAYOUT

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DOUBLE SIDED PCB LAYOUT File extensions used to identify each Gerber file
When you generate the Gerber output a series of files are created, each one corresponding to one of the layers enabled in the Gerber setup. These files are then loaded into a Gerber photo plotter, which produces the necessary photo tools for PCB manufacture. Each Gerber file is given the name of the PCB document, with a unique extension that identifies that layer and plot type. For example, the Top layer Gerber file for a PCB called MyDesign will be saved as MyDeisgn.GTL, to indicate "Gerber Top Layer". Because each design normally generates numerous Gerber files, these extensions help identify each file. We recommend that you follow this convention which conforms to general industry practice. T4e following table shows the extensions that are used: Top Overlay .GTO Bottom Overlay .GBO Top Layer .GTL Bottom Layer .GBL Mid Layer 1, etc. .GI, .G2, etc 22

Power Plane 1, etc. .GP1, GP2, etc Mechanical Layer 1, etc. .GM1, .GM2, etc Top Solder Mask .GTS Bottom Solder Mask .GBS Top Paste Mask .GTP Bottom Paste Mask .GBP Drill Drawing .GDD Drill Drawing; Top to Mid 1, Mid2 to Mid 3, etc. Drill Guide .GDG Drill Guide; Top to Mid 1, Mid 2 to Mid 3, etc Pad Master, Top .GPT .GD1, GD2, GD3, etc. .GG1, GG2, GG3, etc. Pad Master, Bottom .GPB Keep out Layer .GKO Gerber Panels .PO 1, .P02, etc.

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Links:Setting up the Gerber file options Working in PCB documents Generating the manufacturing files Gerber file output setup

Printing and plotting a schematic

Protel 99 includes support for a wide variety of hard copy options for schematic sheets. Virtually any device that is supported by Windows can be used to print or plot your schematic drawings. Schematic printing and pen-plotting are handled similarly to other Windows applications. Windows manages the printing (or plotting) process and provides a range of raster and PostScript printer drivers and vector plotter drivers. These range from 9 pin dot matrix printers and multi-pen plotters, to high-resolution raster image setters. 25

To setup to print or plot from the active schematic or schematic library, select the File Setup Printer menu item (shortcut: F, R). This will open the Schematic Printer Setup dialog, allowing you to choose a printer and set up the output options. To start the print process, click the Print button in the Schematic Printer Setup dialog, or from a schematic select File Print from the menus. Tiling a schematic for printing:- When the size of the sheet or library document to be printed exceeds the print area available on the target device, it will automatically be cut and printed across two or more sheets, or tiles. The sheets are tiled such that the correct margin is maintained at the outer edge of each sheet. You can preview the result of tiling by opening the Schematic Printer Setup dialog box and pressing the Refresh button. A preview of the output will be shown in dialog. It is often possible to reduce the number of sheets required to tile a print, by changing the printer page orientation and adjusting margins. Experiment while in Preview mode to obtain the best match before printing. Schematic PostScript printing issues:- Some PostScript printers will "time out" and discard the current data when they don't receive the end of page marker within a specified time. This can cause problems where you seem to be missing pages from your plots. If you experience this problem using a PostScript printer or any other printing device, open the Windows Control Panel, select the printer icon, select the printer and click the Configure button. Change the Transmission Retry to 500 seconds, or some other large number. This will allow the printer sufficient time to catch up before the Print Manager gives up. If you find your printout is incomplete, say all the components are there but not all the wires, there may be insufficient memory in the printer. Laser printers must capture the entire image in memory before printing it, so if does not all fit in memory, then the image in memory is printed as is.

Introduction to CircuitCAM
This manual is an introduction into the operation of CircuitCAM V3.1 and V3.2 for Windows TM. You can use CircuitCAM to import, check and edit circuit board production data in various CAM formats, and then output them again into a CAM format (LMD/HP-GL). 26

CircuitCAM is particularly useful in calculating the isolation channels between the conductor tracks in circuit board prototype production using LPKF circuit board plotters. Another major usage of CircuitCAM is for the production of high quality Stencils, needed for the soldering process of fine pitch SMD PCBs. For this purpose CircuitCAM is extended to prepare the data for a Stencil-LASER from a pad-layout. CircuitCAM is available in five different variant, optimized for different purposes: CircuitCAM DEMO to test its functionality without being able to store the resulting data. CircuitCAM LITE is the low cost solution. It includes most of the functionality of the PCB variant, but has an optimized user interface for infrequent usage and is limited for 2 insulation tools. CircuitCAM PCB is the standard variant with full insulate functionality. CircuitCAM PRO includes the PCB variant plus additional shape manipulations and Export functionality. CircuitCAM STENCIL includes the PCB variant together with the ability to prepare data for the STENCIL Laser.

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Programming In C Language
The C programming language (often, just "C") is a general-purpose, procedural, imperative computer programming language developed in the early 1970s by Dennis Ritchie for use on the Unix operating system. It has since spread to many other operating systems, and is now one of the most widely used programming languages. C has also had a great influence on most other popular languages, especially C++ which was originally designed as an enhancement to C. It is distinguished for the efficiency of the code it produces, and is the most commonly used programming language for writing system software, though it is also widely used for writing applications. Though not originally designed as a language for teaching, and despite its somewhat unforgiving character, C is commonly used in computer science education, in part because the language is so pervasive. Note that C# is a very different programming language.

C also has the following specific properties:

Low-level access to computer memory via machine addresses and pointers Function pointers allow for a rudimentary form of closures and runtime polymorphism A standardized C preprocessor for macro definition, source code file inclusion, conditional compilation, etc. A simple, small core language, with functionality such as mathematical functions and file handling provided by library routines C (and partially B) was the language that orginally discarded well established operators such as and, or and = (for equality test).

As a systems implementation language, C lacks features found in other languages:

No non-scalar operations such as copying of arrays or strings (old versions of C did not even copy structs automatically). No automatic garbage collection No bounds checking of arrays (expensive in languages with only scalar operations)

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No semi-dynamic (i.e. stacked, runtime-sized) arrays until the C99 standard (despite not requiring garbage collection). No syntax for ranges, such as the A..B notation used in both newer and older languages (does not fit scalar-only semantics well). No nested functions, though the GCC compiler provides this feature as an extension No closures or functions as parameters, only machine-level function pointers No generators or coroutines; intra-thread control flow consists of nested function calls, barring the (somewhat arcane) use of the longjmp or setcontext library functions No exception handling; standard library functions signify error conditions with the global errno variable Very rudimentary support for modular programming; a cumbersome compilation model dependent on operating system-specific tools. No compile-time polymorphism in the form of function or operator overloading; only rudimentary support for generic programming No support for object-oriented programming, although C++ was originally implemented as a preprocessor that translated C++ into C; there are libraries offering object systems for C, and many object-oriented languages are themselves written in C

No native support for multithreading and networking, though these facilities are provided by popular libraries

Although the list of built-in features C lacks is long, this has contributed significantly to its acceptance, as new C compilers can be developed quickly for new platforms. The relatively low-level nature of the language affords the programmer close control over what the program is doing, while allowing solutions that can be specially tailored and aggressively optimized for a particular platform. This allows the code to run efficiently on very limited hardware, such as mass-produced consumer embedded systems, which today are as capable as the first machines used to implement C. Often, only hand-tuned assembly language code runs faster, although advances in compiler technology have narrowed this gap.

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1.1 Variables
In C, a variable must be declared before it can be used. Variables can be declared at the start of any block of code, but most are found at the start of each function. Most local variables are created when the function is called, and are destroyed on return from that function C provides a wide range of types. The most common are

All of the integer types plus the char are called the integral types. float and double are called the real types.

1.2 Constants
A C constant is usually just the written version of a number. For example 1, 0, 5.73, 12.5e9. We can specify our constants in octal or hexadecimal, or force them to be treated as long integers.

Octal constants are written with a leading zero - 015. Hexadecimal constants are written with a leading 0x - 0x1ae. Long constants are written with a trailing L - 890L.

Character constants are usually just the character enclosed in single quotes; 'a', 'b', 'c'. Some characters can't be represented in this way, so we use a 2 character sequence. 31

1.3 Arrays
An array is a collection of variables of the same type. Individual array elements are identified by an integer index. In C the index begins at zero and is always written inside square brackets. We have already met single dimensioned arrays which are declared like this int results[20]; Arrays can have more dimensions, in which case they might be declared as int results_2d[20][5]; int results_3d[20][5][3]; Each index has its own set of square brackets. Where an array is declared in the main function it will usually have details of dimensions included. It is possible to use another type called a pointer in place of an array. This means that dimensions are not fixed immediately, but space can be allocated as required. This is an advanced technique which is only required in certain specialized programs. When passed as an argument to a function, the receiving function need not know the size of the array. So for example if we have a function which sorts a list (represented by an array) then the function will be able to sort lists of different sizes. The drawback is that the function is unable to determine what size the list is, so this information will have to be passed as an additional argument

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To insert an element in an array:

STARTRT

INPUT a [11],pos,value

k = 11 k = k-1

NO Is k > pos

a [k] = a[k-1]

a [pos] =value NO j=0 j = j+1 YES Is j <11 STOP

PRINT a [j]

33

To delete an element from an array:

STARTRT

INPUT a [11], pos, value

k = pos k = k+1 Is k < 11

NO

a [k] = a[k+1]

NO j=0 j = j+1 YES Is j <10 STOP

PRINT a [j]

34

Program to Print sum of any two numbers:#include<stdio.h> #include<conio.h> Void main( ) { int a,b,c; clrscr( ) printf(enter a=); scanf(%d,&a); printf(enter b=); scanf(%d,&b); c=a+b; printf(sum=%d,c); getch( ); }

35

Program to add Digits of a four digit number:#include<stdio.h> #include<conio.h> void main() { int a, b, c, d, e; clrscr(); printf("enter any 4-digit number =\n"); scanf("%d",&a); b=a%10; a=a/10; c=a%10; a=a/10; d=a%10; a=a/10; e=a+b+c+d; printf(sum of 4-digit no.=%d,e); getch(); }

36

37

Operational Amplifier

Introduction
Op-amp is a direct coupled high gain amplifier usually consist of one or more differential amplifier & usually followed by level translator & output stage, which do the operation of adding subtraction and multiplication.

It consists following four parts:

Input Stage: it is the dual input, balanced out put differential amplifier. This stage generally provides over all gain and gives high input impedance. Intermediate Stage: The intermediate stage is dual input, unbalanced output. Level Shifter: It is used after the intermediate stage to shift the dc level at the out put of the intermediate stage downward to zero with respect to ground. Out put Stage: It is usually a push pull complementary amplifier out put stage. the out put stage increases the out voltage swing and raises the current supplying the capability of the opamp. This stage also provides low out put resistance.

Block Diagram of Op-Amp

38

Some important terms

Input offset voltage: -Input offset voltage is the voltage that is applied between the two input terminals of an op-amp to null the output.

Input Offset Current: - The algebraic difference between the current into the inverting and non-inverting terminals is referred to as input off set current. Iio=|IB1-IB2 |

39

Input bias current: - Input bias current is the average of the current that flow into the inverting and non-inverting input terminals of the op-amp. Differential Input Resistance: - It is the equivalent resistance that can be measured at either inverting or non-inverting input terminal with other terminal connected to ground. Input Capacitance: - It is the equivalent capacitance that can be measured at either inverting or non-inverting input terminal with other terminal connected to ground.

Input Voltage Range: - it is the range of common mode voltages over which the offset specifications apply. It is mainly used for test purposes. Common Mode Rejection Ratio: - CMRR is the ratio of the differential voltage gain (Ad) to the common mode voltage gain (Acm). CMRR=Ad/Acm Acm=Vocm/Vcm The ideal op-amp would exhibit the following electrical characteristics: Op-amp operates in two following configurations: Open loop Closed loop 40

Difference between Open Loop and Closed Loop Open Loop 1. It has very high voltage gain. 2. But it has the disadvantage of that its output voltage and the stability is changed with change in temperature and supply voltage. 3. It amplifies the small input signal of low frequency. 4. It has low bandwidth 0f about 5 kHz. Closed Loop 1. It has low voltage gain. 2. Its output voltage and stability doesn't effected by the change in temperature and supply voltage. 3. It is frequency independent, thus its stability doesn't change with change in frequency. 4. It has high band width, thus it amplifies large input signal.

Open-loop OP-AMP configurations

There are three open loop op-amp configurations: 1. Differential Amplifier: the op-amp amplifies the difference between two input signals, this configuration is called differential amplifier. 2. Inverting Amplifier: When one input signal is applied to the inverting terminal and other terminal grounded. Then the output voltage is out of phase with respect to the input by 180degree or is of opposite polarity. 3. Noninverting Amplifier: When one input signal is applied to the non inverting terminal and other input grounded .then the output voltage is in same phase with respect to the input.

Closed Loop OP-AMP Configuration

Closed loop have two feedbacks: Positive Feedback: The signal fed back is of the same polarity or in phase with input signal. In positive feedback signal aids the input signal thus it is called regenerative feedback. Thus it is used in oscillator circuit. 41

Negative Feedback: the signal fed back is of opposite polarity or in out of phase with input signal. An amplifier with negative feed back has self correcting capability against any change in output voltage caused by environmental conditions .negative feedback is also called degenerative feedback. When used it degenerates the output voltage and in turn reduces the voltage gain.

INTEGRATOR
A circuit in which the output voltage waveform is the integral of the input wave form is called integrator. With the application of square wave it generates the triangular wave. With the application of sine wave it generates the cosine wave. Circuit Diagram of Integrator

Wave form of Integrator Output

42

DIFFERENTIATOR
A circuit in which the output wave form is the differentiation of input wave form is called differentiator. With the application of square wave it generates spikes. With the application of sine wave it also produce cosine wave. Circuit diagram of Differentiator

43

Wave form of Differentiator

First Order Low Pass Filter

A low pass filter passes the low frequencies signal and block high frequencies signal. It shows constant gain from 0 to a high cut off frequencies. At high cut of frequencies the gain is down by 3 db.

44

Second Order Low Pass Filter

Its gain is down by 6 db at high cut of frequencies.

First Order High Pass Filter

A high pass filter passes the high frequencies signals and blocks the low order high pass signal the gain increases by 20 db/decade in the stop band. frequencies signal. It blocks the low frequencies signal from 0 to low cutoff frequencies. For the first

Second Order High Pass Filter

Its gain increases 40db/decade in stop band.

All Pass Filter

All pass filters passes all frequencies components of the input signal without attenuation, while providing predictable phase shifts for the different frequencies of the input signal.

Oscillators
An oscillator is a circuit that generates a repetitive wave form of fixed amplitude and frequency without any external input signal. The two requirements for oscillations: 1. The magnitude of the loop gain AB must be at least 1 2. The total phase shift of open loop gain AB must be equal to 0 degree or 360 degree.

Types of oscillator
Square wave generator When the op-amp is forced to operate in saturation square wave are generated. This mean the output of op-amp is forced to swing repetitively between positive +Vsat (=+Vcc) and negative Vsat. Square wave generator is also called a free-running or multivibrator. The output off set voltage (Volt) will initiate the oscillation. 45

Circuit diagram of square wave generator

Triangular wave generator The triangular wave generator can be formed by connecting an integrator to a square wave generator. The frequency of triangular wave generator is same as that of square wave

Circuit diagram of triangular wave generator

46

Schmitt Trigger An inverting comparator with positive feedback. This circuit converts an irregular-shaped wave form to square wave pulse The input voltage triggers the out put every time it exceeds certain voltage levels called the upper threshold voltage and lower threshold voltage. Thus if the thresholds are made larger than the input noise voltage will eliminate the falls output transition. Also the positive feed back because of its regenerative action, will make output voltage switch faster between +Vsat and Vsat. Circuit diagram of Schmitt trigger

Voltage limiters To keep the out put voltage swing within specific limits op-amp are used with externally wired component such as zeners or diodes the resultant circuits ,in which the output are limited to predetermined values , are called limiters. Voltage limiter

47

Waveform of voltage limiter

Clippers A circuit that removes positive and negative part of the input signal, can be formed by the using an op-amp with a rectifier diode is called positive or negative clipper. In these circuit the op-amp is basically Used as a voltage follower with a diode in the feedback circuit. The clipping level is determined by the reference voltage level Vref which should be less then the input voltage range of the op-amp. Positive clipper

48

49

Waveform of positive clipper

Clampers In clamper circuits a predetermined dc level is added to the output voltage. In other words the output is clamped to a desired dc level. If the clamped dc level is positive the clamper is a positive clamper. If the clamped dc level is negative, the clamper is called a negative clamper Positive clamper

50

Waveform

Peak Peak detector that measures the positive peak values of the square wave input.

detector

During the positive half cycle of Vin the output of the op-amp drives D1 on, charging capacitor C to the positive peak value Vp of the input voltage Vin. Thus, when D1 is forward biased, the op-amp operates as a voltage follower.

On the other hand, during the negative half cycle of Vin, diode D1 is reverse biased and voltage across C is retained. The only discharge path for C is through Rl since the input bias current Ib is negligible.

51

Peak detector

Waveform

Simple and hold circuit Sample an input signal and holds on to its at last sampled value until the input is sampled again. Sample-and-hold circuit is formed by using op-amp with an E-MOSFET. E-MOSFET works as a switch .And controlled by the sample-and-hold control voltage. Capacitor C serves as a storage element. 52

Sample and hold circuit

Waveform

Peaking amplifier The peaking amplifier provides high gain at resonant frequency. In peaking amplifier a tuned circuit is connected in parallel with feedback resistor. At resonant frequency the impedance of tuned circuit is very high thus it provides high gain.

53

POWER SUPPLY FOR DIGITAL CIRCUITS

Summary of circuit features
Brief description of operation: Gives out well regulated +9V output, output current capability of 100 mA. Circuit protection: Built-in overheating protection shuts down output when regulator IC gets too hot. Circuit complexity: Simple and easy to build. Circuit performance: Stable +9V output voltage, reliable operation. Availability of components: Easy to get, uses only common basic components. Design testing: Based on datasheet example circuit, I have used this circuit successfully as part of other electronics projects. Applications: Part of electronics devices, small laboratory power supply. Power supply voltage: Unregulated DC 8-18V power supply. Power supply current: Needed output current 1A. Components cost: Few rupees for the electronic components plus the cost of input transformer.

54

DESCRIPTION OF POWER SUPPLY

This circuit is a small +12 volts power supply, which is useful when experimenting with digital electronics. Small inexpensive wall transformers with variable output voltage are available from any electronics shop. Those transformers are easily available, but usually their voltage regulation is very poor, which makes them not very usable for digital circuit experimenter unless a better regulation can be a chieved in some way. The following circuit is the answer to the problem. This circuit can give +12V output at about 1A current. The circuit has overload and terminal protection.

IN 4007

1
4700 uf

7812
2

3
1000 uf

+12V

Circuit diagram of power supply

The above circuit utilizes the voltage regulator IC 7812 for the constant power supply. The capacitors must have enough high voltage rating to safely handle the input voltage feed to circuit. The circuit is very easy to build for example into a piece of Vero board.

55

Pin diagram of 7812 regulator IC

PIN 1 : Unregulated voltage input PIN 2 : Ground PIN 3 : Regulated voltage output

Component list
1. 2. 3. 7812 regulator IC. 4700 uf electrolytic capacitor, at least 25V voltage rating. 1000 uf electrolytic capacitor, at least 25V voltage rating.

56

SEGMENT

DISPLAYS

The 7 segment display is used as a numerical indicator on many types of test equipment. It is an assembly of light emitting diodes which can be powered individually. They most commonly emit red light. They are arranged and labeled as shown in the diagram. Powering all the segments will display the number 8.Powering a, b, c, d, and g will display the number 3. Numbers 0 to 9 can be displayed. The d.p represents a decimal point. The one shown is a common anode display since all anodes are joined together and go to the positive supply. The cathodes are connected individually to zero volts. Resistors must be placed in series with each diode to limit the current through each diode to a safe value. Early wrist watches used this type of display but they used so much current that the display was normally switched off. To see the time you had to push a button. Common cathode displays where all the cathodes are joined are also available. Liquid crystal displays do a similar job and consume much less power. Alphanumeric displays are available which can show letters as well as numbers.

57

The seven-segment LED display has four individual digits, each with a decimal point. Each of the seven segments (and the decimal point) in a given digit contains an individual LED. When a suitable voltage is applied to a given segment LED, current flows through and illuminates that segment LED. By choosing which segments to illuminate, any of the nine digits can be shown. For example, as shown in the figure below, a 2 can be displayed by illuminating segments a, b, d, e, and g.

Seven segment displays come in two varieties - common anode (CA) and common cathode (CC). In a CA display, the anodes for the seven segments and the decimal point are joined into a single circuit node. To illuminate a segment in a CA display, the voltage on a cathode must be at a suitably lower voltage (about .7V) than the anode. In a CC display, the cathodes are joined together, and the segments are illuminated by bringing the anode voltage higher than the cathode node (again, by about .7V). The Dig lab board uses CA displays. The seven LEDs in each digit are labeled a-g. Since the Dig lab board uses CA displays, the anodes for each of the four digits are connected in a common node, so that four separate anode circuit nodes exist (one per digit). Similar cathode leads from each digit have also been tied together to form seven common circuit nodes, so that one node exists for each segment type. These four anode and seven cathode circuit nodes are available at the J2 connector pins labeled A1-A4 and CA-CG. With this scheme, any segment of any digit can be driven individually. For example, to illuminate segments b and c in the second digit, the b and c cathode nodes would be brought to a suitable low voltage (by connecting the corresponding circuit node 58

available at the J2 connector to ground), and anode 2 would be brought to a suitable high voltage (by connecting the corresponding circuit node available at the J2 connector to Vdd).

The Dig lab board uses two 2-digit displays to create a single 4-digit display. These displays use the reference designators DSP1 and DSP2, and they appear as relatively large rectangular boxes on the silk screen. Since they contain LEDs, they must be loaded into the board with the correct orientation or they will not function - the displays must be loaded with the decimal points nearest the slide switches.

59

60

DIGITAL TO ANALOG CONVERTER D/A Converters with binary weighted resistors: - it uses an op-amp & binary weighted resistors. These are connected to either ends. The no of binary input is four the converter is 4 bit converter because there are 16 combinations; an analog o/p should have 16 corresponding values. D/A converter with R & 2R resistors: - the binary inputs are simulated by switches b0 through b3,& the o/p is proportional to the binary I/P. Binary I/P are either be high or low assume most significant bit switch b3 is connected to 5v & other switch are connected to ground. Rth= [{(2R||2R+R)||2R}||2R]+R A/D CONVERTER SUCCESSIVE-APPROXIMATION METHOD:- The heart of the circuit is an 8bit successive approximation resistor (SAR) whose o/p is applied to an 8 bit D/A converter. The analog o/p of the D/A converter is then compared to an analog input-output signal by the comparator .The o/p of the comparator is a serial data input to the SAR.

61

MIROCONTOLLER 89C2051
8-bit Microcontroller with 2K Bytes Flash
Compatible with MCS-51 Products 2K Bytes of Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles 2.7V to 6V Operating Range Fully Static Operation: 0 Hz to 24 MHz Two-level Program Memory Lock 128 x 8-bit Internal RAM 15 Programmable I/O Lines Two 16-bit Timer/Counters Six Interrupt Sources Programmable Serial UART Channel Direct LED Drive Outputs On-chip Analog Comparator Low-power Idle and Power-down Modes

62

Pin Configuration

Pin Description

VCC GND Port 1

Supply voltage. Ground.

Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull up.

P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pull-ups. Port 1 also receives code data during Flash programming and verification.

63

Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/Opins with internal pull-ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. RST Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cycles while the oscillator is running resets the device. Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Power-down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is terminated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Programming Algorithm:
To program the AT89C2051:1. Power-up sequence: Apply power between VCC and GND pins Set RST and XTAL1 to GND 2. Set pin RST to H Set pin P3.2 to H 3. Apply the appropriate combination of H or L logic levels to pins P3.3, P3.4, P3.5, 3.7 to select one of the programming operations shown in the PEROM Programming Modes table.

64

To Program Verify the Array:1. Apply data for Code byte at location 000H to P1.0 toP1.7. 2. Raise RST to 12V to enable programming. 3. Pulse P3.2 once to program a byte in the PEROM array or the lock bits. The byte-write cycle is self-timed and typically takes 1.2 ms. 4. To verify the programmed data, lower RST from 12V to logic H level and set pins P3.3 to P3.7 to the appropriate levels. Output data can be read at the port P1 pins. 5. To program a byte at the next address location, pulse XTAL1 pin once to advance the internal address counter. Apply new data to the port P1 pins. 6. Repeat steps 5 through 8, changing data and advancing the address counter for the entire 2K bytes array or until the end of the object file is reached. 7. Power-off sequence: Set XTAL1 to L Set RST to L Turn VCC power off

AT89S8252 Features:1. Compatible with MCS-51 Products 2. 8K Bytes of In-System Reprogrammable Downloadable Flash Memory -SPI Serial Interface for Program Downloading -Endurance: 1,000 Write/Erase Cycles 3. 2K Bytes EEPROM 4. 4V to 6V Operating Range 5. Fully Static Operation: 0 Hz to 24 MHz 6. Three-level Program Memory Lock 7. 256 x 8-bit Internal RAM 8. 32 Programmable I/O Lines 9. Three 16-bit Timer/Counters 10. Nine Interrupt Sources 11. Programmable UART Serial Channel 65

12. SPI Serial Interface 13. Low-power Idle and Power-down Modes 14. Interrupt Recovery From Power-down 15. Programmable Watchdog Timer 16. Dual Data Pointer 17. Power-off Flag

66

PIN DIAGRAM OF AT89C52

67

PIN DESCRIPTION OF AT89S8252

1. VCC Supply voltage. 2. GND Ground. 3. Port 0:- Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high impedance inputs.

4. Port 1:- Port 1 is an 8-bit bi-directional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pull ups. 5. Port 2:- Port 2 is an 8-bit bi-directional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. 6. When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. 7. Port 3:- Port 3 is an 8 bit bi-directional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. 8. RST:- Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. 9. XTAL1:- Input to the inverting oscillator amplifier and input to the internal clock operating circuit. 10. XTAL2:- Output from the inverting oscillator amplifier. 11. Timer 0 and 1:- Timer 0 and Timer 1 in the AT89S8252 operate the same way as Timer 0 and Timer 1 in the AT89C51, AT89C52 and AT89C55. For further information, see the October 1995 Microcontroller Data Book, page 2-45, section titled, Timer/Counters. 68

12. Timer 2:- Timer 2 is a 16 bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2). Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON; Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.

Liquid Crystal Display(LCD)

INTRODUCTION
The ORIOLE DISPLAY MODULE is a dot matrix liquid crystal display that displays alphanumeric, kana (Japanese) characters and symbols. The built in controller & driver LSIs provide convenient connectivity between a dot matrix LCD and most 4-8 bit micros or microcs.All the functions required for dot matrix crystal display drive are internally provided .Internal refresh is provided by the ODM. The CMOS technology makes the device ideal for application in hand held, portable and other battery powered instruments with low consumption.

FEATURES
Easy interface with a 4 bit or 8 bit MPU. Built in dot matrix LCD controller with font 5*7 or 5*10dots. Display data RAM for 80 characters (80*8bits) Character generator ROM, which provides 160 characters with font 5*7 dots and 32 characters with font 5*10 dots. Both display data and character generator RAMs can be read from the MPU.

69

 Internal automatic reset circuit at power ON. Build in oscillator circuit .(no external ckt is required) Wide range of instruction functions, clear display, cursor home, display on/off, cursor on/off, cursor shift, display shift.

70

LCD INITIALIZATION

ABBREVATED INFORMATION
I/D S S/C R/L DL N F BF =1 =0 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 =1 =0 DDRAM CGRAM ACG ADD AC : Increment : Decrement : Accompanies display shift : Display shift : Cursor move : Shift to right : Shift to left : 8-bits : 4-bits : 2-lines : 1-line : 5*10 Dots : 5*8 Dots : Internally operating : Can accept instruction. : Display data RAM : Character generator RAM : CG RAM address : DD RAM address corresponds to cursor address : Address counter used for DD and CG RAM address.

OPERATIONAL OVERVIEW : Busy Flag: When the busy flag is HIGH level, it indicates that the internal operation mode and the next instruction will not be accepted. When R/W is 1 and RS is 0,the busy flag is o/p from DB7 . The next instruction must be written after the busy flag goes low. Address Counter (AC): The AC generates the address for the DDRAM, the CGRAM and for the cursor display. When an instruction code for DD or CGRAM address is written to the

controller, after deciding whether it is DDRAM or CGRAM, the address information is transferred to AC. After writing into (or reading from) DD or GRAM display data , AC is automatically incremented (or decremented) .The data of the AC is output to DB0 ~DB6 when RS is 0 and R/W is 1. Character Generator ROM (CGROM): The character generator ROM generates 5*7 dot or 5*10 dot character patterns from 8-bit character codes. When the 8-bit character code of a CGROM is written to the DDRAM, the character pattern of the CGROM corresponding to the code is displayed on the LCD display position corresponding to the DDRAM. Character Generator RAM (CGRAM): The character generator RAM (CGRAM) is the RAM with which the user can generate character patterns by program. The CGRAM has the capacity to store 8 kinds of 5*7 or 4 kinds of 5*10 dots. Programming of these character patterns is explained in CGRAM programming. Display Data RAM (DDRAM): The display data RAM (DDRAM) stores display data represented in 8-bit (Hex-decimal) character codes its capacity is 80*8 bits or 80 characters. The DDRAM that is not used for display can be used as general data RAM. LCD will select the character pattern either from CGROM or CGROM. Underline / Blinking Cursor: Cursor is under the control of the MPU programe.The display of the cursor on t5he LCD is made at a position corresponding to the DDRAM address set to the address counter (AC).

PROGRAM FOR TRAFFIC LIGHT CONTROL:#include<REG2051.h> #include<stdio.h> Void delay( ); Void main( ); { While(1) { P3=0X24; P1=0X21; Delay(10) P3=0X24; P1=0X22; Delay(2) P3=0X24; P1=0X0C; Delay(10) P3=0X24; P1=0X14; Delay(2) P3=0X21; P1=0X24; Delay(10) P3=0X22; P1=0X24; Delay(2)

P3=0X0C; P1=0X24; Delay(10) P3=0X14; P1=0X24; Delay(2) } } Void delay( ) { Unsigned int a,I,j; For(i=0;i<=12750;i++} For(j=0;j<=100;j++) } } } }

VLSI (Verilog HDL)

VLSI (Very Large Scale Integration)

INTRODUCTION:The Process of integration hundreds or thousands of components on a single chip.

Advantages :o Small in size o Low cost o Low power o High reliability o More functionality

Disadvantages:Long design & fabrication time, higher risk to protect.

A simple VLSI design circuit:System spefication Architectural design Functional design Logic design Circuit design Physical design Fabrication Packaging & Testing 1. System spefication:it is high level representation of the system.

Factors considerd include

o Performance o Functionality o Physical dimension o Design technique o Fabrication technology

2. Architecture design:-

Basic architectural of the system are also specified such aso Floating, such as point o RISC versus CISC processor o Number of ALUs o Number & structure of pipeline o Size of cache Etc

3. Behavior of Function design:Used to specify behavior of o Input o Output o Timing of each unit

4. Logic design:o Boolean expression o Control flow o Word width o Register allocation

5. Circuit design:Circuit simulation is used to verify the correction & timing of components.

6. Physical design:Exact details depends upon design rule

7. Fabrication:Process includes lithography, polishing, diffusion, etc to produce a chip

8. Packaging & Testing:Finally the wapor is fabricated & derived into individual chip in a fabrication facility chips used in PCB are in a package in dual.

Design Rule / Technology / Methodology:1.Top down

2.Bottom up In top down method circuit is made from top level to bottom level. And in Bottom up method circuit is made from down to top level. A combination of top-down & bottom up is used in todays digital design. As designs become very complex, it is important to follow these structured approaches to manage the design process.

Verilog HDL
Introduction:Verilog, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits. Hardware description languages such as Verilog differ from software programming languages because they include ways of describing the propagation of time and signal dependencies (sensitivity). There are two assignment operators, a blocking assignment (=), and a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a state-machine update without needing to declare and use temporary storage variables. Since these concepts are part of Verilog's language semantics, designers could quickly write descriptions of large circuits in a relatively compact and concise form. At the time of Verilog's introduction (1984), Verilog represented a tremendous productivity improvement for circuit electronic circuits. The designers of Verilog wanted a language with syntax similar to the C programming language, which was already widely used in engineering software development. Like C, Verilog is case-sensitive and has a basic preprocessor (though less sophisticated than that of ANSI C/C++). Its control flow keywords (if/else, for, while, case, etc.) are equivalent, and its operator precedence is compatible. Syntactic differences include variable declaration (Verilog requires bit-widths on net/reg types (classification) demarcation of procedural blocks (begin/end instead of curly braces { }), and many other minor differences. A Verilog design consists of a hierarchy of modules. Modules encapsulate design hierarchy, and communicate with other modules through a set of declared input, output, and bidirectional ports. Internally, a module can contain any combination of the following: designers who were already using graphical schematic capture software and specially written software programs to document and simulate

net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks, and instances of other modules (sub-hierarchies). Sequential statements are placed inside a begin/end block and executed in sequential order within the block. However, the blocks themselves are executed concurrently, making Verilog a dataflow language. Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating, undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of shared signal lines, where multiple sources drive a common net. When a wire has multiple drivers, the wire's (readable) value is resolved by a function of the source drivers and their strengths. A subset of statements in the Verilog language are synthesizable. Verilog modules that conform to a synthesizable coding style, known as RTL (register-transfer level), can be physically realized by synthesis software. Synthesis software algorithmically transforms the (abstract) Verilog source into a netlist, a logically equivalent description consisting only of elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a specific FPGA or VLSI technology.

Importance Of HDL: HDL have many advantages compare to Traditional Schematic based design. Designer can write their RTL description without choosing a specific fabrication technology. Logic synthesis tool can automatically convert the design to any fabrication technology. Since designer work at RTL level, they can optimized and modify the RTL description until it meets the desire functionality. Designing with HDL is analogus to compute programming.

DATA TYPE:NET:- it represent connection between hardware elements, just as real circuits. Nets have values continuously reven on them by the outputs of device that they are connected to. Nets are declare primerly with the keywords wire.

Nets are 1-bit values by default unless they are declare explicitly as vector(default value of net=z)

Registers: It represents data storage elements. It written value until another value is placed on to them. In verilog the term register nearly means say that can hold a value. Verilog registers donot need a clock as hardware register clock.

Hierarchical Modeling Concepts:A digital simulation is made up of various components. Understand top-down and bottom-up design methodologies for digital design. Explain differences between modules and module instances in Verilog. Describe four levels of abstraction-behavioral, data flow, gate level, and switch levelto represent the same module. Describe components required for the simulation of a digital design. Define stimulus block and a design block. Explain two methods of applying stimulus. a

Design Methodologies:There are two basic types of digital design methodologies: a top-down design methodology and a bottom-up design methodology. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. We further subdivide the sub-blocks until we come to leaf cells, which are the cells that cannot further be divided. In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks. These cells are then used for higherlevel blocks until we build the top-level block in the design. Now days, a combination of top-down and bottom-up flows is used. Design architects define the specifications of the top-level block. Logic designers decide how the design should be structured by breaking up the functionality into blocks and sub-blocks. At the same time,

circuit designers are designing optimized circuits for leaf-level cells. They build higher-level cells by using these leaf cells. The flow meets at an intermediate point where the switch-level circuit designers have created a library of leaf cells by using switches, and the logic level designers have designed from top-down until all modules are defined in terms of leaf cells. To illustrate these hierarchical modeling concepts, let us consider the design of a negative edge-triggered.

Modules:Verilog provides the concept of a module. A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. Typically, elements are grouped into modules to provide common functionality that is used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs), but hides the internal implementation. This allows the designer to modify module internals without affecting the rest of the design. module <module-name> (<module-terminal-list>) ; <module internals ... ... Endmodule

Operators:Operator type Operator symbols

Operation performed

Bitwise

Bitwise NOT (1's complement)

&

Bitwise AND

Bitwise OR

Bitwise XOR

~^ or ^~

Bitwise XNOR

NOT

Logical

&&

AND

||

OR

&

Reduction AND

~&

Reduction NAND

| Reduction ~|

Reduction OR

Reduction NOR

Reduction XOR

~^ or ^~

Reduction XNOR

Arithmetic

Addition

Subtraction

2's complement

Multiplication

Division

**

Exponentiation (*Verilog-2001)

>

Greater than

<

Less than

>=

Greater than or equal to

<= Relational ==

Less than or equal to

Logical equality (bit-value 1'bX is removed from comparison)

!=

Logical inequality (bit-value 1'bX is removed from comparison)

===

4-state logical equality (bit-value 1'bX is taken as literal)

!==

4-state logical inequality (bit-value 1'bX is taken as literal)

Shift

>>

Logical right shift

<<

Logical left shift

>>>

Arithmetic right shift

<<<

Arithmetic left shift

Concatenation {, }

Concatenation

Replication

{n{m}}

Replicate value m for n times

Conditional

?:

Conditional

Program:- (example):AND GATE:module and_gate(y,a,b); output y; input a,b; and a1(y,a,b); endmodule;

PROJECT
TRAFFIC SIGNAL CONTROLLER USING A FINITE STATE MACHINE
We are going to design a traffic signal controller using finite state machine approach.

Specification:1. The traffic signal for the main highway gets highest priority because cars are continuously present on the main highway. Thus, the main highway signal remains green by default. 2. If cars from the country road arrive at the Traffic signal. The traffic signal for the country road must turn green only long enough to let cars on the country road go. 3. As soon as there are no cars on the country road, the country road traffic signal turns yellow & then red and the traffic signal on the main highway turns green again. 4. There is a sensor to detect the country road. The sensor sends a signal X as input to the controller X=1 if there are cars on the country road otherwise X=0.

5. There are delays on transitions from s1 to s2, from s2 to s3 & from s4 to s0. The delay must be countable.

FINITE STATE MACHINE (FSM):-

State S0 S1 S2 S3 S4

Signal Hgwy G(green) Y(yellow) R(red) R(red) R(red) Cntry R(red) R(red) R(red) G(green) Y(yellow)

VERILOG:define TRUE 1b1 define FALSE 1b1

//delay define Y2RDELAY 3 //yellow to red delay define R2GDELAY 2 //red to green delay module Sig_Control(hwy,cntry,X,clock,clear); // I/o ports output[1:0] hwy,cntry; //2_Bit output for 3 states of signal green,yellow,red reg[1:0] hwy,cntry; // declared output signals are registers input X; //if TRUE, indicates that there is car onthe countryroad, otherwise FALSE input clock,clear; parameter RED=2d0, Yellow=2d1, Green=2d2; // State parameter def n s0=3d0; hwy // Green Red Red Red cntry Red Red Red Green Yellow

S1=3d1; // Yellow S2=3d2; // S3=3d3; // S4=3d4; //

// Internal state variable reg[2:0] state; reg[2:0] next_state; //state changes only at positive edge of clock always@(posedge clock) if(clear) state<=s0; //controller starts at s0 state else state<=next_state; // state change // compute values of main signal and country signal always@(state) begin

hwy=GREEN //default light assigned for highway light cntry=red; // default light assigned for country light case(state) s0; // no change,use default s1:hwy=YELLOW; s2:hwy=RED; s3:begin hwy=RED; cntry=GREEN; end s4:begin hwy=RED; cntry=YELLOW; end endcase end // state machine using case statements always@(state or X) begin case(state) s0:if(X) next_state=s1; else next_state=s0; s1:begin // delay some positive edge of clock repeat(Y2RDELAY)@(posedge clock); next_state=s2; end s2:begin // delay some positive edge of clock repeat(R2GDELAY)@(posedge clock);

next_state =s3;

s3:if(X) next_ state=s3; else next_state=s4; s4:begin // delay some positive edge of clock repeat(Y2RDELAY)@(posedge clock); next_state=s0; end default:next_state=s0; endcase end endmodule

Stimulus/Test Bench :module stimulus; wire[1:0] MAIN_SIG,CNTRY_SIG; reg CAR_ON_CNTRY_RD; //if TRUE, indicate that there is car on the country roadr reg clock, clear; //instantiate signal controller Sig_control sc(MAIN_SIG,CNTRY_SIG,CAR_ON_CNTRY_RD,clock,clear); // set up monitor initial $monitor($time, main sig=%b Country sig=%b

Car_on_cntry_rd=%b, MAIN_SIG,CNTRY_SIG, CAR_ON_CNTRY_RD);

// set up clock initial begin clock=FALSE; forever #5 clock=~clock; end // control clear signal initial begin clear=TRUE; repeat(5)@(negedge clock); clear=FALSE; end //apply stimulus initial begin CAR_ON_CNTRY_RD=FALSE; repeat(20)@(negedge clock); CAR_ON_CNTRY_RD=TRUE; repeat(10)@(negedge clock); CAR_ON_CNTRY_RD=FALSE; repeat(20)@(negedge clock); CAR_ON_CNTRY_RD=TRUE; repeat(10)@(negedge clock); CAR_ON_CNTRY_RD=FALSE;

repeat(20)@(negedge clock); CAR_ON_CNTRY_RD=TRUE; repeat(10)@(negedge clock); CAR_ON_CNTRY_RD=FALSE; repeat(10)@(negedge clock);$stop; end endmodule