F 19 SERVICE MANUAL

THIS DOCUMENT IS A PROPERTY OF INDUSTRIE FORMENTI ITALIA NO AUTHORIZED MODIFICATIONS ARE PERMITTED.

CREATED BY E.G.

There are two different types of F19 chassis that are equipped with two different microcontroller. These microcontroller are known as ETT having a code SAA5297A and PAINTER with a code number SAA5553. From the point of view of the application on the F19 chassis the two type of microcontroller are substantially having the same performances, the same pinout , the same firmware but they are not interchangeable as the power supply are different.
In case of SAA5297A the power supply is 5 V for the SAA5553 is 3.3 V.

Even if the two devices are non interchangeable the two chassis can be interchanged as the in/out interface are exactly the same.
As the specifications of the two devices are the same and the first version of the chassis was equipped with the SAA5297A , in this document the characteristics of it are very much detailed meanwhile there is a very short description (as an addendum at the end) for the SAA5553.

F19 CHASSIS DESCRIPTION

Summary The F19 is a chassis suitable to drive CRT having both 4 by 3 and 16 to 9 aspect ratio and dimension from 25" up to 34". As we can see from the block diagram the chassis is equipped with the most recent Integrated Circuit like the one chip TV processor TDA884x that does include all the low level signal processing including Video, Audio, synchronisation process, and chroma

decoder . (see more detail at the "TDA884x FAMILY SPECIFICATION" paragraph), and the Sound Processor TDA9875A that perform all sound function including digital decoding of NICAM signals. (see more detail at the " TDA9870A & tda9875A MAIN CHARACTERISTICS" paragraph). The above mentioned devices are driven by an Integrated Circuit that does include the microcontroller function with 64 K ROM and the TELETEXT acquisition and 8 pages RAM. (SAA5297A) In the F19 chassis there are, besides the stereo one, two possible module that are performing "FEATURES" like PIP (picture in picture) and / or CTI (colour transients

improvement) and 4 by 3 to 16 by 9 signal processing. One further module is dedicated to the so called "Zero Power Stand By" A 26 Key Remote Control is performing the full control for the end- used but can also be used in " SERVICE MODE" to control and adjust, without open the back cover of the TV set all the necessary functions. With the 5 "LOCAL KEY BOARD" button all the end user function can also be performed When the TV set is equipped with a PLL tuner the microcontroller recognise it and the tuning method became a frequency synthesis system if not it work as a voltage tuning system (provided all necessary components are mounted) The TV make use of a multilevel MENU (activated both by the Remote Control and Local Keyboard) using five selectable languages ( Italian, German, English, France, end Spanish) with which it is possible to control sequentially all video and sound value, to adjust several parameter like picture format, sound response, sleep timer etc., and to set others important parameter like standard, select country for automatic tuning and sort etc. Here below a list of the characteristics of the TV se

E.G.Data creazione 31/10/99 15.38

1/7

f19intro

TV SET CHARACTERISTICS (MONO & STEREO )

PICTURE TUBE SIZE : 4 : 3 ASPECT RATIO 16 : 9 ASPECT RATIO STANDARD R.F. (ANTENNA) (FOR FREQ. SYNTH.) VIDEO (SCART & CINCH) COLOUR (MAX. THREE STANDARDS) SOUND STANDARD: MONO STEREO TUNING SYSTEM SELECTABLE : FREQUENCY SYTHETIZER TOTAL AVAILABLE CHANNEL NUMBER CHANNEL IN ONE RF STANDARD UP TO NUMBER OF PROGRAM DIRECT PROGRAM & CHANNEL CALL WITH PROGRAM & CHANNEL STEP UP AND DOWN VOLTAGE SYNTHESISER CABLE & HYPERBAND CHANNEL SWITCHABLE AFC AUTOMATIC SEARCH TUNING A S T WITH AUTO SORT 21 / 25 / 28 / 29 / 34 28 / 32 CCIR ( B / G/ L / L / D / K / I ) B / G/ L / L / D / K / I / M / N PAL / SECAM / NTSC B / G/ L / L / D / K / I AM & FM A2 OR NICAM FACTORY OPTION 200 100 100 1, OR 2 OR 3 DIGIT YES YES YES YES YES

AUDIO SECTION
POWER MONO STEREO EXTERNAL CONNECTION HEADPHONE LOUDSPEAKERS A / V INPUT / OUTPUT FRONT PANEL CINCH I FULL SCART (CVBS, STEREO, RBA) SCART (CVBS & STEREO IN / OUT) SCART A TO SCART B LOOP THROUGH TXT LEVEL 1 LEVEL 1,5 (FASTEXT) FEATURES CTI (COLOUR TRANSIENT IMPROVEMENT) 16:9 TO 4:3 VIDEO COMPRESSION VERTICAL ZOOM OUT MENU DRIVEN SYSTEM EASY TO USE REMOTE CONTROL REMOTE CONTROL WITH SERVICE USE PIP E.G.Data creazione 31/10/99 15.38 2/7 6 W RMS. 2 x 6 W RMS. STEREO SET ONLY INTERNAL L.S. SWITCHED A / V INPUT MULTIMEDIA INPUT OUTPUT VCR, HI.FI, SATELLITE, ETC FOR PROGRAMS DUBBING PANEUROPEAN CHARACTER SET 8 PAGES 7 PAGES OPTION ONLY FOR 16:9 TV SET 3 LEVEL

NOT ACCESSIBLE TO END USER OPTION f19intro

AUDIO

TD A9 87 5

AUDIO TDA1521

THIS MODULE IS PRESENT ONLY FOR STEREO SET

AUDIO AUDIO VIDEO & AUDIO

EEPROM PCF8582
TUNER

2ND SCART
A/V IN/OUT

SCART INTER.
A /V OUT A/V IN

FULL SCART
RGB

TD A 84 4X

PLL

SAW FILTER

VIDEO PROCESSOR

RGB VIDEO AMPL. RGB (OSD) TDA5112

TDA 8362A
D.L. CROMA TDA4661

IIC bus MICRO

CUT-OFF

V.

SA A 52 97 A

PCA84C841/210

SECAM TDA8395

VERTICAL TDA3654

RGB

110

TXT

SAA5281/....

TXT & OSD RBG

H. DRIVER

E.W. GEN. TDA4950

L.O.T.
BU 508 D

H.
EHT TRAFO EAT

T.O.P. PHILIPS

BC 639
POWER SUPPLY TDA 460

140 V 26 V 15 V 12 V F16UPF19.DRW E.G. 2/02/99

& STH7N80F

PIP SIEMENS

PIP (RGB)

8V

F16 UPDATED F19

BLOCK DIAGRAM

AUDIO STEREO (NICAM) PROCESSOR TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)

2x7W
AUDIO POWER

F 19
EEPROM PCF8584 / ST2404CB TUNER PLL IIC bus

V I D E O A U D I O I. F.

TDA1521

THIS MODULE IS PRESENT ONLY FOR STEREO SET

I N T E R C A R R I E R AUDIO VIDEO & AUDIO

AUDIO

AUDIO SCART SWITCH HEF4053 VIDEOSCART SWITCH LA7955

A/V IN

HEADPHONE LINE OUT (OPTION)

2ND SCART
A/V IN/OUT A /V OUT

FULL SCART
A/V/ CINCH (OPTION)

RGB

IIC BUS ONE CHIP VIDEO PROCESSOR

SAW FILTER

RGB

VIDEO AMPL. TDA5112

TDA 8843 (4)

*IF VIDEO & PLL DEM *AGC & AFC, MUTE *AUDIO PLL DEM *PAL/NTSC (SECAM) DEC. *B.B CHROMA DELAY LINE *FULL SCART INTERFACE. UV *H & V SYNC PROCESSIG *FULL IIC BUS CONTROLL FOR: *AUTO CUT-OFF *ALL ANALOGUE FUCTIONS *GEOMETRY CORRECTION *FEATURES INTERFACE E-WE-W POWER BUK474200A H DRIVE

CUT-OFF
E-W LOAD COIL

RGB
VERTICAL FEEDBACK

IIC bus

LOCAL KEY BOARD

CRT
V.

ETT

FEATURES MODULE TDA4566 (CTI) SAA4981 (16:9 TO 4:3)

VERTICAL TDA8351

110

SAA5297A
IIC bus MICROCONTROLLER & TELETEX 8 PAGES TXT & OSD RBG

OPTION
H. DRIVER

E-W DRIVE COIL

H.
H. DEFL. &EHT TRAFO EAT

PIP
OPTION

BC 338 I.R. INPUT PIP (RGB) POWER SUPPLY TDA 4605 & STH7N90F1

DRIVER TRAFO 150 V 26 V 12 V 8V 5V

L.O.T. BU 508 D

F19 BLOCK DIAGRAM

F19BLDIA.DRW E.G. 17 / 7 / 99

AUDIO STEREO (NICAM) PROCESSOR TDA 9811 (nicam) TDA 9870A (TDA9875A (nicam)
V I D E O A U D I O I. F.

2x7W
AUDIO POWER

TDA1521

F 19.1
EEPROM PCF8584 / ST2404CB TUNER PLL IIC bus

THIS MODULE IS PRESENT ONLY FOR STEREO SET

I N T E R C A R R I E R

AUDIO
VIDEO & AUDIO

AUDIO

AUDIO SCART SWITCH HEF4053 VIDEOSCART SWITCH LA7955

A/V IN

HEADPHONE LINE OUT (OPTION)

2ND SCART
A/V IN/OUT A /V OUT

FULL SCART
A/V/ CINCH (OPTION) RGB

IIC BUS ONE CHIP VIDEO PROCESSOR

SAW FILTER

RGB

VIDEO AMPL. TDA5112

TDA 8843 (4)

*IF VIDEO & PLL DEM *AGC & AFC, MUTE *AUDIO PLL DEM *PAL/NTSC (SECAM) DEC. *B.B CHROMA DELAY LINE *FULL SCART INTERFACE. UV 4 *H & V SYNC PROCESSIG *FULL IIC BUS CONTROLL FOR: *AUTO CUT-OFF *ALL ANALOGUE FUCTIONS *GEOMETRY CORRECTION *FEATURES INTERFACE E-WE-W POWER BUK474200A H DRIVE

CUT-OFF
E-W LOAD COIL

RGB
VERTICAL FEEDBACK

IIC bus LOCAL KEY BOARD

CRT
V.

ETT
IIC bus

FEATURES MODULE TDA4566 (CTI) SAA4981 (16:9 TO 4:3)

SAA5297A or SAA5553M3
MICROCONTROLLER & 8 PAGES TELETEXT TXT & OSD RBG

VERTICAL TDA8351

110

H.
E-W DRIVE COIL

OPTION
H. DRIVER

PIP
OPTION

BC 338

DRIVER TRAFO 150 V

I.R. INPUT PIP (RGB) POWER SUPPLY TDA 4605 & STH7N90F1 26 V 12 V 8V 5V

L.O.T. BU 508 D

H. DEFL. &EHT TRAFO EAT

F19.1 BLOCK DIAGRAM

F19BDE&P.DRW E.G. 22/04/2000

F19

TUNING & TELETEXT

SAA529XA FAMILY MAIN CHARACTERISTICS

FEATURES

General Single chip microcontroller with integrated teletext decoder Single +5 V power supply Single crystal oscillator for teletext decoder, display and microcontroller Teletext function can be powered-down independent of microcontroller function for reduced power consumption in standby Pin compatibility throughout family.

Microcontroller 80C51 microcontroller core 16/32/64 kbyte mask programmed ROM 256/768/1280 bytes of microcontroller RAM Eight 6-bit Pulse Width Modulator (PWM) outputs for control of TV analog signals One 14-bit PWM for Voltage Synthesis Tuner control Four 8-bit Analog-to-Digital converters 2 high current open-drain outputs for directly driving LEDs etc. I 2 C-bus interface External ROM and RAM capability on QFP80 package version.

Teletext acquisition 1 page and 10 page Teletext version Acquisition of 525-line and 625-line World System Teletext, with automatic selection Acquisition and decoding of VPS data (PDC system A) Page clearing in under 64 s (1 TV line)

Separate storage of extension packets (SAA5296/7, SAA5296/7A and SAA5496/7) Inventory of transmitted Teletext pages stored in the Transmitted Page Table (TPT) end Subtitle Page Table (SPT) (SAA5296/7, SAA5296/7A and SAA5496/7) Automatic detection of FASTEXT transmission 8 / 30 F19MANU.doc

E.G.Data creazione 01/11/99 17.27

SAA5297A
TO CURRENT INTEGRATOR VOLTAGE SINTESYS ONLY TO X13 FRANCE STD. SWITCH CTI DETECTOR 16 : 9 DETECTOR SCART1 / SCART2 SWITCH SCART 1 / TV TO SCART 2 SWITCH FRONT CINCH / SCART1 SWITCH SCART 1 INPUT DETECTOR SCART 2 INPUT DETECTOR HEAD PHONES DETECTOR STANDARD SWITCH

MICRO & TXT Block Diagram

ROM RAM TIMER

UHF SUPPLY (VOLTAGE SINTESYS ONLY) TV / AV SWITCH

MENU V - V + P -

P+

LOCAL KEY BOARD

TV ON / OFF SWITCH TUNER SUPPLY (V.S. ONLY) TUNER SUPPLY(V.S. ONLY)

CVBS FROM ANTENNA CVBS FROM SCART SAA5297A.DRW E.G . 17 / 10 / 99 DATA SLICER REF.PIN

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V TUN. DSC SWT. L/L' CTI STS. 16:9 STS SWT. S1/S2 COPY SWT. SWT. CI/S1 AV1 STS. AV2 STS. H.P. STS. SYSTEM VSS M+T UHF TV / AV P0.3 P0.4 P0.5 ON / OFF VHF H VHF L VSSA CVBS0 CVBS1 BLACK IREF

P O R T 2

A/ D

P O R T 3

PWM

B U S

D TI ISP M LA IN Y G

P O R T 0

TXT INT

PAGE RAM

T X T DATA SLICER & ACQUISITION

SWT 16:9 P OSC. SWT. O MSDA R MSCL T SDA 1 1 INTO SCL 1 AM/FM 8051 VDDM CORE RESET OSCOUT R O OSCIN AT L L CI OSCGND OS VDDT VDDA VSYNC HSYNC BLK R G B RGBREF PIP STS INT. TEST FRAME

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TO CHANGE ASPECT RATIO TO SWITCH S.C. FROM 4.43 TO 3.58 MHz

MAIN IIC BUS

I.R.

IIC BUS FOR EEPROM

SOUND STANDARD SWITCH 5 V from ST-BY FROM RESESET CIRCUIT

QZ100 12 MHz 5V
VERTICAL FLYBACK HORIZONTAL FLYBACK PULSE

TO TDA884X
RGB REFERENCE

DI SP LA Y

2,5 VVOLTAGE
PIP DETECTOR NOT CONNECTED

NOT CONNECTED

SAA5553M3
TO CURRENT INTEGRATOR VOLTAGE SINTESYS ONLY TO X13 FRANCE STD. SWITCH CTI DETECTOR 16 : 9 DETECTOR SCART1 / SCART2 SWITCH SCART 1 / TV TO SCART 2 SWITCH FRONT CINCH / SCART1 SWITCH SCART 1 INPUT DETECTOR SCART 2 INPUT DETECTOR HEAD PHONES DETECTOR STANDARD SWITCH

MICRO & TXT Block Diagram

RAM TIMER
P O R T 1

UHF SUPPLY (VOLTAGE SINTESYS ONLY) TV / AV SWITCH

MENU V - V + P -

P+

LOCAL KEY BOARD

TV ON / OFF SWITCH TUNER SUPPLY (V.S. ONLY) TUNER SUPPLY(V.S. ONLY)

CVBS FROM ANTENNA CVBS FROM SCART DATA SLICER REF.PIN

SAA5553.DRW E.G 22/ 04 / 2000

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

V TUN. DSC SWT. L/L' CTI STS. 16:9 STS SWT. S1/S2 COPY SWT. SWT. CI/S1 AV1 STS. AV2 STS. H.P. STS. SYSTEM VSS M+T UHF TV / AV P0.3 P0.4 P0.5 ON / OFF VHF H VHF L VSSA CVBS0 CVBS1 BLACK IREF

ROM
P O R T 2

A/ D

P O R T 3

PWM

B U S

8051 CORE
R TO A LL CI S O

DI TI SP M LA IN Y G

P O R T 0

TXT INT

PAGE RAM

T X T DATA SLICER & ACQUISITION

SWT 16:9 OSC. SWT. MSDA MSCL SDA 1 INTO SCL 1 AM/FM VDDM RESET OSCOUT OSCIN OSCGND VDDT VDDA VSYNC HSYNC BLK R G B RGBREF PIP STS INT. TEST FRAME

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TO CHANGE ASPECT RATIO TO SWITCH S.C. FROM 4.43 TO 3.58 MHz

MAIN IIC BUS I.R.

IIC BUS FOR EEPROM

SOUND STANDARD SWITCH 5 V from ST-BY FROM RESESET CIRCUIT

QZ100 12 MHz 3V
VERTICAL FLYBACK HORIZONTAL FLYBACK PULSE

TO TDA884X
RGB REFERENCE

DI SP LA Y

2,5 V VOLTAGE
PIP DETECTOR NOT CONNECTED

NOT CONNECTED

Real-time packet 26 engine for processing accented (and other) characters Comprehensive Teletext language coverage Video signal quality detector.

Teletext Display 525-line and 625-line display 12 10 character matrix

Double height, width and size On-Screen Display (OSD) Definable border colour Enhanced display features including meshing and shadowing 260 characters in mask programmed ROM Automatic FRAME output control with manual override RGB push-pull output to standard decoder ICs Stable display via slave synchronisation to horizontal sync and vertical sync.

Additional features of SAA529xA devices Wide Screen Signalling (WSS) bit decoding (line 23).

2 GENERAL DESCRIPTION The SAA529x, SAA529xA and SAA549x family of microcontrollers are a derivative of the Philips industry-standard 80C51 microcontroller and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system and include an integrated teletext function. The teletext hardware has the capability of decoding and displaying both 525-line and 625line World System Teletext. The same display hardware is used both for Teletext and OnScreen Display, which means that the display features give greater flexibility to differentiate the TV set. The family offers both 1 page and 10 page Teletext capability, in a range of ROM sizes. Increasing display capability is offered from the SAA5290 to the SAA5497.

TELETEXT DECODER Data slicer E.G.Data creazione 01/11/99 17.27 9 / 30 F19MANU.doc

The data slicer extracts the digital teletext data from the incoming analog waveform. This is performed by sampling the CVBS waveform and processing the samples to extract the teletext data and clock. Acquisition timing The acquisition timing is generated from a logic level positive-going composite sync signal VCS. This signal is generated by a sync separator circuit which adaptively slices the sync pulses. The acquisition clocking and timing are locked to the VCS signal using a digital phase-locked-loop. The phase error in the acquisition phase-locked-loop is detected by a signal quality circuit which disables acquisition if poor signal quality is detected. Teletext acquisition This family is capable of acquiring 625-line and 525-line World System Teletext see World System Teletext and Data Broadcasting System. Teletext pages are identified by seven numbers: magazine (page hundreds), page tens, page units, hours tens, hours units, minutes tens and minutes units. The last four digits, hours and minutes, are known as the subcode, and were originally intended to be time related, hence their names. For the ten page device, each packet can only be written into one place in the teletext RAM so if a page matches more than one of the page requests the data is written into the area of memory corresponding to the lowest numbered matching page request. At power-up each page request defaults to any page, hold on and error check Mode 0. Rolling headers and time When a new page has been requested it is conventional for the decoder to turn the header row of the display green and to display each page header as it arrives until the correct page has been found. Error checking Before teletext packets are written into the page memory they are error checked. The error checking carried out depends on the packet number, the byte number, the error check mode bits in the page request data and the TXT1.8 BIT bit. If an uncorrectable error occurs in one of the Hamming checked addressing and control bytes in the page header or in the Hamming checked bytes in packet 8/30, bit 4 of the byte written into the memory is set, to act as an error flag to the software. If uncorrectable errors are detected in any other Hamming checked data the byte is not written into the memory. E.G.Data creazione 01/11/99 17.27 10 / 30 F19MANU.doc

Packet 26 processing One of the uses of packet 26 is to transmit characters which are not in the basic teletext character set. The family automatically decodes packet 26 data and, if a character corresponding to that being transmitted is available in the character set, automatically writes the appropriate character code into the correct location in the teletext memory. This is not a full implementation of the packet 26 specification allowed for in level 2 teletext, and so is often referred to as level 1.5. By convention, the packets 26 for a page are transmitted before the normal packets. To prevent the default character data overwriting the packet 26 data the device incorporates a mechanism which prevents packet 26 data from being overwritten. Fastext detection When a packet 27, designation code 0 is detected, whether or not it is acquired, the TXT13.FASTEXT bit is set. If the device is receiving 525-line teletext, a packet X/0/27/0 is required to set the flag. The flag can be reset by writing a logic 0 into the SFR bit. When a packet 8/30 is detected, or a packet 4/30 when the device is receiving a 525-line transmission, the TXT13.Pkt 8/30 is set. The flag can be reset by writing a logic 0 into the SFR bit. THE DISPLAY Introduction The capabilities of the display are based on the requirements of level 1 teletext, with some enhancements for use with locally generated on screen displays. The display consists of 25 rows each of 40 characters, with the characters displayed being those from rows 0 to 24 of the basic page memory. If the TXT7.STATUS ROW TOP bit is set row 24 is displayed at the top of the screen, followed by row 0, but normally memory rows are displayed in numerical order. The teletext memory stores 8 bit character codes which correspond to a number of displayable characters and control characters, which are normally displayed as spaces. The character set of the device is described in more detail below.

E.G.Data creazione 01/11/99 17.27

11 / 30

F19MANU.doc

(OPTION BYTE 1 BIT 3 SETTED TO 0

EAST EUROPE
CHARACTER SET NATIONAL OPTION FOR:

POLISH GERMAN ESTONIAN SERBO-CROAT CZECH SLOVAKIA RUMANIAN WEST EUROPE

CHARACTER SET NATIONAL OPTION FOR:

WEST ENGLISH GERMAN SWEDISH ITALIAN FREANCH SPANISH TURKISH

EAST

D A

PL CZ H Y

(OPTION BYTE 1 BIT 6 SETTED TO 1

F19 E&WCS.DRW E.G. 7/11/99

Character matrix Each character is defined by a matrix 12 pixels wide and 10 pixels high. When displayed, each pixel is 1 12 s wide and 1 TV line, in each field, high.

East/West selection In common with their predecessors, these devices store teletext pages as a series of 8 bit character codes which are interpreted as either control codes (to change colour, invoke flashing etc.) or displayable characters. When the control characters are excluded, this gives an addressable set of 212 characters at any given time.

National option characters The meanings of some character codes between 20H and 7FH depend on the C12 to C14 language control bits from the teletext page header. The interpretation of the C12 to C14 language control bits is dependent on the East/West bit. On-Screen Display characters Character codes 80H to 9FH are not addressed by the teletext decoding hardware. An editor is available to allow these characters to be redefined by the customer. The

alternative character shapes in columns 8a and 9a (SAA549x only) can be displayed when the graphics serial attribute is set. This increases the number of customer definable characters to 64. Clock generator The oscillator circuit is a single-stage inverting amplifier in a Pierce oscillator configuration. The circuitry between XTALIN and XTALOUT is basically an inverter biased to the transfer point. A crystal must be used as the feedback element to complete the oscillator circuitry. It is operated in parallel resonance. XTALIN is the high gain amplifier input and XTALOUT is the output. To drive the device externally XTALIN is driven from an external source and XTALOUT is left open-circuit.

E.G.Data creazione 01/11/99 17.27

12 / 30

F19MANU.doc

12 V

SOUND I.F. AM SOUND FILTER F204 12V TR218

TUNUNG VOLTAGE TO PIN 2 TR500 TUNER

SAA5297A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

MICRO & TXT PERIPHERALS

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
TO CTI & 16:9 MOULE TR 109 TR 208 4.43 MHz

TO X13

TR219 5V

R174

CVBS PIN 6 IC 204

TO PIN 10, 11 IC 200

TO PIN 4 IC 201 TO PIN 8 IC 201

R128 R140 R141

TR200

TR110 TR201 F575 5V TO PIN 1 IC 204 F576 TR210 TR111 TR107 TO STEREO NICAM MODULE TO SWITC INT/EX SOUND R146 TR209 FRON PIN 8 SCART 1 FROM PIN 8 SCART 2

MENU V - V + P -

P+

TO PIN 4 IC 10

TR2

TV ON / OFF

TR 502 PIN 5 CVBS FROM ANTENNA TR 501 PIN 3 TR203

T O T U N E R PIN 4

TR503

CVBS FROM SCART TR211

5V

V TUN. SWT 16:9 OSC. SWT. DSC SWT. L/L' MSDA MSCL CTI STS. SDA 1 16:9 STS SWT. S1/S2 INTO COPY SWT. SCL 1 SWT. CI/S1 AM/FM VDDM AV1 STS. AV2 STS. RESET H.P. STS. OSCOUT OSCIN SYSTEM VSS M+T OSCGND VDDT UHF VDDA TV / AV VSYNC P0.3 HSYNC P0.4 BLK P0.5 R ON / OFF G VHF H B VHF L RGBREF VSSA PIP STS CVBS0 COR CVBS1 BLACK INT. TEST FRAME IREF

TR206 IIC BUS 3.58MHz TR 205 TO PIN 35 IC 204

IRR100

IIC BUS

EEPROM IC 101
TO PIN 10 IC 102 TR 105

SOUND STDANDARD SWITCH

TR 108

5V ST-BY

QZ100 12 MHz
R 106

D 105

5V
D 102 FLYBACK PULSE FROM EHT VERTICAL BLANKING FROM PIN 8 IC 5

D 108

TR 101 TR 102 TR 103 5V R167

TO PIN 23, 24, 25 IC 204

F19MTPER.DRW E.G. 24 /10 /99 FOR VOLTAGE SISTETIZER ONLY

12 V

SOUND I.F. AM SOUND FILTER F204 12V CVBSPIN 6 IC 204 TO PIN 10, 11 IC 200 TR218

TUNUNG VOLTAGE TO PIN 2 TUNER

TR500

SAA 5553 MICRO

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

& TXT PERIPHERALS

TO CTI & 16:9 MOULE TR 109 TR 208 4.43 MHz

TO X13

TR219 5V

R174

TO PIN 4 IC 201 TO PIN 8 IC 201 TR110

R128 R140 R141

TR200 TR201 F575

FRON PIN 8 SCART 1 FROM PIN 8 SCART 2 5V

TO PIN 1 IC 204 F576 TR210

R146 TR209 TR111

TR107 TO STEREO NICAM MODULE

TO SWITC INT/EX SOUND

MENU V - V + P -

P+

TO PIN 4 IC 10

TR2

TV ON / OFF

TR 502

PIN 5
T O T U N E R PIN 4 PIN 3 TR 501

CVBS FROM ANTENNA TR203

TR503

CVBS FROM SCART TR211 5V

V TUN. SWT 16:9 DSC OSC. SWT. SWT. L/L' MSDA MSCL CTI STS. SDA 1 16:9 STS SWT. S1/S2 INTO COPY SWT. SCL 1 SWT. CI/S1AM/FM AV1 STS. VDDM AV2 STS. RESET H.P. STS. OSCOUT SYSTEM OSCIN VSS M+T OSCGND VDDT UHF VSSA TV / AV VSYNC P0.3 HSYNC P0.4 BLK P0.5 R ON / OFF G VHF H B VHF L RGBREF VSSA PIP STS CVBS0 COR CVBS1 BLACK INT. TEST FRAME IREF

52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27

TR206 IIC BUS 3.58MHz

TR 205

TO PIN 35 IC 204

IRR100

IIC BUS

EEPROM IC 101
TO PIN 10 IC 102 TR 105

SOUND STDANDARD SWITCH 3,3 V

TR 108
TR8

5V
R39 R40

QZ100 12 MHz

D 105

3,3 V 5V D 108 D 102

TR7 D5 2,5V FLYBACK FROM EHT VERTICAL BLANKING FROM PIN 8 IC 5 TO PIN 23, 24, 25 IC 204

TR 101 TR 102

TR 103
5V R167 F19PAPER.DRW E.G. 22 / 04 /2000 FOR VOLTAGE SISTETIZER ONLY

PAINTER

VIDEO SIGNAL PROCESSING

FOR VOLTAGE SINTHESIS ONLY

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SIF AUDEXT NC NC PLLIF IFVIDEO OUT SCL SDA DECOUPLING CHR.IN EX.CVBS/Y IN VP1 INT CVBS IN GND AUDIO OUT DECOUPLING EX. CVBS IN BLKIN B OUT G OUT R OUT BCL/VG R IN G IN B IN RGB INSERT. Y IN Y OUT

TR500 UV 1 2 3 4 5 6 7 8 9 10 11 UHF

TDA884X
I.F. VIDEO AGC AFC DEM. IDENT

EF

EF
TR200 IIC

F 19
TO PIN 33 IC100 CVBS EF FOR TXT TR203 TO PIN 24 IC 100 (CVBS FOR TXT) TO PIN 9 IC 100 AV1 STATUS 19 8 15 11 7 16 20

TR201

MSD PAL (SECAM) NTSC

TR202

EF
VIDEO IN CINCH

SOUND PROCES. (MONO)

C.D. & RGB MATRIX VIDEO CONTROL

EF
TR204

SYNC PROCES. V. & H. TIME BASE

EXT RGB SWITCH & RGB DRIVE

SCART 1

IIC
TRANSRECEIVER

DECOUPLING DEENPHASIS AGC OUT DECOPLING I REF VERT. RAMP EHT PROTEC. IF IN 2 IF IN 1 V. DRIVE A V. DRIVE B E - W OUT GND 2 PH. 1 FILTER PH. 2 FILTER H. IN, S.C. OUT HOR. OUT DECOUPLING CVBS 1 OUT VP2 DET FILTER X TAL 2 X TAL 1 S.C. REF OUT R - Y IN B - Y IN R - Y OUT B - Y OUT

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

FROM PIN 1 IC 100 TR501 5V

TR503

IIC

VHF H VHF L TR502

FROM IC 100 PIN 14, 20, 21 BAND SWITCHING TR105

TR208 3.58MHz 8V 4.43MHz 3,57MHz FROM PIN 51 IC 100 TR205 TR206

A10
1 2 3 4 5

CTI & 4:3 TO 16 : 9

12 V TR211

EF
FROM PIN 6 IC100 AV1 / AV2 SWITCH CVBS IN TV CVBS FROM PIN 7 IC100 AV1 / TV SWITCH TO AV2 3 2 TO PIN 10 IC 100 AV2 STATUS 7 8 9 12 V 4 1 6 5 TR212 CVBS OUT

EF
5V

EF
SCART 2 8 20 19

RGB AMPLIFIER MODULE

6 7 8 9 10 11 12

1/3 0F IC201 LA7955

CVBS IN

FROM PIN 52 IC 100 4:3 TO 16:9 SWITCH

TO CRT
8V

FROM EHT

VIDEO SIGNAL PATH

F19VIDEP.DRW E.G. 14 / 11 / 99

Reset signal The externally applied RESET signal (active HIGH) is used to initialize the microcontroller core, in addition to the teletext decoder. However, the teletext decoder incorporates a separate internal reset function which is activated on the rising edge of the analog supply pin, VDDA . The purpose of this internal reset circuit is to initialize the teletext decoder when returning from the text standby mode.

TDA884X FAMILY SPECIFICATION

FEATURES

The following features are available in all ICs: Multi-standard vision IF circuit with an alignment-freePLL demodulator without external components Alignment-free multi-standard FM sound demodulator(4.5 MHz to 6.5 MHz) Audio switch Flexible source selection with CVBS switch andY(CVBS)/C input so that a comb filter can be applied Integrated chrominance trap circuit Integrated luminance delay line Asymmetrical peaking in the luminance channel with a(defeatable) noise coring function Black stretching of non-standard CVBS or luminancesignals Integrated chroma band-pass filter with switchablecentre frequency Dynamic skin tone control circuit Blue stretch circuit which offsets colours near whitetowards blue RGB control circuit with Continuous CathodeCalibration and white point adjustment Possibility to insert a blue back option when no videosignal is available Horizontal synchronization with two control loops andalignment-free horizontal

oscillatoroptimised N2 application.Functionally the IC series is split up is 3 categories, viz:

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F19MANU.doc

CVBS OUT CVBS (int) IN CVBS / Y IN (comb filter) CVBS OUTPUT CVBS (ext) IN CHROMA IN

Secam Decoupling SCL SDA

Xtal 34 35 36 33 28 29
BASE BAND CHROMA DELAY LINE

Loop filter Phase Detector

6
TUNER AGC

13

17

11
CVBS & Y/C SWITCH

10

38

54 53 48

IF & TUNER A G C

TUNER T.O.P gating calibration I.F. value IIC TRANSRECEIVER

16

BURST PHASE DETECTOR & VCXO

Subcarrier

IIC
I.F IN PLL FILTER VIDEO IF AMPLIFIER PLL DEMOD. & VCO MOD Pos./Neg. VIDEO AMPLIFIER Luma Y DELAY, C. TRAP, Y PEAKING Chroma CHROMA CLOCHE & BANDPASS

Fsc Y B-Y R-Y Y B-Y R-Y R G B F.B.

Black O Currente U Input T R P U G T I N P U T

49
Sensitivity

5
A F W AFA AFB AFC

To Sync

PAL / NTSC SECAM DECODER

GAI AUTO SYSTEM IDENT. MANAGER V. sync

30 27 31 32 23 24 25 26 18

H. SYNC
SEPARATOR

V . SYNC
SEPARATOR

SAT

MAT

TDA 8844
55
Deenphasis DEENPHASIS LINE Internal Audio EXTERNAL AUDIO SWITCH SWT MONO AUDIO OUTPUT

H. sync VIDEO IDENT. VIDEO MUTE

DSA VERTICAL DEVIDER

PHI 1
DETECTOR

R-Y & B-Y MATRIX SAT CONTR. BLACK STRETCH SKIN TINT CORR. RGB SWITCH

AVL

CON
AUDIO PRE AMPLIFIER & MUTE

2
EXTERNAL AUDIO IN

AVL
SWITCH & VOLUME Volume

LINE
OSCILL.

VERTICAL SAWTOOTH GENERATOR

A.F.
AVL Decoupling

15 (45) 1

RGB CONTROL AUTO CUT-OFF & OUTPUT BRI

19 20 21 47

B Vertical Drive Output

INTERCARRIER IN BandGap Decoupling

1 A 10 MHz B.P.F.

AUDIO LIMITER

AUDIO PLL DEM.

PHI 2 LINE OUT S.C. GENER.

E-W GEOMETRY

VERTICAL DRIVE

46

12
8 V Main Supply

37
8V Supply

14
Ground

56
Sound Decoupling

43

42
Phi 2 filter

41

40

51

52

45

50
EHT Overvoltage

22
V- Guard & B.C. limiter TDA8844BLDIA.DRW E.G. 17 /10 / 99

Phi 1 filter

Flyback in Line E-W Sand Pulse DRIVE Vertical Castle Out Sawtooth Reference Out

 Versions intended to be used in economy TV receiverswith all basic functions (envelope: S-DIP 56 and QFP 64) Versions with additional features like E-W geometrycontrol, H-V zoom function and YUV interface which are intended for TV receivers with 110 picture tubes(envelope: S-DIP 56) Versions which have in addition a second RGB inputwith saturation control and a second CVBS output (envelope: QFP 64) Vertical count-down circuit Vertical driver optimised for DC-coupled vertical outputstages
GENERAL DESCRIPTION

The various versions of the TDA 884X/5X series areI 2 C-bus controlled single chip TV processors which are intended to be applied in PAL, NTSC, PAL/NTSC and multi-standard television receivers. The N2 version is pin and application compatible with the N1 version, however,a new feature has been added which makes the N2 more attractive. The IF PLL demodulator has been replaced byan alignment-free IF PLL demodulator with internal VCO (no tuned circuit required). The setting of the variousfrequencies (33.4, 33.9, 38, 38.9, 45,75 and 58.75 MHz) can be made via the I 2 C-bus. Because of this difference the N2 version is compatiblewith the N1, however, N1 devices cannot be used in an optimized N2 application Functionally the IC series is split up is 3 categories, viz: Versions intended to be used in economy TV receivers with all basic functions (envelope: S-DIP 56 and QFP 64) Versions with additional features like E-W geometry control, H-V zoom function and YUV interface which areintended for TV receivers with 110 picture tubes (envelope: S-DIP 56) Versions which have in addition a second RGB input with saturation control and a second CVBS output (envelope: QFP 64)

FUNCTIONAL DESCRIPTION Vision IF amplifier

The IF-amplifier contains 3 ac-coupled control stages with a total gain control range which is higher then 66 dB. The sensitivity of the circuit is comparable with that of modern E.G.Data creazione 01/11/99 17.27 14 / 30 F19MANU.doc

IF-ICs. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internalVCO. This VCO is calibrated by means of a digital control circuit which uses the X-tal frequency of the colour decoder as a reference. The frequency setting for the various standards (33.4, 33.9, 38, 38.9, 45.75 and 58.75 MHz) is realised via the I 2 Cbus. To get a good performance for phase modulated carrier signals the control speed of the PLL can be increased by means of the FFI bit. The AFC output is generated by the digital control circuit of the IF-PLL demodulator and can be read via the I 2 C-bus. For fast search tuning systems the window of the AFC can be increased with a factor 3. The setting is realised with the AFW bit. The AFC data is valid only when the horizontal PLL is in lock (SL = 1) Depending on the type the AGC-detector operates on top-sync level (single standard versions) or on top sync and top white- level (multi standard versions). The demodulation polarity is switched via the I 2 C-bus. The AGC detector time-constant capacitor is connected externally. This mainly because of the flexibility of the application. The timeconstant of the AGC system during positive modulation is rather long to avoid visible variations of the signal amplitude. To improve the speed of the AGC system a circuit has been included which detects whether the AGC detector is activated every frame period. When during 3 field periods no action detected the speed of the system is increased. For signals without peak white information the system switches automatically to a gated black level AGC. Because a black level clamp pulse is required for this way of operation the circuit will only switch to black level AGC in the internal mode. The circuits contain a video identification circuit which is independent of the synchronisation circuit. Therefore search tuning is possible when the display section of the receiver is used as a monitor. However, this ident circuit cannot be made as sensitive as the slower sync ident circuit (SL) and we recommend to use both ident outputs to obtain a reliable search system. The ident output is supplied to the tuning system via the I 2 C-bus. The input of the identification circuit is connected to pin 13 (S-DIP 56 devices), the internal CVBS input (see Fig.6). This has the advantage that the ident circuit can also be made operative when a scrambled signal is received (descrambler connected between pin 6 (IF video output) and pin 13). A second advantage is that the ident circuit can be used when the IF amplifier is not used (e.g. with built-in satellite tuners). E.G.Data creazione 01/11/99 17.27 15 / 30 F19MANU.doc

The video ident circuit can also be used to identify the selected CBVS or Y/C signal. The switching between the 2 modes can be realised with the VIM bit.
Video switches

The circuits have two CVBS inputs (internal and external CVBS) and a Y/C input. When the Y/C input is not required the Y input can be used as third CVBS input. The switch configuration is given in Fig.6. The selection of the various sources is made via the I 2 Cbus. For the TDA 884X devices the video switch configuration is identical to the switch of the TDA 8374/75 series. So the circuit has one CVBS output (amplitude of 2 VP-P for the TDA884X series) and the I 2 C-bus control is similar to that of the TDA 8374/75. For the TDA 885X ICs the video switch circuit has a second output (amplitude of 1 VP-P ) which can be set independently of the position of the first output. The input signal for the decoder is also available on the CVBS1-output. Therefore this signal can be used to drive the Teletext decoder. If S-VHS is selected for one of the outputs the luminance and chrominance signals are added so that a CVBS signal is obtained again.
Sound circuit

The sound bandpass and trap filters have to be connected externally. The filtered intercarrier signal is fed to a limiter circuit and is demodulated by means of a PLL demodulator. This PLL circuit tunes itself automatically to the incoming carrier signal so that no adjustment is required. The volume is controlled via the I 2 C-bus. The deemphasis capacitor has to be connected externally. The non-controlled audio signal can be obtained from this pin (via a buffer stage). The FM demodulator can be muted via the I 2 C-bus. This function can be used to switchoff the sound during a channel change so that high output peaks are prevented. The TDA 8840/41/42/46 contain an Automatic Volume Levelling (AVL) circuit which automatically stabilises the audio output signal to a certain level which can be set by the viewer by means of the volume control. This function prevents big audio output fluctuations due to variations of the modulation depth of the transmitter. The AVL function can be activated via the I 2 C-bus.
Synchronisation circuit

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The sync separator is preceded by a controlled amplifier which adjusts the sync pulse amplitude to a fixed level. These pulses are fed to the slicing stage which is operating at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. This coincidence detector is used to detect whether the line oscillator is synchronised and can also be used for transmitter identification. This circuit can be made less sensitive by means of the STM bit. This mode can be used during search tuning to avoid that the tuning system will stop at very weak input signals. The first PLL has a very high statical steepness so that the phase of the picture is independent of the line frequency. The horizontal output signal is generated by means of an oscillator which is running at twice the line frequency. Its frequency is divided by 2 to lock the first control loop to the incoming signal. The time-constant of the loop can be forced by the I 2 C-bus (fast or slow). If required the IC can select the time-constant depending on the noise content of the incoming video signal. The free-running frequency of the oscillator is determined by a digital control circuit which is locked to the reference signal of the colour decoder. When the IC is switched-on the horizontal output signal is suppressed and the oscillator is calibrated as soon as all subaddress bytes have been sent. When the frequency of the oscillator is correct the horizontal drive signal is switched-on. To obtain a smooth switching-on and switching-off behaviour of the horizontal output stage the horizontal output frequency is doubled during switch-on and switch-off (slow start/stop). During that time the duty cycle of the output pulse has such a value that maximum safety is obtained for the output stage. To protect the horizontal output transistor the horizontal drive is immediately switched off when a power-on-reset is detected. The drive signal is switched-on again when the normal switch-on procedure is followed, i.e. all sub-address bytes must be sent and after calibration the horizontal drive signal will be released again via the slow start procedure. When the coincidence detector indicates an out-of-lock situation the calibration procedure is repeated. The circuit has a second control loop to generate the drive pulses for the horizontal driver stage. The horizontal output is gated with the flyback pulse so that the horizontal output transistor cannot be switched-on during the flyback time. Via the I 2 C-bus adjustments can be made of the horizontal and vertical geometry. The vertical sawtooth generator drives the vertical output drive circuit which has a differential output current. For the E-W drive a single ended current output is available. A special E.G.Data creazione 01/11/99 17.27 17 / 30 F19MANU.doc

feature is the zoom function for both the horizontal and vertical deflection and the vertical scroll function which are available in some versions. When the horizontal scan is reduced to display 4:3 pictures on a 16:9 picture tube an accurate video blanking can be switched on to obtain well defined edges on the screen. Overvoltage conditions (X-ray protection) can be detected via the EHT tracking pin. When an overvoltage condition is detected the horizontal output drive signal will be switched-off via the slow stop procedure but it is also possible that the drive is not switched-off and that just a protection indication is given in the I 2 C-bus output byte. The choice is made via the input bit PRD. The ICs have a second protection input on the 2 filter capacitor pin. When this input is activated the drive signal is switched-off immediately and switched-on again via the slow start procedure. For this reason this protection input can be used as flash protection. The drive pulses for the vertical sawtooth generator are obtained from a vertical countdown circuit. This countdown circuit has various windows depending on the incoming signal (50 Hz or 60 Hz and standard or non standard). The countdown circuit can be forced in various modes by means of the I 2 C-bus. During the insertion of RGB signals the maximum vertical frequency is increased to 72 Hz so that the circuit can also synchronise on signals with a higher vertical frequency like VGA. To obtain short switching times of the countdown circuit during a channel change the divider can be forced in the search window by means of the NCIN bit. The vertical deflection can be set in the deinterlace mode via the I 2 C bus. To avoid damage of the picture tube when the vertical deflection fails the guard output current of the TDA 8350/51 can be supplied to the beam current limiting input. When a failure is detected the RGB-outputs are blanked and a bit is set (NDF) in the status byte of the I 2 C-bus. When no vertical deflection output stage is connected thisguard circuit will also blank the output signals. This can be overruled by means of the EVG bit.
Chroma and luminance processing

The circuits contain a chroma bandpass and trap circuit. The filters are realised by means of gyrator circuits and they are automatically calibrated by comparing the tuning frequency with the X-tal frequency of the decoder. The luminance delay line and the delay for the peaking circuit are also realised by means of gyrator circuits. The centre frequency of the chroma bandpass filter is switchable via the I 2 C-bus so that the performance can be optimised for

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F19MANU.doc

front-end signals and external CVBS signals. During SECAM reception the centre frequency of the chroma trap is reduced to get a better suppression of the SECAM carrier frequencies. All ICs have a black stretcher circuit which corrects the black level for incoming video signals which have a deviation between the black level and the blanking level (back porch). The timeconstant for the black stretcher is realised internally. The resolution of the peaking control DAC has been increased to 6 bits. All ICs have a defeatable coringfunction in the peaking circuit. Some of these ICs have a YUV interface (see table on page 2) so that picture improvement ICs like the TDA 9170 (Contrast improvement), TDA 9177 (Sharpness improvement) and TDA 4556/66 (CTI) can be applied. When the CTI ICs are applied it is possible to increase the gain of the luminance channel by means of the GAI bit in subaddress 03 so that the resulting RGB output signals are not affected.
Colour decoder

Depending on the IC type the colour decoder can decode PAL, PAL/NTSC or PAL/NTSC/SECAM signals. The PAL/NTSC decoder contains an alignment-free X-tal oscillator, a killer circuit and two colour difference demodulators. The 90 phase shift for the reference signal is made internally. The ICs contain an Automatic Colour Limiting (ACL) circuit which is switchable via the I 2 C-bus and which prevents that oversaturation occurs when signals with a high chroma-toburst ratio are received. The ACL circuit is designed such that it only reduces the chroma signal and not the burst signal. This has the advantage that the colour sensitivity is not affected by this function. The SECAM decoder contains an auto-calibrating PLL demodulator which has two references, viz: the 4.4 MHz sub-carrier frequency which is obtained from the X-tal oscillator which is used to tune the PLL to the desired free-running frequency and the bandgap reference to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search or SECAM mode. The frequency of the active X-tal is fed to the Fsc output (pin 33) and can be used to tune an external comb filter (e.g. the SAA 4961). The base-band delay line (TDA 4665 function) is integrated in the PAL/SECAM ICs and in the NTSC IC TDA 8846A. In the latter IC it improves the cross colour performance (chroma comb filter). The demodulated colour difference signals are internally supplied to the delay line. The colour difference matrix switches automatically between PAL/SECAM and NTSC, however, it is also possible to fix the matrix in the PAL standard. E.G.Data creazione 01/11/99 17.27 19 / 30 F19MANU.doc

The blue stretch circuit is intended to shift colour near white with sufficient contrast values towards more blue to obtain a brighter impression of the picture. Which colour standard the ICs can decode depends on the external X-tals. The X-tal to be connected to pin 34 must have a frequency of 3.5 MHz (NTSC-M, PAL-M or PAL-N) and pin 35 can handle X-tals with a frequency of 4.4 and 3.5 MHz. Because the X-tal frequency is used to tune the line oscillator the value of the X-tal frequency must be given to the IC via the I 2 C-bus. It is also possible to use the IC in the so called Tri-norma mode for South America. In that case one X-tal must be connected to pin 34 and the other 2 to pin 35. The switching between the 2 latter X-tals must be done externally. This has the consequence that the search loop of the decoder must be controlled by the -computer. To prevent calibration problems of the horizontal oscillator the external switching between the 2 X-tals should be carried out when the oscillator is forced to pin 34. For a reliable calibration of the horizontal oscillator it is very important that the X-tal indication bits (XA and XB) are not corrupted. For this reason the X-tal bits can be read in the output bytes so that the software can check the I 2 C-bus transmission. Under bad-signal conditions (e.g. VCR-playback in feature mode), it may occur that the colour killer is activated although the colour PLL is still in lock. When this killing action is not wanted it is possible to overrule the colour killer by forcing the colour decoder to the required standard and to activate the FCO-bit (Forced Colour On) in the control-5 subaddress. The ICs contain a so-called Dynamic skin tone (flesh) control feature. This function is realised in the YUV domain by detecting the colours near to the skin tone. The correction angle can be controlled via the I 2 C-bus.
RGB output circuit and black-current stabilisation

The colour-difference signals are matrixed with the luminance signal to obtain the RGBsignals. The TDA 884X devices have one (linear) RGB input. This RGB signal can be controlled on contrast and brightness (like TDA 8374/75). By means of the IE1 bit the insertion blanking can be switched on or off. Via the IN1 bit it can be read whether the insertion pin has a high level or not. The TDA 885X ICs have an additional RGB input. This RGB signal can be controlled on contrast, saturation and brightness. The insertion blanking of this input can be switched-off by means of the IE2 bit. Via the IN2 bit it can be read whether the insertion pin has a high level or not.

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The output signal has an amplitude of about 2 volts black-to-white at nominal input signals and nominal settings of the controls. To increase the flexibility of the IC it is possible to insert OSD and/or teletext signals directly at the RGB outputs. This insertion mode is controlled via the insertion input (pin 26 in the S-DIP 56- and pin 38 in the QFP-64 envelope). This blanking action at the RGB outputs has some delay which must be compensated externally. To obtain an accurate biasing of the picture tube a Continuous Cathode Calibration circuit has been developed. This function is realised by means of a 2-point black level stabilisation circuit. By inserting 2 test levels for each gun and comparing the resulting cathode currents with 2 different reference currents the influence of the picture tube parameters like the spread in cut-off voltage can be eliminated. This 2-point stabilisation is based on the principle that the ratio between the cathode currents is coupled to the ratio between the drive voltages according to:

[ I ki / Ik2 ] = [ Vdr1 / Vdr2 ]

The feedback loop makes the ratio between the cathode currents Ik1 and Ik2 equal to the ratio between the reference currents (which are internally fixed) by changing the (black) level and the amplitude of the RGB output signals via 2 converging loops. The system operates in such a way that the black level of the drive signal is controlled to the cut-off point of the gun so that a very good grey scale tracking is obtained. The accuracy of the adjustment of the black level is just dependent on the ratio of internal currents and these can be made very accurately in integrated circuits. An additional advantage of the 2-point measurement is that the control system makes the absolute value of Ik1 and Ik2 identical to the internal reference currents. Because this adjustment is obtained by means of an adaption of the gain of the RGB control stage this control stabilises the gain of the complete channel (RGB output stage and cathode characteristic). As a result variations in the gain figures during life will be compensated by this 2-point loop. An important property of the 2-point stabilisation is that the off-set as well as the gain of the RGB path is adjusted by the feedback loop. Hence the maximum drive voltage for the cathode is fixed by the relation between the test pulses, the reference current and the relative gain setting of the 3 channels. This has the consequence that the drive level of the CRT cannot be adjusted by adapting the gain of the RGB output stage. Because different picture tubes may require different drive levels the typical cathode drive level amplitude can be adjusted by means of an I 2 C-bus setting. Dependent on the chosen cathode drive E.G.Data creazione 01/11/99 17.27 21 / 30 F19MANU.doc

level the typical gain of the RGB output stages can be fixed taking into account the drive capability of the RGB outputs (pins 19 to 21). More details about the design will be given in the application report. The measurement of the high and the low current of the 2- point stabilisation circuit is carried out in 2 consecutive fields. The leakage current is measured in each field. The maximum allowable leakage current is 100 A When the TV receiver is switched-on the RGB output signals are blanked and the black current loop will try to set the right picture tube bias levels. Via the AST bit a choice can be made between automatic start-up or a start-up via the -processor. In the automatic mode the RGB drive signals are switched-on as soon as the black current loop has been stabilised. In the other mode the BCF bit is set to 0 when the loop is stabilised. The RGB drive can than be switched-on by setting the AST bit to 0. In the latter mod some delay can be introduced between the setting of the BCF bit and the switching of the AST bit so that switch-on effects can be suppressed. It is also possible to start-up the devices with a fixed internal delay (as with the TDA 837X and the TDA884X/5X N1). This mode is activated with the BCO bit. The vertical blanking is adapted to the incoming CVBS signal (50 Hz or 60 Hz). When the flyback time of the vertical output stage is longer than the 60 Hz blanking time the blanking can be increased to the same value as that of the 50 Hz blanking. This can be set by means of the LBM bit. For an easy (manual) adjustment of the Vg2 control voltage the VSD bit is available. When this bit is activated the black current loop is switched-off, a fixed black level is inserted at the RGB outputs and the vertical scan is switched-off so that a horizontal line is displayed on the screen. This line can be used as indicator for the Vg2 adjustment. Because of the different requirements for the optimum cut-off voltage of the picture tube the RGB output level is adjustable when the VSD bit is activated. The control range is 2.5 0.7 V and can be controlled via the brightness control DAC. It is possible to insert a so called blue back back-ground level when no video is available. This feature can be activated via the BB bit in the control2 subaddress.

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FOR VOLTAGE SINTHESIS ONLY

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
SIF AUDEXT NC NC PLLIF IFVIDEO OUT SCL SDA DECOUPLING CHR.IN EX.CVBS/Y IN VP1 INT CVBS IN GND AUDIO OUT DECOUPLING EX. CVBS IN BLKIN B OUT G OUT R OUT BCL/VG R IN G IN B IN RGB INSERT. Y IN Y OUT

TR500 UV 1 2 3 4 5 6 7 8 9 10 11 UHF

TDA884X
I.F. VIDEO AGC AFC DEM. IDENT

EF

EF
TR200 IIC

F 19
TO PIN 33 IC100 CVBS EF FOR TXT TR203 TO PIN 24 IC 100 (CVBS FOR TXT) TO PIN 9 IC 100 AV1 STATUS 19 8 15 11 7 16 20

TR201

MSD PAL (SECAM) NTSC

TR202

EF
VIDEO IN CINCH

SOUND PROCES. (MONO)

C.D. & RGB MATRIX VIDEO CONTROL

EF
TR204

SYNC PROCES. V. & H. TIME BASE

EXT RGB SWITCH & RGB DRIVE

SCART 1

IIC
TRANSRECEIVER

DECOUPLING DEENPHASIS AGC OUT DECOPLING I REF VERT. RAMP EHT PROTEC. IF IN 2 IF IN 1 V. DRIVE A V. DRIVE B E - W OUT GND 2 PH. 1 FILTER PH. 2 FILTER H. IN, S.C. OUT HOR. OUT DECOUPLING CVBS 1 OUT VP2 DET FILTER X TAL 2 X TAL 1 S.C. REF OUT R - Y IN B - Y IN R - Y OUT B - Y OUT

56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29

FROM PIN 1 IC 100 TR501 5V

TR503

IIC

VHF H VHF L TR502

FROM IC 100 PIN 14, 20, 21 BAND SWITCHING TR105

TR208 3.58MHz 8V 4.43MHz 3,57MHz FROM PIN 51 IC 100 TR205 TR206

A10
1 2 3 4 5

CTI & 4:3 TO 16 : 9

12 V TR211

EF
FROM PIN 6 IC100 AV1 / AV2 SWITCH CVBS IN TV CVBS FROM PIN 7 IC100 AV1 / TV SWITCH TO AV2 3 2 TO PIN 10 IC 100 AV2 STATUS 7 8 9 12 V 4 1 6 5 TR212 CVBS OUT

EF
5V

EF
SCART 2 8 20 19

RGB AMPLIFIER MODULE

6 7 8 9 10 11 12

1/3 0F IC201 LA7955

CVBS IN

FROM PIN 52 IC 100 4:3 TO 16:9 SWITCH

TO CRT
8V

FROM EHT

VIDEO SIGNAL PATH

F19VIDEP.DRW E.G. 14 / 11 / 99

IC204 TDA884X
26 23/24/25 19/20/21
RGB OUT

F19 RGB AMPLIFIER

12 V 200 V TO G1 TRC 3 1

18

RGB IN FAST BLK. IN RGB IN FROM SCART

R17,R18,R19 R215 R216 R217 R600 2 6/11/14 D800, D801, D802 9/12/15 E.F. R613 R614 R615 4/5/6 R604 R605 R606 1/3/4
TO RGB KATODE

7/10/13

STV 5112

F19 RGBCO.DRW E.G. 14 / 11 /99

3 X

F 19 FEATURE MODULE
Colour Transient Improvment

& 4 : 3 to 16 : 9 Signal Processing

SAA4981
Monolithic integrated 16 : 9 Compressor
FEATURES Fixed horizontal compression by a factor of 4 3 for most video standards Three fixed screen positions (left, centre and right) 5 MHz bandwidth Bypass function Inputs for luminance and chrominance of side panels Standard video inputs and outputs (Y, (-Y) and (-Y)) Horizontal and vertical sync signals are not processed Pre filters and post filters on chip. GENERAL DESCRIPTION The integrated 16 : 9 compressor is an IC which compresses the active part of a video line by a factor of 4 3 from, for example, 52 ms to 39ms. This is necessary to display 4:3 video software on a 16 : 9 tube in the correctproportion. The capacitively coupled video inputs are Y, ( -Y) and (-Y). The synchronisation input HREF is a line frequencyreference signal. The bandwidth of the IC is up to 5 MHz and the signal delay is realized with SC Line Memories (Switched Capacitors Line Memories). The output of the 16 : 9 compressor also has the format Y, ( Y) and (-Y) and provides the following two possibilities: 1. Bypass function (the input signal is not compressed) 2. Compressed video by a factor of 4 3 with three different fixed screen positions (left, centre and right). The luminance and chrominance of the side panels are determined by the external signals YSIDE, BYSIDE and RYSIDE. The horizontal compression is a time discrete and amplitude continuous signal processing. This provides pre and post filters which are realized on-chip. FUNCTIONAL DESCRIPTION SAA4981 16:9 TO 4:3 PROCESSOR Pagina 1 di 3 e.g.SAA4981R.doc

VCCA

VEEA

VCCD

VEED

SUB

20

19

23 YIN

SC LINE MEMORY CLAMP 5 MHz LOW-PASS FILTER SC LINE MEMORY

MUX SC LINE MEMORIES

6.7 MHz LOW-PASS FILTER

MUX Y

18

YOUT

SAA4981
C1 C2 C3

22 CLAMP

SC LINE MEMORY 5 MHz LOW-PASS FILTER SC LINE MEMORY

(B-Y)IN

MUX SC LINE MEMORIES

6.7 MHz LOW-PASS FILTER

MUX BY

17

(B-Y)OUT

C1

C2

C3

21 CLAMP

SC LINE MEMORY 5 MHz LOW-PASS FILTER SC LINE MEMORY

(R-Y)IN

MUX SC LINE MEMORIES

6.7 MHz LOW-PASS FILTER MUX RY

16

(R-Y)OUT

HREF

3 HORIZONTAL SEPARATION C1 CONTROLLER 54 MHz PLL C2 C3 CLAMP REFERENCE 3

C1

C2

C3

12 TEST

10 CTRL2

11

24

15

14

13

MHA277

CTRL1

CTRL3

pagewidth

YSIDE CLMY CLMBY CLMRY CLAOUT BGREF

BYSIDE RYSIDE

Applicable video standards The integrated 16 : 9 compressor can be used for the following video standards; B, C, D, G, H, I, K, K1, L, M and N. standards D, I, K, K1 and L will show a reducedvideo bandwidth above 5 MHz. Clamping circuit The clamping circuits clamp the video input signals Y, (-Y) and (-Y) to the DC level of the clamp reference signal fed from the clamp reference circuit. This is necessary to ensure that the input signals are in the correct input voltage range for the 5 MHz low-pass filters and the SC line memories. Internal pre filters Before the signals are sampled in the time discrete and amplitude continuous area, lowpass filtering is necessary to avoid any aliasing. Even if the inputs have already been lowpass filtered further filtering is advantageous for the electromagnetic compatibility (EMC). The same transfer function is used for all three low-pass filters because of the same bandwidth for the luminance and chrominance signals (up to 5 MHz) SC line memories After the low-pass filters the input signals are fed to the SC line memories. The signals are sampled at a clock frequency of 13.5 MHz. One video line later the signals are read with a clock frequency of 18 MHz in the compression mode. The result of the different clock frequencies is a horizontal compression by a factor of 4 3 . The clocks and the horizontal starting pulses for the SC line memories are fed from the controller. Two line memories are required for each signal path because in the compression mode, in one video line the signals are sampled to the SC line memories with 13.5 MHz and one video line later the signals are read with 18 MHz. In the bypass mode, via the SC line memories, in one video line the signals are sampled with 13.5 MHz and one video line later the signals are read with 13.5 MHz. The SC line memories are suitable for signals with a bandwidth up to 5 MHz. With a multiplexer (MUX) behind the SC line memories, the sampled video signal is connected to the internal post filters. Output multiplexer MUX Y, MUX (-Y) and MUX (-Y) SAA4981 16:9 TO 4:3 PROCESSOR Pagina 2 di 3 e.g.SAA4981R.doc

The output multiplexers are controlled via C1 and C2 fed from the controller. The multiplexers are used to connect one of the four input signals to the output and, also, enable fast switching. The input signals of the multiplexers for one component The output signal of the post filter The uncompressed signal after the input clamping The clamping reference signal The signal for the side panel determined by YSIDE, BYSIDE and RYSIDE. The horizontal separation circuit The 54 MHz horizontal PLL is locked to the positive edge of the digital HREF signal, which is generated in the positive edge of the burst key of a sandcastle signal. 54 MHz horizontal PLL The 13.5 MHz clock frequency for the sampling clock and the 18 MHz clock frequency for the reading clock are generated in the 54 MHz horizontal PLL. The 13.5 MHzclock and the 18 MHz clock are line locked. Clamp reference Reference voltages are generated In the clamp reference block. These DC signals are used in the clamping circuits as input signals for the output multiplexers and as reference voltages for the SC line memories. Four external capacitors at the pins CLMY , CLMBY , CLMRY and BGREF respectively are necessary to provide smoothing for the reference voltages. A black level reference signal is available at CLAOUT. Controller The controller generates the clocks and the horizontal start signals for the SC line memories and, also, the control signals for the output multiplexers. The timing for the start reading signal for three different screen positions (left, centre and right) and the control signals for the multiplexers (C1 and C2) is fixed. For the uncompressed signals a bypass via the SC line memories and a bypass not via the SC line memories is available. When the signals do not pass the line memories, the frequencyresponse is not affected by the sifunction. SAA4981 16:9 TO 4:3 PROCESSOR Pagina 3 di 3 e.g.SAA4981R.doc

HREF 64 s

1.5 s 1.5 s

(2) (2) (1)

sampled video 49 s (used for compression) 6.3 s 52 s 36.75 s side panel compressed video (centre position) side panel

side panel

compressed video (right position)

compressed video (left position)

side panel

bypassed video (bypass via the Line Memories)

(2) (2)

bypassed video

(1)

(full bypass not through the Line Memories)

MHA278

TDA4566
Colour transient improvement circuit

GENERAL DESCRIPTION The TDA4566 is a monolithic integrated circuit for colour-transient improvement (CTI) and luminance delay line in gyrator technique in colour television receivers. Features Colour transient improvement for colour difference signals (R-Y) and (B-Y) with transient detecting-, storage- and switching stages resulting in high transients of colour difference output signals A luminance signal path (Y) which substitutes the conventional Y-delay coil with an integrated Y-delay line Switchable delay time from 550 ns to 820 ns in steps of 90 ns and additional fine adjustment of 37 ns Two Y output signals; one of 180 ns less delay

TDA4566 CTI e.g.TDA4566R.doc

Pagina 1 di 1

F19 CTI & 16:9 TO 4 : 3 COMPRESSOR

6 9
15

10 12 V IC2 TDA4566
THESHOLD SWT.

5V
13 14 10 12
t = 180 ns

IC 1
23 CLAMP 11 Y R-Y 22 CLAMP

SAA4981
20 8 MUX LINE MEMORY LINE MEMORY LPF MUX LINE MEMORY LPF MUX LPF MUX 18 Y OUT LINE MEMORY LPF

7 4 3

8 1

Y R-Y

17 1

CLAMP

GYRATOR DELAY CELLS 7 x 90 ns

17

dV/dt
INTEGRATOR & PULSE FORMER

SWT. & STORE

R-Y OUT

dV/dt

SWT. & STORE

B-Y

21

CLAMP

LINE MEMORY LPF MUX LINE MEMORY LPF MUX

16 13

B-Y OUT

B-Y 2 3 4 5 6 9 18 6 HOR. SEPAR. 7 JS 7 JS 6 JS 5 20 54 MHz PLL 4 12 CONTROLLER CLAMP REFERENCE 19 1 2 3 24 5

14 15

11 10

H REF

5V TR1

5 8V
R4

C10 16 14 13 15 8 16 1 3 5 DUAL MONOSTABLE MULTIVIBRATOR M.M. M.M. 10 2

T2

16:9 TO 4:3 SWITCH SIGNAL

12

EF
C9

IC 4 HEF 4538 8V

D1

note: If CTI ( IC 2 TDA4566 IS NOT PRESENT THAN JS 5, JS 6 & JS7 MUST BE INSERTED

11

S.C INPUT

R2

12 V

F19FEAT.DRW E.G. 12/12/99

SCANNING SECTION SECTION

TDA8351
DC-coupled vertical deflection Circuit
FEATURES Few external components Highly efficient fully DC-coupled vertical output bridge circuit Vertical flyback switch Guard circuit Protection against: GENERAL DESCRIPTION The TDA8351 is a power circuit for use in 9 and 11 colour deflection systems for short-circuit of the output pins (7 and 4) short-circuit of the output pins to VP Temperature (thermal) protection High EMC immunity because of common mode inputs A guard signal in zoom mode.

field frequencies of 50 to 120 Hz. The circuit provides a DC driven vertical deflection output circuit, operating as a highly efficient class G system. FUNCTIONAL DESCRIPTION The vertical driver circuit is a bridge configuration. The deflection coil is connected between the output amplifiers, which are driven in phase opposition. An external resistor (RM ) connected in series with the deflection coil provides internal feedback information. The differential input circuit is voltage driven. The input circuit has been adapted to enable it to be used with the TDA9150, TDA9151B, TDA9160A, TDA9162, TDA8366 and TDA8376 which deliver symmetrical current signals. An external resistor (RCON ) connected between the differential input determines the output current through the deflection coil. TDA8351 VERTICAL OUTPUT Pagina 1 di 2 e.g. TDA8351R

The relationship between the differential input current and the output current is defined by: Idiff RCON =Icoil RM . The output current is adjustable from 0.5 A (p-p) to 3 A(p-p) by varying RM . The maximum input differential voltage is 1.8 V. In the application it is recommended that Vdiff = 1.5 V (typ). This is recommended because of the spread of input current and the spread in the value of RCON . The flyback voltage is determined by an additional supply voltage VFB . The principle of operating with two supply voltages (class G) makes it possible to fix the supply voltage VP optimum for the scan voltage and the second supply voltage VFB optimum for the flyback voltage. Using this method, very high efficiency is achieved. The supply voltage VFB is almost totally available as flyback voltage across the coil, this being possible due to the absence of a decoupling capacitor (not necessary, due to the bridge configuration). The output circuit is fully protected against the following: thermal protection short-circuit protection of the output pins (pins 4 and 7) short-circuit of the output pins to VP .

A guard circuit VO(guard) is provided. The guard circuit is activated at the following conditions: during flyback during short-circuit of the coil and during short-circuit of the output pins (pins 4 and 7) to VP or ground during open loop when the thermal protection is activated. This signal can be used for blanking the picture tubescreen.

TDA8351 VERTICAL OUTPUT

Pagina 2 di 2

e.g. TDA8351R

dth

VP VO(guard)

VFB 6

3 VP

CURRENT SOURCE

TDA8351

VP 7 VO(A) IS IT IT 9 VP V I(fb) VO(A)

I drive(pos)

I drive(neg)

2 V IS

4 VO(B)

VO(B)

5 GND
MBC988- 1

PINNING SYMBOL Idrive(pos) Idrive(neg) VP VO(B) GND VFB VO(A) VO(guard) VI(fb) PIN 1 2 3 4 5 6 7 8 9 DESCRIPTION input power-stage (positive); includes II(sb) signal bias input power-stage (negative); includes II(sb) signal bias operating supply voltage output voltage B ground input yback supply voltage output voltage A guard output voltage input feedback voltage

handbook, 2 columns

I drive(pos)

1 2

I drive(neg) VP VO(B) GND V FB VO(A) VO(guard) V I(fb)

3 4 5 6 7 8 9
MBC989

TDA8351

HEATER VOLTAGE

11 12 1

T3
EHT

IC 204 TDA8844
47
20 mS

28 V

146 V

FOCUS 4

46

45

40
VIDEO SUPPLAY LINE

200 V
D 53

9 VG2

1 2 2
64 /uS

TDA8351

3 4 5 6

T2 EF

TR18 BU508D 3 10 C154 B.C.L. PIN22 TDA8844 PIN 50 50 V 7 8 EHT P. SERVICE FLYBACK PULSE TO: PIP TUNING OSD SYNC

TR207 TR15 D24

L22

LINEARITY

IC 5

7 8 9

PIN6 TDA8351 YOKE L26 16 V C51 L25 6 PIN 3 TDA8351 R35 C52 5 5

TR12

L20

C71

BUK474 D25

VERTICAL YOKE

F19 VERTICAL & LINE OUTPUT PLUS E-W CORRECTION

F19 V&HDF.DRW E.G. 27/12/99

SCART 1 1 EF TR202 TR201 EF TR210

6 55 10 2 EXT. IN 2 1 8V R239 F575 15 SCART OUT CVBS & INTERCARRIER OUT

6 TR110

TR525

FROM PIN8 IC 100 SCART/CINCH SWITCH

IC 204
14

12 13 11

AUDIO CINCH IN

TDA844X
SOUND IF IN R208 F576 9 15 8 1

IC 400 TDA2613
7 6 5 4 3 2 1

IC200 (2/3) HEF 4053

R242

FROM PIN 12 IC100 SAA5297A

AUDIO OUT

28 V TR575

TR209

F19 AUDIO MONO SIGNAL PATH

F19AMSPH.DRW E.G. 29/12799

TDA 9870A & TDA9875A MAIN CHARACTERISTICS

FEATURES
Demodulator and decoder section Sound IF (SIF) input switch e.g. to select between terrestrial TV SIF and SAT SIF sources SIF AGC with 24 dB control range (ADC) DQPSK demodulation for different standards, simultaneously with 1-channel FM demodulation NICAM decoding (B/G, I and L standard) Two-carrier SIF 8-bit Analog-to-Digital Converter

multistandard FM demodulation (B/G, D/K and M standard Decoding for three analog multi-channel systems (A2, A2+ and A2*) and satellite sound Optional AM demodulation for system L, simultaneously with NICAM Programmable identification (B/G, D/K and M standard) and different identification times. DSP section Digital crossbar switch for all digital signal sources and destinations Control of volume, balance, contour, bass, treble, pseudo stereo, spatial, bass boost and soft-mute Plop-free volume control Automatic Volume Level (AVL) control Adaptive de-emphasis for satellite Programmable beeper Monitor selection for FM/AM DC values and signals, with peak detection option I 2 S-bus

interface for a feature extension (e.g. Dolby surround) with matrix, level adjust and mute. Analog audio section Analog crossbar switch with inputs for mono and stereo 23 / 30 F19MANU.doc

E.G.Data creazione 01/11/99 17.27

(also applicable as SCART 3 input), SCART 1 input/output, SCART 2 input/output and line output User defined full-level/ 3 dB scaling for SCART outputs Output selection of mono, stereo, dual A/B, dual A or Dual B 20 kHz bandwidth for SCART-to-SCART copies Standby mode with functionality for SCART copies Dual audio digital-to-analog converter from DSP to analog crossbar switch, bandwidth 15 kHz Dual audio ADC from analog inputs to DSP Two dual audio Digital-to-

Analog Converters (DACs) for loudspeaker (Main) and headphone (Auxiliary) outputs; also applicable for L, R, C and S in the Dolby Pro Logic mode with feature extension.

GENERAL DESCRIPTION The TDA9875A is a single-chip Digital TV Sound Processor (DTVSP) for analog and digital multi-channel sound systems in TV sets and satellite receivers. Supported standards The multistandard/multi-stereo capability of the TDA9875A is mainly of interest in Europe, but also in Hong Kong/Peoples Republic of China and South East Asia. This includes B/G, D/K, I, M and L standard. In other application areas there exists only subsets of those standard combinations otherwise only single standards are transmitted. M standard is transmitted in Europe by the American Forces Network (AFN) with European channel spacing (7 MHz VHF, 8 MHz UHF) and monaural sound. The AM sound of L/L standard is normally demodulated in the 1st sound IF. The resulting AF signal has to be entered into the mono audio input of the TDA9875A. A second possibility is to use the internal AM demodulator stage, however this gives limited performance. Korea has a stereo sound system similar to Europe and is supported by the TDA9875A. Differences include deviation, modulation contents and identification. It is based on M standard. FUNCTIONAL DESCRIPTION

Description of the demodulator and decoder section SIF INPUT E.G.Data creazione 01/11/99 17.27 24 / 30 F19MANU.doc

Two input pins are provided, SIF1 e.g. for terrestrial TV and SIF2 e.g. for a satellite tuner. For higher SIF signal levels the SIF input can be attenuated with an internal switchable 10 dB resistor divider. As no specific filters are integrated, both inputs have the same specification giving flexibility in application. The selected signal is passed through an AGC circuit and then digitized by an 8-bit ADC operating at 24.576 MHz. AGC The gain of the AGC amplifier is controlled from the ADC output by means of a digital control loop employing hysteresis. The AGC has a fast attack behaviour to prevent ADC overloads and a slow decay behaviour to prevent AGC oscillations. For AM demodulation the AGC must be switched off. When switched off, the control loop is reset and fixed gain settings can be chosen from Table 15 (subaddress 0). MIXER The digitized input signal is fed to the mixers, which mix one or both input sound carriers down to zero IF. A 24-bit control word for each carrier sets the required frequency. Access to the mixer control word registers is via the I 2 C-bus. When receiving NICAM programs, a feedback signal is added to the control word of the second carrier mixer to establish a carrier-frequency loop. FM AND AM DEMODULATION An FM or AM input signal is fed via a band-limiting filter to a demodulator that can be used for either FM or AM demodulation. Apart from the standard (fixed) de-emphasis characteristic, an adaptive de-emphasis is available for encoded satellite programs. A stereo decoder recovers the left and right signal channels from the demodulated sound carriers. Both the European and Korean stereo systems are supported. FM IDENTIFICATION The identification of the FM sound mode is performed by AM synchronous demodulation of the pilot signal and narrow-band detection of the identification frequencies. The result is available via the I 2 C-bus interface. A selection can be made via the I 2 C-bus for B/G, D/K and M standard and for three different modes that represent different trade-offs between speed and reliability of identification. NICAM DEMODULATION The NICAM signal is transmitted in a DQPSK code at a bit rate of 728 kbit/s. The NICAM demodulator performs DQPSK demodulation and feeds the resulting bitstream and clock signal onto the NICAM decoder and, for evaluation purposes, to PCLK (pin 1) and NICAM E.G.Data creazione 01/11/99 17.27 25 / 30 F19MANU.doc

(pin 2). A timing loop controls the frequency of the crystal oscillator to lock the sampling rate to the symbol timing of the NICAM data. NICAM DECODER The device performs all decoding functions in accordance with the EBU NICAM 728 specification. After locking to the frame alignment word, the data is descrambled by applying the defined pseudo-random binary sequence; the device will then synchronize to the periodic frame flag bit C0. The status of the NICAM decoder can be read out from the NICAM status register by the user. The OSB bit indicates that the decoder has locked to the NICAM data. The VDSP bit indicates that the decoder has locked to the NICAM data and that the data is valid sound data. The C4 bit indicates that the sound conveyed by the FM mono channel is identical to the sound conveyed by the NICAM channel. The error byte contains the number of sound sample errors, resulting from parity checking, that occurred in the past 128 ms period. NICAM AUTO-MUTE This function is enabled by setting bit AMUTE LOW subaddress 14 Upper and lower error limits may be defined by writing appropriate values to two registers in the I 2 C-bus section (subaddresses 16 and 17; . When the number of errors in a 128 ms period exceeds the upper error limit the auto-mute function will switch the output sound from NICAM to whatever sound is on the first sound carrier (FM or AM). When the error count is smaller than the lower error limit the NICAM sound is restored. The auto-mute function can be disabled by setting bit AMUTE HIGH. In this condition clicks become audible when the error count increases; the user will hear a signal of degrading quality. A decision to enable/disable the auto-muting is taken by the microcontroller based on an interpretation of the application control bits C1, C2, C3 and C4 and, possibly, any additional strategy implemented by the set maker in the microcontroller software. For NICAM L applications, it is recommended to demodulate AM sound in the first sound IF and connect the audio signal to the mono input of the TDA9875A. By setting the AMSEL bit subaddress 14. the auto-mute function will switch to the audio ADC instead of switching to the first sound carrier. CRYSTAL OSCILLATOR The digital-controlled crystal oscillator (DCXO) is illustrated in Fig.8 (see Chapter 12). The circuitry of the DCXO is fully integrated, only the external 24.576 MHz crystal is needed. E.G.Data creazione 01/11/99 17.27 26 / 30 F19MANU.doc

TEST PINS Both test pins are active HIGH, in normal operation of the device they are wired to VSSD1 Test functions are for manufacturing tests only and are not available to customers. Without external circuitry these pads are pulled down to LOW level with internal resistors. POWER FAIL DETECTOR The power fail detector monitors the internal power supply for the digital part of the device. If the supply has temporary been lower than the specified lower limit, the power-on reset bit POR, transmitter register subaddress 0 will be set to HIGH. The CLRPOR bit, slave register subaddress 1 resets the power-on reset flip-flop to LOW. If this is detected, an initialization of the TDA9875A has to be carried out to ensure reliable operation. LEVEL SCALING All input channels to the digital crossbar switch (except for the loudspeaker feedback path) are equipped with a level adjust facility to change the signal level in a range of 15 dB. It

is recommended to scale all input channels to be 15 dB below full scale ( 15 dB full scale) under nominal conditions. NICAM PATH The NICAM path has a switchable J17 de-emphasis. FM (AM) PATH A high-pass filter suppresses DC offsets from the FM demodulator due to carrier frequency offsets and supplies the monitor/peak function with DC values and an unfiltered signal, e.g. for the purpose of carrier detection. The de-emphasis function offers fixed settings for the supported standards (50 s, 60 s 75 s and J17). An adaptive de-emphasis is available for Wegener-Panda 1 encoded programs. A matrix performs the dematrixing of the A2 stereo, dual and mono signals. NICAM AUTO-MUTE If NICAM B/G, I, D/K is received, the auto-mute is enabled and the signal quality becomes poor, the digital crossbar switch switches automatically to FM and switches the matrix to channel 1. The automatic switching depends on the NICAM bit error rate. The auto-mute function can be disabled via the I 2 C-bus. For NICAM L applications, it is recommended to demodulate AM sound in the first sound IF and connect the audio signal to the mono input of the TDA9875A. By setting the AMSEL bit subaddress 14 (see Section 10.3.11), the auto-mute function will switch to the audio ADC instead of switching to the E.G.Data creazione 01/11/99 17.27 27 / 30 F19MANU.doc

first sound carrier. The ADC source selector subaddress 23 (see Section 10.3.20) should be set to mono input, where the AM sound signal should be connected. LOUDSPEAKER (MAIN) CHANNEL The matrix provides the following functions; forced mono, stereo, channel swap, channel 1, channel 2 and spatial effects. There are fixed coefficient sets for spatial settings of 30%, 40% and 52%. The Automatic Volume Level (AVL) function provides a constant output level of 23 dB full scale for input levels between 0 and 29 dB full scale. There are some fixed decay time constants to choose from, i.e. 2, 4 and 8 seconds. Pseudo stereo is based on a phase shift in one channel via a 2nd-order all-pass filter. There are fixed coefficient sets to provide 90 degrees phase shift at frequencies of 150, 200 and 300 Hz. Volume is controlled individually for each channel ranging from +24 to -83 dB with 1 dB resolution. There is also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for volume control is identical to the volume setting in dBs (e.g. the I 2 C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Contour is adjustable between 0 and +18 dB with 1 dB resolution. This function is linked to the volume setting by means of microcontroller software. Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable between +/-12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for contour, bass or treble is identical to the new contour, bass or treble setting in dBs (e.g. the I 2 C-bus data byte +8 sets the new value to +8 dB). Extra bass boost is provided up to 20 dB with 2 dB resolution. The implemented coefficient set serves merely as an example on how to use this filter. The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I 2 C-bus. The beeper output signal is added to theloudspeaker and headphone channel signals. The beeper volume is adjustable with E.G.Data creazione 01/11/99 17.27 28 / 30 F19MANU.doc

respect to full scale between 0 and effected by mute.

93 dB with 3 dB resolution. The beeper is not

Soft-mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine masking. HEADPHONE (AUXILIARY) CHANNEL The matrix provides the following functions; forced mono, stereo, channel swap, channel and channel 2 (or C and S in Dolby Surround Pro Logic mode). Volume is controlled individually for each channel in a range from +24 to 83 dB with 1 dB resolution. There is

also a mute position. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for volume control is identical to the volume setting in dB (e.g. the I 2 C-bus data byte +10 sets the new volume value to +10 dB). Balance can be realized by independent control of the left and right channel volume settings. Bass is adjustable between +15 and -12 dB with 1 dB resolution and treble is adjustable between +/- 12 dB with 1 dB resolution. For the purpose of a simple control software in the microcontroller, the decimal number that is sent as an I 2 C-bus data byte for bass or treble is identical to the new bass or treble setting in dB (e.g. the I 2 C-bus data byte +8 sets the new value to +8 dB). The beeper provides tones in a range from approximately 400 Hz to 30 kHz. The frequency can be selected via the I 2 C-bus. The beeper output signal is added to the loudspeaker and headphone channel signals. The beeper volume is adjustable with respect to full scale between 0 and effected by mute. Soft-mute provides a mute ability in addition to volume control with a well defined time (32 ms) after which the soft-mute is completed. A smooth fading is achieved by a cosine masking. SCART INPUTS The SCART specification allows for a signal level of up to 2 V (rms). Because of signal handling limitations, due to the 5 V supply voltage of the TDA9875A, it is necessary to have fixed 3 dB attenuators at the SCART inputs to obtain a 2 V input. This results in a +3 dB SCART-to-SCART copy gain. If 0 dB copy gain is preferred (with maximum 1.4V input), there are +3 dB/0 dB amplifiers at the outputs of SCART 1 and SCART 2 and at the line E.G.Data creazione 01/11/99 17.27 29 / 30 F19MANU.doc 93 dB with 3 dB resolution. The beeper is not

output. The input attenuator is realized by an external series resistor in combination with the input impedance, both of which form a voltage divider. With this voltage divider the maximum SCART signal level of 2 V (rms) is scaled down to 1.4 V (rms) at the input pin. EXTERNAL AND MONO INPUTS The 3 dB input attenuators are not required for the external and mono inputs, because those signal levels are under control of the TV designer. The maximum allowed input level is 1.4 V (rms). By adding external series resistors, the external inputs can be used as an additional SCART input. SCART OUTPUTS The SCART outputs employ amplifiers with two gain settings. The gain can be set to +3 dB or to 0 dB via the I 2 C-bus. The +3 dB position is needed to compensate for the 3 dB attenuation at the SCART inputs should SCART-to-SCART copies with 0 dB gain be preferred [under the condition of 1.4 V (rms) maximum input level]. The 0 dB position is needed, for example, for an external-to-SCART copy with 0 dB gain. LINE OUTPUT The line output can provide an unprocessed copy of the audio signal in the loudspeaker channels. This can be either an external signal that comes from the dual audio ADC, or a signal from an internal digital audio source that comes from the dual audio DAC. The line output employs amplifiers with two gain settings. The +3 dB position is needed to compensate for the attenuation at the SCART inputs, while the 0 dB position is needed, for example, for non-attenuated external or internal digital signals (see Section 6.3.4).

E.G.Data creazione 01/11/99 17.27

30 / 30

F19MANU.doc

IIC BUS TO PIN 9 IC1 TDA9811

TR8 STD SWITCH

INTERCARRIER FROM PIN 20 IC1 TDA9811

EF

6V
TO L/L' FILTER SWITCH TR8 L /L' SWITCH

II S

AM AUDIO FROM PIN 22 IC1 TR6 TDA9811

EF

TDA9875A TDA9875A PINOUT & PERIPHERALS

1 PLCK 2 NICAM 3 ADDR1 4 SCL 5 SDA 6 VSSA1 7 VDEC1 8 Iref 9 P1 10 SIF2 11 Vref 12 SIF1 13 ADDR2 14 Vssd1 15 Vdd1 16 CRESET 17 Vssd4 18 XTAL1 19 XTAL0 20 P2 21 SYSLCK 22 SCK 23 WS 24 SDO2 25 SDO1 26 SDI2 27 SDI1 28 TEST1 29 MONOIN 30 TEST2 31 EXT/R 32 EXT/L

IIC
IN / OUT

INPUT SWITCH AGC ADC

IDENT

FM DEM (AM DEM)

QPSK DEM.

I/O PORT

DEMATR DEEMPH

NICAM DEC.

PEAK DETEC.

LEVEL ADJ.

LEVEL ADJ.

VCXO CLOCK CHANNEL SELECTION

DAC

DAC

IIS
AUDIO PROCESSING

L.S.
ENC. DEC. AVL,VOL CONTOUR BASS TREBLE PSEUDO BASS CORR

H.P.
VOL. BASS TREB.

DAC

DAC

TEST

VDD2 LOR LOL MOL MOR Vdda AUXOL AUXOR Vssa3 pcapl pcapr vREF3 SCOL2 SCOR2 Vssa4 Vssd2 SCOL1 SCOR2 Vref2 i.c. i.c. Vssa2 i.c. i.c. Vref(n) Vref(p) Vdec2 SCIL2 SCIR2 Vssd3 SCIL1 SCIR1

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

6V AUDIO LINE OUT TR9 TO AUDIO AMPLIFIER TR10

6V TR11 TR12

ANALOGUE CROSS BAR SWITCH

TO HEADPHONES APLIFIER IC4 TDA2822M

AUDIO OUT TO SCART

AUDIO FROM SCART

TDA9875A.DRW E.G. 7/11/99

TDA9811
Multistandard VIF-PLL with QSS-IF and AM demodulator
FEATURES 5 V supply voltage Two switched VIF inputs, gain controlled wide band VIF-amplifier (AC-coupled) True synchronous demodulation with active carrier regeneration (very linear

demodulation, good intermodulation figures, reduced harmonics, excellent pulse response) Gated phase detector for L/L accent standard VCO frequency switchable between L and L accent (alignment external) picture carrier frequency Separate video amplifier for sound trap buffering with high video bandwidth VIF AGC detector for gain control, operating as peak sync detector for B/G (optional external AGC) and peak white detector for L; signal controlled reaction time for L Tuner AGC with adjustable takeover point (TOP) AFC detector without extra reference circuit SIF input for single reference QSS mode (PLL controlled); SIF AGC detector for gain controlled SIF amplifier; single reference QSS mixer able to operate in high performance single reference QSS mode AM demodulator without extra reference circuit AM mute (especially for NICAM) Stabilizer circuit for ripple rejection and to achieve constant output signals.

GENERAL DESCRIPTION

The TDA9811 is an integrated circuit for multistandard vision IF signal processing and sound AM demodulation, with single reference QSS-IF in TV and VCR sets.

TDA9811 QSS

Pagina 1 di 4

e.g. TDA9811R

th

CAGC VIF input switch

TOP C BL

2 x f PC tuner AGC loop filter AFC

30

28

19

25

24

23 AFC DETECTOR 21 video 1 V (p-p)

TUNER AND VIF-AGC

VCO TWD

5 VIFB 4 2 VIFA 1 32 SIF 31 SIF AMPLIFIER SINGLE REFERENCE MIXER AND AM DEMODULATOR FPLL VIF AMPLIFIER AND INPUT SWITCH VIDEO DEMODULATOR AND AMPLIFIER VIDEO BUFFER 10 22 CVBS 2 V (p-p) Vi(vid)

TDA9811

AF AMPLIFIER AND SWITCH

12

AF/AM

INTERNAL VOLTAGE STABILIZER 29 27 26 1/2 VP 9

13 SIF-AGC 14 8 20 11 18 n.c. 16 n.c. 15 n.c. mute switch, AM 17

n.c. n.c.

C AGC 5V standard switch (2nd SIF) Vo QSS

L/L switch

MHA046

FUNCTIONAL DESCRIPTION

Vision IF amplifier and input switch The vision IF amplifier consists of three AC-coupled differential amplifier stages. Each differential stage comprises a feedback network controlled by emitterdegeneration. T The first differential stage is extended by two pairs of emitter followers to provide two IF input channels. The VIF input can be selected by pin 30 Tuner and VIF AGC The AGC capacitor voltage is transferred to an internal IF control signal, and is fed to the tuner AGC to generate the tuner AGC output current (open-collector output). The tuner AGC takeover point can be adjusted. This allows the tuner and the SWIF filter to be matched to achieve the optimum IF input level. The AGC detector charges/discharges the AGC capacitorto the required voltage for setting of VIF and tuner gain in order to keep the video signal at a constant level. Therefore for negative video modulation the sync level and for positive video modulation the peak white level of the video signal is detected. In order to reduce the reaction time for positive modulation, where a very large time constant is needed, an additional level detector increases the discharging current of the AGC capacitor (fast mode) in the event of a decreasing VIF amplitude step. The additional level information is given by the black-level detector voltage. Frequency Phase Locked Loop detector (FPLL) The VIF-amplifier output signal is fed into a frequency detector and into a phase detector via a limiting amplifier. During acquisition the frequency detector produces a DC current proportional to the frequency difference between the input and the VCO signal. After frequency lock-in the phase detector produces a DC current proportional to the phase difference between the VCO and the input signal. The DC current of either frequency detector or phase detector is converted into a DC voltage via the loop filter, which controls the VCO frequency. In the event of positive modulated signals the phase detector is gated by composite sync in order to avoid signal distortion for overmodulated VIF signals.

TDA9811 QSS

Pagina 2 di 4

e.g. TDA9811R

VCO, Travelling Wave Divider (TWD) and AFC The VCO operates with a resonance circuit (with L and C in parallel) at double the PC frequency. The VCO is controlled by two integrated variable capacitors. The control voltage required to tune the VCO from its free-running frequency to actually double the PC frequency is generated by the frequency-phase detector and fed via the loop filter to the first variable capacitor (FPLL). This control voltage is amplified and additionally converted into a current which represents the AFC output signal. The VCO centre frequency can be decreased (required for L accent standard) by activating an additional internal capacitor. This is achieved by using the L accent switch. In this event the second variable capacitor can be controlled by a variable resistor at the L accent switch for setting the VCO centre frequency to the required L accent value. At centre frequency the AFC output current is equal to zero. The oscillator signal is divided-by-two with a TWD which generates two differential output signals with a 90 degree phase difference independent of the frequency. Video demodulator and amplifier The video demodulator is realized by a multiplier which is designed for low distortion and large bandwidth. The vision IF input signal is multiplied with the in phase signal of the travelling wave divider output. In the demodulator stage the video signal polarity can be switched in accordancewith the TV standard. The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the video amplifier. The video amplifier is realized by an operational amplifier with internal feedback and high bandwidth. A low-pass filter is integrated to achieve an attenuation of the carrier harmonics for B/G and L standard. The standard dependent level shift in this stage delivers the same sync level for positive and negative modulation. The video output signal is 1 V (p-p) for nominal vision IF modulation. Video buffer For an easy adaption of the sound traps an operational amplifier with internal feedback is used in the event of B/G and L standard. This amplifier is featured with a high bandwidth and 7 dB gain. The input impedance is adapted output stage delivers a nominal 2 V (p-p) positive video signal. Noise clipping is provided.

TDA9811 QSS

Pagina 3 di 4

e.g. TDA9811R

SIF amplifier and AGC The sound IF amplifier consists of two AC-coupled differential amplifier stages. Each differential stage comprises a controlled feedback network provided by emitter degeneration. The SIF AGC detector is related to the SIF input signals (average level of AM or FM carriers) and controls the SIF amplifier to provide a constant SIF signal to the AM demodulator and single reference QSS mixer. The SIF AGC reaction time is set to slow for nominal video conditions. But with a decreasing VIF amplitude step the SIF AGC is set to fast mode controlled by the VIF AGC detector. In FM mode this reaction time is also set to fast controlled by the standard switch. Single reference QSS mixer The single reference QSS mixer is realized by a multiplier. The SIF amplifier output signal is fed to the single reference QSS mixer and converted to intercarrier frequency by the regenerated picture carrier (VCO). The mixer output signal is fed via a high-pass for attenuation of the video signal components to the output pin 20. With this system a high performance hi-fi stereo sound processing can be achieved. AM demodulator The AM demodulator is realized by a multiplier. The modulated SIF amplifier output signal is multiplied in phase with the limited (AM is removed) SIF amplifier output signal. The demodulator output signal is fed via an integrated low-pass filter for attenuation of the carrier harmonics to the AF amplifier. Internal voltage stabilizer and 1 2 VP -reference The bandgap circuit internally generates a voltage of approximately 1.25 V, independent of supply voltage and temperature. A voltage regulator circuit, connected to this voltage, produces a constant voltage of 3.6 V which is used as an internal reference voltage. For all audio output signals the constant reference voltage cannot be used because large output signals are required.

TDA9811 QSS

Pagina 4 di 4

e.g. TDA9811R

PINNING SYMBOL Vi VIF1 Vi VIF2 CBL Vi VIF3 Vi VIF4 TADJ TPLL CSAGC STD Vo CVBS LSWI Vo AF n.c. n.c. n.c. n.c. MUTE n.c. TAGC Vo QSS Vo(vid) Vi(vid) AFC VCO1 VCO2 Cref GND CVAGC VP INSWI Vi SIF1 Vi SIF2 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DESCRIPTION VIF differential input signal voltage 1 VIF differential input signal voltage 2 black level detector
andbook, halfpage

VIF differential input signal voltage 3 VIF differential input signal voltage 4 tuner AGC takeover adjust (TOP) PLL loop lter SIF AGC capacitor standard switch CVBS output signal voltage L/L accent switch AM audio voltage frequency output not connected not connected not connected not connected AM mute not connected tuner AGC output single reference QSS output voltage composite video output voltage video buffer input voltage AFC output VCO1 reference circuit for 2fPC VCO2 reference circuit for 2fPC
1 2VP

Vi VIF1 Vi VIF2 C BL Vi VIF3 Vi VIF4 TADJ TPLL CSAGC STD

1 2 3 4 5 6 7 8

32 V i SIF2 31 V i SIF1 30 INSWI 29 VP 28 C VAGC 27 GND 26 Cref 25 VCO2

TDA9811
9 24 VCO1 23 AFC 22 Vi(vid) 21 Vo(vid) 20 Vo QSS 19 TAGC 18 n.c. 17 MUTE
MHA047

Vo CVBS 10 LSWI 11 Vo AF 12 n.c. 13 n.c. 14 n.c. 15 n.c. 16

reference capacitor

ground VIF AGC capacitor supply voltage VIF input switch SIF differential input signal voltage 1 SIF differential input signal voltage 2 Fig.2 Pin configuration.

TDA9830
TV sound AM-demodulator and audio source switch

FEATURES Adjustment free wideband synchronous AM demodulator Audio source-mute switch (low noise) Audio level according EN50049 5 to 8 V power supply or 12 V alternative Low power consumption. GENERAL DESCRIPTION The TDA9830, a monolithic integrated circuit, is designed for AM-sound demodulation used in L- and L-standard. The IC provides an audio source selector and also mute switch. FUNCTIONAL DESCRIPTION Sound IF input The sound IF amplifier consists of three AC-coupled differential amplifier stages each with approximately 20 dB gain. At the output of each stage is a multiplier for gain controlling ( current distribution gain control). The overall control range is approximately -6 to +60 dB and the frequency response (-3 dB) of the IF amplifier is approximately 6 to 70 MHz. The steepness of gain control is approximately 10 mV/dB. IF AGC The automatic gain control voltage to maintain the AM demodulator output signal at a constant level is generated by a mean level detector. This AGC-detector charges and discharges the capacitor at pin 3 controlled by the output signal of the AM-demodulator compared to an internal reference voltage. The maximum charge/discharge current is approximately 5 mA. This value in combination with the value of the AGC capacitor and the AGC steepness determines the lower cut-off audio frequency and the THD-figure at low modulation frequency of the whole AM-demodulator. Therefore a large time constant has to be chosen which leads to slow AGC reaction at IF level change. To speed up the AGC in case of IF signal jump from low to high level, there is an additional comparator built in, which can provide additional discharge current from the AGC capacitor up to 5 mA in a case of overloading the AM demodulator by the internal IF signal. AM-demodulator The IF amplifier output signal is fed to a limiting amplifier (two stages) and to a multiplier circuit. However the limiter output signal (which is not any more AM modulated) is also fed to the multiplier, which provides AM demodulation (in phase demodulation). After lowpass filtering (fg 400 kHz) for carrier rejection and buffering, the demodulator output signal is present at pin 6. The AM demodulator operates over a wide frequency range, so that in

combination with the frequency response of the IF amplifier applications in a frequency range from approximately 6 MHz up to 70 MHz are possible. Audio switch This circuit is an operational amplifier with three input stages and internal feedback network determining gain (0 dB) and frequency response (fg 700 kHz). Two of the input stages are connected to pin 7 and pin 9, the third input stage to an internal reference voltage. Controlled by the switching pins 10 and 12, one of the three input stages can be activated and a choice made between two different AF signals or mute state. The selected signal is present at pin 8. The decoupling capacitors at the input pins are needed, because the internally generated bias voltage for the input stages must not be influenced by the application in order to avoid DC-plop in case of switching. The AM demodulator output is designed to provide almost the same DC voltage as the input bias voltage of the audio switch. But there may be spread between both voltages. Therefore it is possible to connect pin 6 directly to pin 7 (without a decoupling capacitor), but in this event the DC-plop for switching can increase up to 100 mV. Reference circuit This circuit is a band gap stabilizer in combination with a voltage regulation amplifier, which provides an internal reference voltage of about 3.6 V nearly independent from supply voltage and temperature. This reference voltage is filtered by the capacitor at pin 4 in order to reduce noise. It is used as a reference to generate all important voltages and currents of the circuit. For application in 12 V power supply concepts, there is an internal voltage divider in combination with a Darlington transistor in order to reduce the supply voltage for all IC function blocks to approximately 6 V. This is necessary because of use of modern high frequency IC technology, where most of the used integrated components are only allowed to operate at maximum 9 V supply voltage.

12

11

MONO INPUT 10 9 5

EXT. IN 2 1

SCART OUT 4 3

LINE OUT

A1
6V

A3
6V
SCART SOUND OUT

A2
1

INTERCARRIER INPUT

29

31

32

33

34

35 36 37

IIC
38 39 47 48 49 50 51 52 62 63 59 64 2 3 4 VDDA3 VDDD2 VSSD2 49 VSSA2 43 VSSA3 56 VSSA4 50

ANALOGUE CROSS BAR SWITCH

10

INPUT SWITCH AGC ADC

TDA9870A
FM DEM (AM DEM) DEMATR DEEMPH LEVEL ADJ.

DAC

DAC

12

AUDIO PROCESSING L.S .

AVL, VOL CONTOUR, BASS TREB, PSEU BASSCORR BEEPER

28
TEST

26V
TR10

7 10 8

30
60

CHANNEL SELECTION IIS

DAC 9 61 TR9

SCL 4

IIC
SDA

IIC
8

IDENT

I/O PORT 20 9

PEAK DETECT.
2 IIC ADDRESS

VCXO CLOCK 18

IIS
ENC / DEC.

57

TR12

H.P.
VOL, BEEP. BASS, TREB.

DAC 58 TR11

3 IIC ADDRES. 6 VSSA1 7

17

14

11

13 15 16

19 22 23 24 25 26 27 21

IIS

F19 STEREO A2 MODULE

6V

7 6 HEADPHONES IC 4 AMPLIFIER TDA2822M

1 3

5 6

2 KIA7812
1 2 3 12 V

IC 5
F19STA2 .DRV E.G 5/11/99

7 IF IN

12

11

10

9
EXT. IN

A1

A3
6V

TR6

6V

12V

EF
STEREO INTERCARRIER ONLY

SCART SOUND OUT

A2
1

29

31

32

33

34

35 36 37

IIC
38 39 47 48 49 50 51 52 62 63 59 64 2 3 4 VDDA3 VDDD2 VSSD2 49 VSSA2 43 VSSA3 56 VSSA4 50 28 TEST 30 60 DAC 9 61 57 TR12 TR9 TR10

TDA9875A
10 TR1 INPUT SWITCH AGC ADC FM DEM (AM DEM)

ANALOGUE CROSS BAR SWITCH AUDIO PROCESSING L.S .

AVL, VOL CONTOUR, BASS TREB, PSEU BASSCORR BEEPER

QPSK DEM.

NICAM DEC.

LEVEL ADJ.

DAC

DAC

26V

7 10 8

EF

12 1
PLK

DEMATR DEEMPH

LEVEL ADJ.

CHANNEL SELECTION IIS

2 NICAM
DATA

SCL 4 IIC SDA 3 6

IIC ADDR.

IIC
7 8

IDENT

I/O PORT 9

PEAK DETECT.
2 IIC ADDRESS

VCXO CLOCK 18 21 19

IIS
ENC / DEC. 22 23 24 25 26 27 IIS

H.P.
VOL, BEEP. BASS, TREB.

DAC 58 TR11

17

14 20

11

13 15 16

TR7 TR8 TR5 TR4 8V FOS2 L /L' 1 2 R7 12 V R5 R6 D2 TR3 2 1 TR2 3 FOS 1 4 5 31 32 D1 R6 SIF AMPL. 29 5V 27 FM MIXER & AM DEM. 20 IF AMPL. & VIDEO SWITCH 6V STD 30 VIF SWT. 9 28 3 6 19 L/L' R20 11 24 VCO L1 25 23

8V

7 6 HEADPHONES AMPLIFIER IC 4 TDA2822M 2 4 12 V

1 3

5 6

EF

TUNER & VIF AGC

AFC 21

3 KIA7812 2 1 IC 5 26 V FROM PIM 7 A2

FPLL

VIDEO DEMOD. AF AMPL. & SWT.

10

F19NICAM.DRV E.G 5/11/99

6V

22 12 17 MUTE

TDA 9811 IC 1

F19 NICAM MODULE

STEREO MODULE CONNECTOR

3 4 7 1 2 8 9 9 8

IC 400 TDA1521A
7 6 5 4 3 2 1

1 3

FROM PIN 11 TUNER (I.F.)

FROM PIN 6 IC 100 AV1 / AV2 SWITCH 2 19 6 18 16 10 2 15 11 1 4 20

TR110

FROM PIN8 IC 100 SCART/CINCH SWITCH

SCART 1

17

12

13 14

15

12 14 13 11

AUDIO CINCH IN

FROM PIN 7 IC 100 TV/AV SWITCH TO AV2 F19ASSPH.DRW E.G. 29/12799

IC201 (2/3 OF LA7955) SCART 2

6 2 1 3

IC200 (2/3) HEF 4053

F19 AUDIO STEREO SIGNAL PATH

TDA4605
Control IC for Switched-Mode Power Supplies using MOS-Transistors
Features Fold-back characteristic provides overload protection for external components Burst operation under short-circuit conditions Loop error protection Switch-off if line voltage is too low (undervoltage switch-off) Line voltage compensation of overload point Soft-start for quiet start-up Chip-over temperature protection (thermal shutdown) On-chip parasitic transformer oscillation suppression circuitry

Functional desciption The IC TDA 4605-1 controls the MOS-power transistor and performs all necessary regulation and monitoring functions in free running flyback converters. Since good load regulation over a wide load range is attained, this IC is applicable tor consumer and industrial power supplies. The serial circuit of power transistor and primary winding of the flyback transformer is connected to the input voltage. During the switch - on period of the transistor, energy is stored in the transformer and during the switch - off period it is fed to the load via the secondary winding. By varying switch-ontime of the power transistor, the IC controls each portion of energy transferred to the secondary side such that the output voltage remains nearly independent ot load variations. The required control information is taken from the input voltage during the switch-on period and from a regulation winding during the switch-off period. In the different load ranges the switched-mode power supply (SMPS) behaves as follow:

TDA4605 SMPS CONTRO I.C. e.g.tda4605R.doc

Pagina 1 di 6

No load operation: The power supply unit oscillates at its resonant frequency typ. 100 kHz to 200 kHz. Depending upon the transformator windings the output voltage can be slightly above nominal value. Nominal operation: The switching frequency declines with increasing load and decreasing AC-voltage. The duty factor primarly depends on the AC-voltage. The output voltage is load-dependent only. Overload point: Maximal output power is available at this point ot the output characteristic. Overload: The energy transferred per operation cycle is limited at the top. Therefore the output voltage declines by secondary overloading..Semiconductor Group 35

TDA 4605 Pin Definitions and Functions

Pin No. Function 1 Regulating Voltage: Information input concerning secondary voltage. By

comparing the regulating voltage - obtained from the regulating winding ot the transformer - with the internal reference voltage, the output impulse width on pin 5is adapted to the load ot the secondary side (normal, overload, short-circuit, no load). 2 Primary Current Simulation: Information input regarding the primary current.

The primary current rise in the primary winding is simulated at pin 2 as a voltagerise by means ot external RC-element. When a value is reached that is derivedfrom the regulating voltage at pin 1, the output impulse at pin 5 is terminated. TheRC-element serves to set the maximum power at the overload point set. 3 Input for Primary Voltage Monitoring: In the normal operation V 3 is moving between the thresholds V 3H and V 3L (V 3H > V 3 > V 3L ). V 3 < V 3L : SMPS is switched OFF (line voltage too low). V 3 > V 3H : Compensation of the overload point regulation (controlled by pin 2) starts at V 3H : V 3L = 1.7. TDA4605 SMPS CONTRO I.C. Pagina 2 di 6 e.g.tda4605R.doc

4 5

Ground Output: Push-pull-output provides 1 A for rapid charge and discharge of the

gate capacitance ot the power MOS-transistor. 5 Supply Voltage Input: A stable internal reference voltage V REF is derived from the supply voltage also the switching thresholds V 6A , V 6E , V 6 max and V 6 min for the supply voltage detector. If V 6 > V 6E then V REF is switched on and swiched off when V 6 < V 6A . In addition the logic is only enable for V 6 min < V 6 < V 6 max . 7 Soft-Start: Input for soft-start. Start-up will begin with short pulses by connecting a

capacitor from pin 7 to ground. 8 Zero Detector: Input tor the oscillation feedback. After starting oscillation, every

zero transit of the feedback voltage (falling edge) triggers an output impulse at pin 5. The trigger threshold is at + 50 mV typical..Semiconductor Group 36 TDA 4605 Application Circuit Application circuit shows a flyback converter for video recorders with a power rating of 50 W. The circuit is designed as a wide-range power supply tor AC-line voltages ot 90 to 270 V. The AC-input voltage is rectified by bridge rectifier GR1 and smoothed by C 1 . The NTC limits the rush in current.In the period before the switch-on threshold is reached the IC is supplied via resistor R 1 ; during the start-up phase it uses the energy stored in C 2 , under steady-state conditions the IC receives its supply voltage from transformer winding n 1 via diode D1. The switching transistor T1 is a BUZ 90. The parallel-connected capacitor C 3 and the inductance ot primary winding 112 determine the system resonance frequency. The R 2 - C 4 - D2 circuitry limits overshoot peaks, and R 3 protects the gate of T1 against static charges. While T1 conducts, the current rise in the primary winding depends on the windings inductance and the V C1 voltage. A voltage reproduction ot the current rise is tabbed using the R 4 - C 5 network and forwarded into pin 2 ot the IC. The RC-time constant ot R 4 , R 5 must be dimensioned correctly in order to prevent driving the transformer core into saturation. The R 10 /R 11 divider ratio provides the line voltage threshold controlling the undervoltage control circuit in the IC. The voltage present at pin 3 also determines the overload. Detection of overload together with the current characteristic at pin 2 controls the on period ot T1. This keeps the cut-off point stable even with higher AC-line voltages. TDA4605 SMPS CONTRO I.C. e.g.tda4605R.doc Pagina 3 di 6

Pin 3 The down-divide primary voltage applied there stabilizes the overload point. In addition the logic is disabled in the event of low voltage by comparison with the internal stable voltage V V in the primary voltage monitor block. Pin 4 Ground Pin 5 In the output stage the output signals produced by the logic are shifted to a leved suitable for MOS-power transistors. Pin 6 From the supply voltage V 6 are derived a stable internal reference V REF and the switching threshold V 6A , V 6E , V 6 max and V 6 min for the supply voltage monitor. All reference values (V R , V 2B , V ST ) are derived from V REF . If V 6 > V VE the V REF is switched on and switched off when V 6 < V 6A . In addition, the logic is released only for V 6 min < V 6 < V 6 max . Pin 7 The output of the overload amplifier is connected to pin 7. A load on this output causes a reductio in maximal impulse duration. This function can be used to implement a soft start, when pin 7 is connected to ground by a capacitor Pin 8 The zero detector controlling the logic block recognizes the transformer being discharged by positive to negative zero crossing of pin 8 voltage and enables the logic for a new pulse. Parasitic oscillations occurring at the end of a pulse cannot lead to a new pulse (double-pulsing), because an internal circuit inhibits the zero detector for a finite time t UL after the end of each pulse.

Start-Up Behaviour The start-up behaviour of the application circuit per sheet 48 is represented on sheet 50 for a line voltage barely above the lower acceptable limit voltage value (without soft-start). After applying the line voltage at the time t 0 to the tollowing voltages built up: V 6 corresponding to the half-wave charge current over R 1 V 2 to V 2 max (typically 6.6 V) V 3 to the value determined by the divider R 10 /R 11 . The current drawn by the IC in this case is less than 1.6 mA. If V 6 reaches the threshold V 6E (time point t 1 ), the IC switches on the internal reference voltage. The currentdraw max. rises to 12 mA. The primary current- voltage reproducer regulates V 2 down to V 2E and the starting impulse generator generates the starting impulses from time point t 5 to t 6 . The feedback to pin 8 starts the next impulse and so on. All impulses including the starting impulse are TDA4605 SMPS CONTRO I.C. e.g.tda4605R.doc Pagina 5 di 6

controlled in width by regulating voltage of pin 1. When switching on this corresponds to a short-circuit event, i.e. V 1 = 0. Hence the IC starts up with "short-circuit impulses" to assume a width depending on the regulating voltage feedback (the IC operates in the overload range). The maximum pulse width is reached at time point t 2 (V 2 = V 2 max ). The IC operates at the overload point. Thereafter the peak values ot V 2 decrease rapidly, as the IC is operating within the regulation range. The regulating loop has built up. If voltage V 6 falls below the switch-off threshold V 6 min before the reversal point is reached, the starting attempt is aborted (pin 5 is switched to low). As the IC remains switched on, V 6 further decreases to V 6 . The IC switches off; V 6 can rise again (time point 14) and a new start-up attempt begins at time point t 1 . If the rectified alternating line voltage (primary voltage) collapses during load, V 3 can fall below V 3A , as is happening at time point t 3 (switch-on attempt when voltage is too low). The primary voltage monitor then clamps V 3 to V 3S until the IC switches off (V 6 < V 6A ). Then a new start-up attempt begins at time point t

Regulation, Overload and No-Load Behaviour When the IC has started up, it is operating in the regulation range. The potential at pin 1 typically is 400 mV. If the output is loaded, the regulation amplifier allows broader impulses (V 5 = H). The peak voltage value at pin 2 increases up to V 2S max . If the secondary load is further increased, the overload amplifier begins to regulate the pulse width downward. This point is referred to as the overload point of the power supply. As the IC supply voltage V 6 is directly proportional to the secondary voltage, it goes down in accordance with the overload regulation behaviour. If V 6 falls below the value V 6 min , the IC goes into burst operation. As the time constant of the half-wave charge-up is relatively large, the short-circuit power remains small. The overload amplifier cuts back to the pulse width t pk . This pulse width must remain possible, in order to permit the IC to start-up without problems from the virtual short circuit, which every switching on with V 1 = 0 represents. If the secondary side is unloaded, the loading impulses (V 5 = H) become shorter. The frequency increases up to the resonance frequency of the system. If the load is further reduced, the secondary voltages and V 6 increase. When V 6 = V 6 max , the logic is blocked. The IC converts to burst operation. This renders the circuit absolutely safe under no-load conditions.

TDA4605 SMPS CONTRO I.C. e.g.tda4605R.doc

Pagina 6 di 6

Regulation of the switched-mode power supply is via pin 1. The control voltage of winding n 1 during the off-period of T1 is rectified by D3, smoothed by C 6 and stepped down at an adjustable ratio by R 5 , R 6 and R 7 . The R 6 - C 7 network suppresses parasitic overshoots (transformer oscillation). The peak voltage at pin 2, and thus the primary peak current, is adjusted by the IC so that the voltage applied across the control winding, and hence the output voltages, are at the desired level. When the transformer has supplied its energy to the load, the control voltage passes through zero. The IC detects the zero crossing via series resistors R 9 connected to pin 8. But zero crossings are also produced by transformer oscillation after T1 has turned off if output is short-circuited. Thereforethe IC ignores zero crossings occurring within a specitied period of time after T1 turn-off. The capacitor C 8 connected to pin 7 causes the power supply to be started with shorter pulses to keep the operating ftrequency outside the audible range during start-up. On the secondary side, tive output voltages are produced across winding n 3 to n 7 rectified by D4 to D8 and smoothed by C 9 to C 13 . Resistors R 12 , R 14 and R 19 to R 21 are used as bleeder resistors. Fusable resistors R 15 to R 18 protect the rectifiers against short circuits in the output circuits, which are designed to supply only small loads.. TDA 4605 Block Diagram

Pin 1 The regulating voltage forwarded to this pin is compared with a stable internal reference voltage V R in the regulating and overload amplifier. The output of this stage is ted to the stop comparator. Pin 2 A voltage proportional to the drain current ot the switching transistor is generated there by theexternal RC-combination in conjunction with the primary current transducer. The output of this transducer is controlled by the logic and referenced to the internal stable voltage V 2B . If the voltage V 2 exceeds the output voltage of the regulating amplifier, the logic is reset by the stop comparator and consequently the output ot pin 5 is switched to low potential. Further inputs tor the logic stage are the output for the start impulse generator with the stable reference potential V ST and the supply voltage monitor. TDA4605 SMPS CONTRO I.C. e.g.tda4605R.doc Pagina 4 di 6

MAINS INPUT
NON MAINS ISOLATED SECTOR

F 19 S.M.P.S.
(CONFIGURATION WITHOUT ZERO POWER STAND BY MODULE) line output stage TR 1 STH7N80FI
D6 3 DRIVE OUTPUT PULSE ZERO CROSSING DETECTOR 11 8 2 5 1 9 6 / 16 12 D8 R14 4 8 9 10 2

148 V (110)

TR 4 TR3

26 V

15

START-UP

D13

sound power line driver 26 V 12 V signal processing

128 V

R1

SOFTSTART

stand by
8,5v 5V

SMPS CONTROL IC1 TDA 4605 4 3 2

1

T1 FROM PIN 19 OFF IC 100 ON SAA5297A

TR6

TR 2

TR5

PRIMARY VOLTAGE & CURRENT SENSING

SUPPLY VOLTAGE ADJUSTMENT OVER LOAD PROTECTION

5V
F19SMPS.DRW E.G. 7/11/99

line output stage

15 2 4

148 V (110)

TR 4 TR3

26 V

F 19
LOW POWER STAND-BY CONFIGURATION
5V
stand by

sound power line driver

26 V

128 V
3 11 8 2 1 9 6 / 16 5 4 10

IC10 TDA8183
9 8

12 V signal processing 5V 8,5v

OFF ON

12

FROM PIN 19 IC 100 SAA5297A

T1
TR 2

MAINS TO MAIN BOARD

T1

1
9
FROM MAINS SWITCH 1 IC 1 L7805CV 3 X1 X2 X3 IC2 IL410

TR2 BT808

7 5

A12 ON-OFF

STAND-BY MODULE

5 V ST-BY F19LPSBC.DRW E.G. 14 /11/99

F19 F19 SERVICE MODE

For the description of the use of the TV make use of the Instruction Manual

Service mode
As already mentioned in the summary the remote control can be used to set all parameter and to adjust the TV set without to open the back cover. There are two ways to enter the "SERVICE MODE" that are to use the LOCAL KEYBOARD or to have a precial prepared REMOTE CONTROL. FIRST METHOD. (If the special remote control is available use the button following the indication of the Table 1

Table 1 List of command of the "SERVICE REMOTE CONTROL" BUTTON RC5 Sub Decimal Coce System 0 1 2 3 4 5 6 7 8 9 Pr + Pr Vol + Vol TV MEM MENU SERVICE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 0 1 2 3 4 5 6 7 8 9 32 33 16 17 63 50 53 58 Vertical Slope Vertical Amplitude Vertical Shift Vertical S Correctio Horizontal Shift HorizontalAmplitude E-W parabola E-W Corner E-W Trapezium AGC Up Carousel of all Service Parameter Down Carousel of all Service Parameter Adjust Parameter Value (UP) Adjust Parameter Value (Down) Leave SERVICE MODE" without to store Leave SERVICE MODE with store Wred SERVICE MODE ENTER

Function

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f19intro

Table 2 Parameter and value to be adjusted in "SERVICE MODE" PARAMETER init ctvfor v0.6 vg2test txtbri txtcon 884c04 884c03 88c02 optionb1 optionb2 optionb3 nicamuperror nicamlowerror nicamcon pipcontrast wblue wgreen wred ydelaypal ewtrapeze ewcorner ewparab ewwidth h-shift s-corr v-shift v-ampl v-slope agc if xx afc 2/3 VALUE on/ off on/off 0--63 0--63 Bit (FSU) Bit (FSU) Bit (FSU) Bit (FSU) Bit (FSU) DESCRIPTION Default Initialization Cut -off adjustment Adjust TXT brightness Adjust TXT Contrast Increase blue stretch and the dynamic skin Adj. acl (automatic colour limiter - and cathode drive level. Adj.(black stretch), blue stretch, and the blue back Select TV standard and TXT character set Scart type selections (

Bit (FSU) (*) Hotel mode setting 0--63 0--63 Bit (FSU) 0--15 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 0--63 Nicam sensitivity (upper limit) Nicam sensitivity (Lower limit). Tda9875 CONTROL PIP Contrast control Blue channel gain Green channel gain Red channel gain Luma chroma delay E-W- Trapezium adjustment E-W- Corner Adjustment E-W- Parabola Adjustment Horizontal Amplitude Horizontal shift Vertical S-Correction Shift Vertical Vertical Amplitude Slope Vertical AGC adjustment

0--63 (FSU) Factory set up

(*) REDUCE OF A QUANITY 4 TO GET HOTEL MODE

LEGENDA: (FSU)= FACTORY SET UP

WARNING!! Do not change value for those parameter that are highlighted please
E.G.Data creazione 31/10/99 15.38 5/7 f19intro

Note 1 If during the installation of the TV set the AUTOSTORE" method is used, it is

fundamental, before to start the function, to select the name of the country as the criteria of listing the broadcasters names is fixed by EBU table that are related to the country itself. It is possible to find more channels of the same broadcaster on the Arial. In this case the system will place first the signal having TXT with the strongest signal level than the others and finally, with the found sequence the weakest one without TXT. Note 2 To get HOTEL MODE it is necessary to enter "SERVICE MODE" and to change the parameter "optionb3". Read the original value e subtract 4 (decimal). In HOTEL MODE all tuning systems are not possible, the volume is pre fixed and the MENU from the LOCAL KEY BOARD is not accessible. Note 3 For fast programming (in case of installation of several TV set in Shops or Hotels a "Black Box" is available on request. The procedure for a quick program is as follows: 1. Install and tune all channel storing it in the program sequence you want 2. Switch off the Set with the remote control and leave it in Stand-by mode 3. Switch on the "Black Box" and connect it to Scart 4. Press the button corresponding to the chassis to be programmed and at the same time press the button "Read" for a while. (corresponding LED will be on. 5. When the LED "Write" became off (after few seconds) disconnect the "Black Box" 6. Insert the Black Box in the new TV set (in stand by condition) 7. Press F19 and "Write" buttons at same time. Corresponding "Write" LED will light 8. After few seconds when the "Write" LED will switch-off the procedure is finished . 9. Repeat points from 6 to 8 to program others TV set

WARNING!!!!! The above procedure can be applied only to TV set specially prepared for this functions

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Table 4 List of languages that can be reproduced as a function of the TXT characters set setting with the optionb1 (bit number 6) WEST EUROPE CHARACTER SET LANGUAGES ENGLISH GERMAN SWEDISH ITALIAN FRENCH SPANISH TURKISH EAST EUROPE CHARACTER SET LANGUAGES POLISH GERMAN ESTONIA SERB-CROAT CZECH RUMEN

Just to give an example how to set the option byte 1, 2, and 3 we can start from a TV set for BG standard, with hyperband tuner to be sold in a country using West European character set. Locking at the table 3 Optionb1 we have the following condition:

BIT NUMBER 0 1 2 3 4 5 6 7 0 BG L/L' I DK X X

OPTIONB1 1 VALUE WEIGHT 1 0 0 0 0 0 1 1 64 128 1 Adding the value of the last column we get 193 in decimal form and C! in hexadecimal. This means that we have to choose this value (C1) for the optionb1 in service mode

E.E.TXT W.E. TXT CATV

If we want to change from West Europe character set to East Europe, bit 6 became 0 that is the new value is 129 (128 plus 1)that in hexadecimal format is 41

REMEMBER TO INSERT COUNTRY TABLE

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THE SECOND METHOD to enter service mode is to use the LOCAL KEY BOARD as describe here below 1. Starting from TV off press VOLUME + on the LOCAL KEYBOARD and in the mean time switch on the TV with the mains switch 2. Within three second switch on the TV using the "SWITCH-OFF" button on the Remote Control 3. A small windows with black background and yellow characters will appear in the middle of the screen.

PARAMETER VALUE
4. Using the Remote control, program + / - (top bottom) will change the "PARAMETER" and the VOLUME + / - (left / right) will change the value 5. Each parameter can be stored, leaving the service mode, by using the MEM (yellow) button on the remote control 6. To leave "SERVICE MODE" without to store the new value use the TV button. 7. It is not necessary to store each value one by one this means that you can change all value you need and finally leave the SERVICE MODE pressing the YELLOW button MEM. In the Table 3 we can find all parameter and related value to be seated. Some parameter have to adjusted with a simple on-off value, others are just factory option and more others must be adjusted with value that are expressed in hexadecimal form ranging from 0 to FF (that is from 0 to 63 in decimal form ). Table 3 represent the value to be assigned to three parameter to properly set options: Table 3 Option bye (1, 2 and 3) value and related meaning BIT WEIGHT 0 1 2 3 4 5 6 7 E.E.TXT 0 BG L/L' I DK X X W.E.TXT CATV 4/7 OPTIONB1 1 0 OPTIONB2 1 2 SCART MUST BE 1 CINCH SVHS RGB X X X f19intro HOTEL NTSC M UV1316 V. GUARD 0 FSU
BACKGROUND

OPTIONB3 1

E.G.Data creazione 31/10/99 15.38

PICTURE IN PICTURE MODULE

SDA 9288X
PICTURE IN PICTURE
1 General Description

The Picture-in-Picture Processor SDA 9288X A141 generates a picture of reduced size of a video signal (inset channel) for the purpose of combining it with another video signal (parent channel). The easy implementation of the IC in an existing system needs only a few additional external components. There is a great variety of application facilities professional and consumer products (TV sets, supervising monitors, multi-media, )
Data Sheet

212 luminance and 53 chrominance pixels per inset line for picture size 1/9 6-bit amplitude resolution for each incoming signal component Field and frame mode display Horizontal and vertical filtering Special antialias filtering for the luminance signal Operation in 4:3 and 16:9 sets 4:3 inset signals on 16:9 displays or v.v. with picture size 1/9 and 1/16, respectively Y, + (B-Y), + (R-Y) or Y, -(B-Y), -(R-Y) Y, + (B-Y), + (R-Y) or Y, (B-Y), (R-Y) or RGB 3 RGB matrices: EBU, NTSC (Japan), NTSC (USA) Steps of 1 pixel and 1 line All PIP and POP positions are possible

16:9 compatibility

Analog inputs

Analog outputs

Free programmable position of inset picture

2 picture sizes

1/9 or 1/16 of normal size

High resolution display

13.5 MHz/27 MHz display clock frequency

Freeze picture I 2 C Bus control
SDA 9288X P.I.P. Pagina 1 di 4 e.g. sda9288xR.doc

Threefold PIP/POP facility

Three different I 2 C-addresses (pin-programmable)

System Description AD Conversion, Inset Synchronization

The inset video signal is fed to the SDA 9288X A141 as analog luminance and chrominance components 1) . The polarity of the chrominance signals is programmable. After clamping the video components are AD-converted with an amplitude resolution of 6 bit. The conversion is done using a 13.5 MHz clock for the luminance signal and a 3.375 MHz clock for the chrominance signals. For the adaption to different application the clamp timing for the analog inputs can be chosen (CLPS; CLPFIX). Setting this bits to 1 can be useful for non-standard input signals. For inset synchronization it is possible to feed either a special 3-level signal via pin HVI (detection of horizontal and vertical pulses) or separate signals via pins SCI for horizontal and VI for vertical synchronization. SCI is the horizontal synchron signal of the inset channel. If the burst gate pulse of the sandcastle is used it must be adapted to TTL compatible levels by a simple external circuit. Centering of the displayed picture area is possible by a programmable delay for the horizontal synchronization signal (HSIDEL). The inset horizontal synchronization signals are sampled with 27 MHz. This 27 MHz clock and the AD converter clocks are derived from the parent horizontal synchronization pulse or from the quartz frequency converted by a factor of 4/3. Delay differences between luminance and chrominance signals at the input of the IC caused by chroma decoding are compensated by a programmable luminance delay line (YDEL) of about 290 ns 740 ns (at decimation input By analyzing the synchronization pulses the line standard of the inset signal source is detected and interference noise on the vertical sync signal is removed. For applications with fixed line standard (only 625 lines or 525 lines) the automatic detection can be switched off. The phase of the vertical sync pulse is programmable (VSIDEL; VSPDEL). By this way a correct detection of the field number is possible, an important condition for frame mode display.
Input Signal Processing
SDA 9288X P.I.P. Pagina 2 di 4 e.g. sda9288xR.doc

This stage performs the decimation of the inset signal by horizontal and vertical filtering and sub-sampling. A special antialias filter improves the frequency response of the luminance channel. It is optimized for the use of the horizontal decimation factor 3:1. A window signal, derived from the sync pulses and the detected line standard, defines the part of the active video area used for decimation. For HSIDEL = 0 the decimation window is opened about 104 clock periods (13.5 MHz) after the horizontal synchronization pulse. For the 625 lines standard the 36th video line is the first decimated line, for the 525 lines standard decimation starts in the 26th video line. The realized chrominance filtering allows omitting the color decoder delay line for PAL and SECAM demodulation if the color decoder supplies the same output voltages independent of the kind of operation. In case of SECAM signals an amplification of the chrominance signals by a factor of 2 is necessary because just every second line a signal is present. This chrominance amplification is programmable via pin SYS or I 2 C Bus (AMSEC). The horizontal and vertical decimation factors are free programmable (DECHOR, DECVER). Using different decimations horizontal and vertical 16:9 applications become realizable: DECHOR = 1, DECVER = 0: picture size 1/9 for 4:3 inset signals on 16:9 displays DECHOR = 0, DECVER = 1: picture size 1/16 for 16:9 inset signals on 4:3 displays
PIP Field Memory

The on-chip memory stores one decimated field of the inset picture. Its capacity is 169 812 bits. The picture size depends on the horizontal and vertical decimation factors. In field mode display just every second inset field is written into the memory, in frame mode display the memory is continuously written. Data are written with the lower inset clock frequency depending on the horizontal decimation factor (4.5 MHz or 3.375 MHz). Normally the read frequency is 13.5 MHz and 27 MHz for scan conversion systems. For progressive scan conversion systems and HDTV displays a line doubling mode is available (LINEDBL). Every line of the inset picture is read twice. Memory writing can be stopped by program (FREEZE), a freeze picture display results (one field). Having no scan conversion and the same line numbers in inset and parent channel (625 lines or 525 lines both) frame mode display is possible. The result is a higher vertical and time resolution because of displaying every incoming field. For this purpose the standards are internally analysed and activating of frame mode display is blocked automatically when the described restrictions are not fulfilled. As in the inset channel a field number detection is carried out for the parent channel.
SDA 9288X P.I.P. Pagina 3 di 4 e.g. sda9288xR.doc

Depending on the phase between inset and parent signals a correction of the display raster for the read out data is performed by omitting or inserting lines when the read address counter outruns the write address counter. The display position of the inset picture is free programmable (POSHOR, POSVER). The first possible picture position (without frame) is 54 clock periods (13.5 MHz or 27 MHz) after the horizontal and 4 lines after the vertical synchronization pulses. Starting at this position the picture can be moved over the whole display area. Even POP-positions (Picture Outside Picture) at 16:9 applications are possible.
Horizontal Decimation PIP PIXELS per Line

Having different line standards in inset and parent channels we have a so called mixed mode display. It causes deformations in the aspect ratio of the inset picture. A special mixed mode display is available for the picture size 1/9 (MIXDIS): Synchronization of memory reading with the parent channel is achieved by processing the parent horizontal and vertical synchronization signals in the same way as described for the inset channel. The synchronization signals are fed to the IC at pin HP/SCP for horizontal synchronization and pin VP for vertical synchronization. In the same way as described for the inset channel the burst gate of the sandcastle signal can be used for horizontal synchronization. In scan conversion systems also the inputs HPD/SCI and VPD/VI are available if the input HVI is activated for inset synchronization.
2.4 Output Signal Processing

At the memory output the chrominance components are demultiplexed and linearly interpolated to the luminance sample rate. Different output formats are available: luminance signal Y with inverted or non-inverted chrominance signals (B-Y), (R-Y) or RGB. For the RGB conversion 3 matrices are integrated: Matrix selection is done by pin SYS or I 2 C Bus. The matrices are designed for the following input voltages (100 % white, 75 % color saturation):

SDA 9288X P.I.P.

Pagina 4 di 4

e.g. sda9288xR.doc

TDA8310A
PAL/NTSC colour processor for PIP applications
FEATURES Video switch with 2 CVBS inputs. One input can beswitched between CVBS and Y/C and the circuit can automatically detect whether the incoming signal is CVBS or Y/C Integrated chrominance trap and bandpass filters (automatically calibrated) Integrated luminance delay line Automatic PAL/NTSC decoder which can decode all standards available in the world Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications Horizontal PLL with an alignment-free horizontal oscillator Vertical count-down circuit RGB/YUV and fast blanking switch with 3-state output and active clamping Low dissipation (560 mW) Small amount of peripheral components compared with competition Ics GENERAL DESCRIPTION The TDA8310A is an alignment-free PAL/NTSC colour processor for Picture-in-Picture (PIP) applications. The main difference between the TDA8310 and the TDA8310A is that the vision IF amplifier has been omitted in the TDA8310A. Therefore, the circuit contains an input signal selector, a PAL/NTSC colour decoder, horizontal and vertical synchronization and an RGB/YUV switch. The input signal selector has 2 CVBS inputs. One of the inputs can be switched between CVBS and Y/C and the circuit can automatically detect whether the incoming signal is CVBS or Y/C. The output signals for the PIP processor are: Luminance signal Colour difference signals (U and V) Horizontal and vertical synchronization pulses. The RGB/YUV switch can select between two RGB or YUV sources, e.g. between the PIP processor and the

SCART input signal. The supply voltage for the IC is 8 V. It is available in a 52-pin SDIP package.

FUNCTIONAL DESCRIPTION CVBS switch The circuit contains a 2 input CVBS switch and one of the inputs can be switched between CVBS and Y/C. The circuit contains an identification circuit which can automatically switch between the CVBS and Y/C signals. It is also possible to force the switch to CVBS or Y/C.

TDA8310A CHROMA DECODER FOR PIP

Pagina 1 di 2

e.g. TDA8310A.doc

Synchronization circuit The sync separator is preceded by a voltage controlled amplifier which adjusts the sync pulse amplitude to a fixed level. The sync pulses are fed to the slicing stage (separator) which operates at 50% of the amplitude. The separated sync pulses are fed to the first phase detector and to the coincidence detector. The coincidence detector is used to detect whether the line oscillator is synchronized and for transmitter identification. The first PLL has a very high static steepness this ensures that the phase of the picture is independent of the line frequency. The line oscillator operates at twice the line frequency. The oscillator network is internal. Because of the spread of internal components an automatic adjustment circuit has been added to the IC. The circuit compares the oscillator frequency with that of the crystal oscillator in the colour decoder. This results in a free-running frequency which deviates less than 2% from the typical value. The horizontal output pulse is derived from the horizontal oscillator via a pulse shaper. The pulse width of the output pulse is 5.4 ms, the front edge of this pulse coincides with the front edge of the sync pulse at the input. The vertical output pulse is generated by a count-down circuit. The pulse width is approximately 380 ms. Both the horizontal and vertical output pulses will always be available at the outputs even when no input signal is available. In addition to the horizontal and vertical sync pulse outputs the IC has a sandcastle pulse output which contains burst key and blanking pulses. Integrated video filters The circuit contains a chrominance bandpass and trap circuit. The filters are realised by gyrator circuits that are automatically tuned by comparing the tuning frequency with the crystal frequency of the decoder. When a Y/C signal is supplied to the input the chrominance trap is automatically switched off by the Y/C detection circuit however, it is also possible to force the filters in the CVBS or Y/C position. The luminance delay line is also realised by gyrator circuits. Colour decoder The colour decoder contains an alignment-free crystal oscillator, a colour killer circuit and colour difference demodulators. The 9 0 phase shift for the reference signal is achieved internally. The colour decoder is very flexible. Together with the SECAM decoder (TDA8395) an automatic multistandard decoder can be designed but it is also possible to use it for one standard when only one crystal is connected to the IC. The decoder can be forced to one of the standards via the forced mode pins. The crystal pins which are not used must be connected to the positive supply line via a 8.2 resistor. It is also possible to connect the non-used pins with one resistor to the positive supply line. In this event the resistor must have a value of 8.2 divided by the number of pins. The chrominance output signal of the video switch is externally available and must be used as an input signal for the SECAM decoder. RGB/YUV switch The RGB/YUV switch is for switching between two RGB or YUV video sources. The outputs of the switch can be set to high-impedance state so that other switches can be used in parallel. The switch is controlled via pins 13 and 52.

TDA8310A CHROMA DECODER FOR PIP

Pagina 2 di 2

e.g. TDA8310A.doc

INTB

VP1 PH1LF 37 DECBG 35 DECDIG 21 19

VP2 41 30

HOUT VOUT 39 36

SAND 40

COINCIDENCE/ NOISE DETECTOR

PHASE DETECTOR

VCO + CONTROL

10 PULSE SHAPER SANDCASTLE GENERATOR R1 11 12 13 G1 B1

i.c. n.c.

22, 29 33, 34 SYNC SEPARATOR VERTICAL SYNC SEPARATOR HORIZONTAL/ VERTICAL DIVIDER RGB/YUV SWITCH 14

BLANK1 CLAMP 8 7 6 R G B BLANK R2 G2 B2 BLANK2 IDENT HUE

DECFT

5 15

TDA8310A

1 2 3

CHROMINANCE BANDPASS

CHROMINANCE TRAP

FILTER TUNING

52

4 CVBSSW 32 REF 28 AUTOMATIC Y/C DETECTOR INPUT SELECTOR PAL/NTSC DECODER LUMINANCE DELAY LINE 49

31

20

17

16

47

48

46 PLL

45 XTAL4

44 XTAL3

43 XTAL2

42 XTAL1

27

26

25

24

23

50

51

18

38

MGD128

CVBSEXT GND2 CVBSINT

CHROMAI

SECAM

R/W

COLOUR2

LOGIC2 B Y

R Y GND1 GND3

SYSTSW

CHROMAO

COLOUR1

LOGIC1

th

PINNING SYMBOL R2 G2 B2 IDENT BLANK B G R SYSTSW R1 G1 B1 BLANK1 CLAMP DECFT CHROMAI CVBSEXT GND1 VP1 CVBSINT DECDIG i.c. LOGIC2 LOGIC1 COLOUR2 COLOUR1 R/W PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 DESCRIPTION RED input 2 (PIP) GREEN input 2 (PIP) BLUE input 2 (PIP) colour standard identication output blanking output BLUE output GREEN output RED output CVBS/system switch RED input 1 GREEN input 1 BLUE input 1 blanking input 1 clamping pulse input decoupling lter tuning chrominance input external CVBS/Y input ground 1 (0 V) supply voltage 1 (+8 V) internal CVBS input decoupling digital supply rail internally connected (test purposes) crystal logic 2 input/output crystal logic 1 input/output colour system logic 2 input/output colour system logic 1 input/output read/write selection input n.c. n.c. DECBG VOUT PH1LF GND3 HOUT SAND VP2 XTAL1 XTAL2 XTAL3 XTAL4 PLL CHROMAO SECAM Y BY RY BLANK2 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 SYMBOL HUE i.c. INTB GND2 CVBSSW PIN 28 29 30 31 32 DESCRIPTION HUE control input internally connected (test purposes) internal bias ground 2 (0 V) CVBS positive/negative modulation control switch input not connected not connected bandgap decoupling vertical sync output pulse phase 1 loop lter ground 3 (0 V) horizontal sync output pulse sandcastle pulse output supply voltage 2 (+8 V) 4.4336 MHz crystal 3.5820 MHz crystal for PAL-N 3.5756 MHz crystal for PAL-M 3.5795 MHz crystal for NTSC PLL colour lter chrominance output for TDA8395 SECAM reference output Y output BY output RY output blanking/insertion input 2 (PIP)

TDA8395
SECAM DECODER
FEATURES Fully integrated filters Alignment free For use with baseband delay GENERAL DESCRIPTION The TDA8395 is a self-calibrating, fully integrated SECAM decoder. The IC should preferably be used in conjunction with the PAL/NTSC decoder TDA8362 or TDA8366 and with the switched capacitor baseband delay circuit TDA4660. The IC incorporates HF and LF filters, a demodulator and an identification circuit (luminance is not processed in this IC). The IC needs no adjustments and very few external components are required. A highly stable reference frequency is required for calibration and a two-level sandcastle pulse for blanking and burst gating. FUNCTIONAL DESCRIPTION The TDA8395 is a self-calibrating SECAM decoder designed for use with a baseband delay circuit. During frame retrace a 4.433619 MHz reference frequencyis used to calibrate the filters and the demodulator. Thereference frequency should be very stable during this period. The Cloche filter is a gyrator-capacitor type filter theresonance frequency of which is controlled during the calibration period and offset during scan; this ensures thecorrect frequency during calibration. The demodulator is a Phase-Locked Loop (PLL) type demodulator which uses the frequency reference and the bandgap reference to force the PLL to the required demodulation characteristic. The low frequency de-emphasis is matched to the PLL and is controlled by the tuning voltage of the PLL.

Secam secoder TDA8395

Pagina 1 di 2

e.g. TDA8395R

Fig.1 Block diagram.

PINNING SYMBOL fref/ IDENT TEST VP n.c. n.c. GND CLOCHEref PLLref (RY) (BY) n.c. n.c. n.c. n.c. Fig.2 Pin configuration SAND CVBS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION reference frequency input/identication input test output positive supply voltage not connected not connected ground Cloche reference lter PLL reference (RY) output (BY) output not connected not connected not connected not connected sandcastle pulse input video (chrominance) input

A digital identification circuit scans the incoming signal for SECAM (only line-identification is implemented). The identification circuit needs to communicate with theTDA8362 to guarantee that the output signal from the decoder is only available when no PAL signal has been identified. If a SECAM signal is decoded a request for colour-on is transmitted to pin 1 (current is sunk). If the signal request is granted (i.e. pin 1 is HIGH therefore no PAL) the colour difference outputs (-(-Y) and -( -Y)) from the TDA8362 are high impedance and the output signals from the TDA8395 are switched ON. If no SECAM signal is decoded during a two-frame period the demodulator will be initialized before another attempt is made also during a two-frame period. The CD outputs will be blanked or high-impedance depending on the logic level at pin 1. A two-level sandcastle pulse generates the required blanking periods and, also, clocks the digital identification pulse on the falling edge of the burst gate pulse. To enable The calibration period to be defined the vertical retrace is discriminated from the horizontal retrace, this is achieved by measuring the width of the blanking period.

Secam secoder TDA8395

Pagina 2 di 2

e.g. TDA8395R

TEA6415C
BUS-CONTROLLED VIDEO MATRIX SWITCH
DESCRIPTION 20MHz BANDWIDTH CASCADABLE WITH ANOTHER TEA6415C (INTERNAL ADDRESS CAN BE CHANGED BY PIN 7VOLTAGE) INPUTS (CVBS, RGB, MAC, CHROMA, ...) POSSIBILITY OF MAC OR CHROMA SIGNAL FOR EACH INPUT BY SWITCHING-OFF THE CLAMP WITH AN EXTERNAL RESISTOR BRIDGE BUS CONTROLLED 6.5dB GAIN BETWEEN ANY INPUT AND OUT-PUT -55dB CROSSTALK AT 5MHz FULLY ESD PROTECTED

GENERALDESCRIPTION

The mainfunctionof the IC is to switch 8 video input sources on 6 outputs. Each output can be switched on only one of each input. On each input an alignment of the lowest level of the signal is made (bottom of synch. top for CVBS or black level for RGB signals). Each nominal gain between any input and output is 6.5dB. For D2MAC or Chroma signal the align-ment is switched off by forcing, with an external resistor bridge, 5 VDC on the input. Each input can be used as a normal input or as a MAC or Chroma input (with external resistor bridge). All the switch-ing possibilities are changed through the BUS. Driving 75 load needs an external transistor. It is possible to have the same input connected to several outputs. The starting configuration upon power on (power supply : 0 to 10V) is undetermined. In this case, 6 words of 16 bits are necessary to determine one configuration. In other case, 1 word of 16 bits is necessary to determine one configura-tion
TEA6415C video matrix switch Pagina 1 di 1 e.g. TEA6415C.doc

TDA4665
Baseband delay line
FEATURES

Two comb filters, using the switched-capacitor technique, for one line delay time (64 ms) Adjustment-free application No crosstalk between SECAM colour carriers (diaphoty) Handles negative or positive colour-difference input signals Clamping of AC-coupled input signals ((-Y) and (-Y)) VCO without external components 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 ms line) Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal Addition of delayed and non-delayed output signals Output buffer amplifiers Comb filtering functions for NTSC colour-difference signals to suppress cross-colour GENERAL DESCRIPTION The TDA4665 is an integrated baseband delay line circuit with one line delay. It is suitable for decoders with colour-difference signal outputs (-Y) and (-Y).

TDA4665 Crhroma Delay line

Pagina 1 di 3

e.g.TDA4665.doc

handbook, full pagewidth

(RY)

16

SIGNAL CLAMPING LINE MEMORY SAMPLEAND-HOLD LP

11

(RY)

colour-difference input signals 14

pre-amplifiers

addition output stages buffers

colour-difference output signals

(BY)

SIGNAL CLAMPING LINE MEMORY analog supply FREQUENCY PHASE DETECTOR 3 MHz shifting clock DIVIDER BY 192 6 MHz CCO 1 GND2 DIVIDER BY 2 3 SAMPLEAND-HOLD LP

12

(BY)

VP1 sandcastle pulse input

TDA4665

SANDCASTLE DETECTOR

2 6 13 15

n.c. n.c. n.c. n.c.

LP 10 GND1 digital supply

7 4, 8

i.c.

VP2

MED848

SAA55xx
Standard TV microcontrollers with On-Screen Display (OSD)
1 FEATURES Single-chip microcontroller with integrated On-Screen Display (OSD) Versions available with integrated data capture One Time Programmable (OTP) memory for both program Read Only Memory (ROM) and character sets Single power supply: 3.0 to 3.6 V 5 V tolerant digital inputs and I/O 29 I/O lines via individual addressable controls Programmable I/O for push-pull, open-drain and quasi-bidirectional Two port lines with 8 mA sink (at <0.4 V) capability, for direct drive of Light Emitting Diode (LED) Single crystal oscillator for microcontroller, OSD and data capture Power reduction modes: Idle and Power-down Byte level I 2 C-bus with dual port I/O Pin compatibility throughout family Operating temperature: -20 to +70 C. 2 GENERAL DESCRIPTION The SAA55xx standard family of microcontrollers are a derivative of the Philips industrystandard 80C51 microcontroller, and are intended for use as the central control mechanism in a television receiver. They provide control functions for the television system, OSD, and some versions include an integrated data capture and display function. The data capture hardware has the capability of decoding and displaying both 525 and 625-line World System Teletext (WST), Video Programming System (VPS) and Wide Screen Signalling (WSS) information. The same display hardware is used both for Teletext and OSD, which means that the display features available give greater flexibility to differentiate the TV set. The SAA55xx standard family offers a range of functionality from non-text, 16-kbyte program ROM and 256-byte Random Access Memory (RAM), to a 10-page text version, 64-kbyte program ROM and 1.2-kbyte RAM.

1 2 3 R1 100 R2 100 6 7 C1 470N R3 10K 4 5

PCLK NICAM data I2C addr1 SCL SDA VSSA1 VDEC1 IREF Port 1 SIF2 VREF1 SIF1 I2C addr 2 VSSD1 VDDD1 RESET CAP VSSD4 XTAL IN XTAL OUT PORT2 SYSCLK SCK WS SDO2 SDO1 SOI2 SDI1 TEST1 MONO IN TEST2 Ex InR Ex InL IC1

VDDD264 Line outR Line outL Main outL Main outR

63 62 61 60

100H

820

+6V

C12 22 16V

+26V

Industrie Formenti Italia s.p.a.

+6V R16 470 R17 TR2 BC848 1K2 R18 1K2

Stabilimento di Sessa Aurunca (CE)

100H C18 470 10V

12

AUX outL AUX outR VSSA3

58

R8 10K

R9 10K

R12 47K

R13 47K

R14 1K

R15 1K

Descr.

9 C2 100N C3 100N C4 12 +6V 100 13 14 15 R5 390 C6 470N C7 1 16V C8 10 QZ1 24,576MHZ 16 10 11

56 C19 10N C20 10N C22 22 16V

PCAPL 55 PCAPR 54 VREF3 Sc2 outL Sc2 outR VSSA4 VSSD2 Sc1 outL Sc1 outR VREF2
53 52 51 50 49 C21 47 16V

C24 22 16V R19 10K

R20 47K TR3 BC848 R21 47K R22 1K

R23 1K2

R24 R26 47K TR4 BC848 C23 22 16V R25 10K C25 22 16V R27 47K R28 1K C27 22 16V R29 1K C28 22 16V R30 1K 1K2

R4 4,7 L1 100H

C26 470 35V

17 18 19

48 47 46 C31 47 16V

C9 10

20 21 22 23 24 25 26

I.C. 45 I.C. 44 VSSA2

43 C38 100 16V R33 1K8

C29 2N2

C30 2N2

R31 10K

R32 10K

I.C. 42 I.C. 41 VREF(N) VREF(P)

40 39 R35 270 C32 470N C33 47 16V

C39 100 16V R34 1K8

8 1 IC2 KIA7812 3 2 1 +26V

IC3 TDA2822M 4 3 2

27 28 29 +6V C10 470N 30 31 C5 1000 10V 32

VDEC2 38 Sc2 InL Sc2 InR VSSD3 Sc1 InL Sc1 InR TDA 9870A
37 36 35 34 33 R36 15K R37 15K

C40 1000 16V C41 1000 16V C36 22 16V C37 22 16V

C42 1000 16V

R38 4,7

R39 4,7

C45 22 16V

C46 22 16V

C34 330N C43 100N C44 100N

R40 2K2

R41 2K2

C35 330N 2 1 4 3 10 4

+26V 7 3 6 5 8 9 1 2

12

11

10

A1-F

A1-C

A1-J

A1-D

A2-H

A1-A

A1-G

A2-G

A2-C

A2-D

A1-H

A2-A

A1-K

A1-B

A2-E

A2-F

A1-L

A1-I

A2-J

SC1/ SC2 CINCH

OUT SC

CUFFIA

AP

BB

A2-B

A1-E

A2-I

Data:

Disegnato:

57

+6V

06/07/1999
Scala:

+6V

Di Maio

VDDA3 59

L3

R7

C15 22 16V

C17 22 16V

Approvato:

C13 22 16V

Sost.schema:

C14 22 16V

C16 22 16V

R10 47K

R11 47K

Cod. Schema:

TR1 BC848

Stereo-Nicam i.c. per Telaio F19

531.01S 531.00S

L2

R6

A3-C

A3-A A3-B

1.531.01S

C11 470N

S10.135

511.05S

A3-A

1 2 +12V R78 100 C72 220 16V 17 18 R77 1K2 TR1 BC848 R1 220 R76 1K5 F1 TPS 6,5 L8 6.8H R75 270 21 R36 270 22 23 L1 77,8 MHZ 24 25 C3 22 16V C4 22 16V 26 27 28 29 C40 1000 10V +12V R6 4K7 R7 4K7 +12V FOS1 K9453 C6 10N R4 22K 31 32 5 4 30 19 20 3 16 15 14 13 12 11 R21 1K C20 22 16V R24 100 C22 C24 100N 100N C21 100N R25 12K C26 1 16V C34 10 C23 100N R28 47K C25 100N R27 47K C18 100N R19 1K R71 1K C73 10n C27 470N R32 10K R22 R26 10K C19 100N TR8 BC848 R23 47K 47K R79 10K C28 100N C29 100N C30 12 +6V 100 R33 4,7 L5 100H R34 390 C31 470N C32 1 16V 13 14 15 16 17 18 19 C36 10 20 21 5 22 2 3 4 23 R9 C10 100N R35 47K 47K +6V +12V IC2 L78M08CS 1 C5 1000 10V C11 100N C12 1000 16V 3 2 +8V C69 470 16V C17 470N 24 25 26 27 28 29 30 31 R18 1K C14 1N 32 TR6 BC848 R29 100 R30 100 6 7 8 9 10 11 4 5

PCLK NICAM data I2C addr1 SCL SDA VSSA1 VDEC1 IREF Port 1 SIF2 VREF1 SIF1 I2C addr 2 VSSD1 VDDD1 RESET CAP VSSD4 XTAL IN XTAL OUT PORT2 SYSCLK SCK WS SDO2 SDO1 SOI2 SDI1 TEST1 MONO IN TEST2 Ex InR Ex InL IC3

VDDD264 Line outR Line outL Main outL Main outR

63 62 61 60

R37 820

100H

+6V

C70 22 16V

A3-B

L3

Industrie Formenti Italia s.p.a.

+6V R51 470 R52 TR10 BC848 1K2 R53 1K2

+26V

NC TAGC VoQss Vo Vi AFC VCO1 VCO2 Cref GND CvAgc Vp INSW SIF1 SIF2 IC1 TDA 9811

NC NC NC VoAf LSW

100H C15 470 10V

AUX outL AUX outR VSSA3

58 57 56 C43 10N C44 10N

R57 10K

R56 10K

R40 47K +6V

R41 47K

R42 1K

R43 1K

Descr.

R2 22K C1 1 16V

CVBS10 STD
9

PCAPL 55 PCAPR54 VREF3 Sc2 outL Sc2 outR VSSA4 VSSD2 Sc1 outL Sc1 outR VREF2 I.C.
53 52 51 50 49 48 47 46 45 C45 47 16V

C57 22 16V C41 22 16V R61 10K

R45 47K TR11 BC848 R46 47K R47 1K

R54 1K2

R3 22K

C2 100N

CsAgc8 Tpll TAdj VIF4 VIF3 Cbl VIF2 VIF1

7 6 5 4 3 2 1

R55 R48 47K 1K2 TR12 BC848 R50 1K C58 22 16V R63 1K C59 22 16V R64 1K

+8V

R74 18

L7 100H

C42 22 16V

R62 10K

C56 22 16V

R49 47K

C46 470 35V

+12V D1 LL103 BA682 R5 BA782 2K7 BA783 R31 2K7 C7 1N D2 LL103 BA682 BA782 BA783

QZ1 24,576MHZ

1 2

C47 47 16V

C64 2N2

C65 2N2

R65 10K

R66 10K

C8 1N

FOS2 K3953M

I.C. 44 VSSA2
43 C67 100 16V R68 1K8

TR2 BC848

R8 47K C9 100N

TR3 BC848

I.C. 42 I.C. 41 VREF(N) VREF(P)

40 39 R58 270 C51 470N C50 47 16V

C66 100 16V R67 1K8

5 IC4 4

6 7 TDA2822M 3 2

8 1 IC5 KIA7812 3 2 1 +26V

+12V R10 22 R11 100 L2 1H 1K TR4 BF 959 R14 47 C13 1N R15 120

VDEC238 Sc2 InL Sc2 InR VSSD3 Sc1 InL Sc1 InR TDA 9875
37 36 35 34 33 R59 15K R60 15K

C63 1000 16V C68 1000 16V C54 22 16V C55 22 16V

C62 1000 16V

TR5 BF 959 R12 R13 150 R16 120

R17 3K9

R70 4,7

R69 4,7

C60 22 16V

C61 22 16V

C52 330N C33 100N C35 100N

R72 2K2

R73 2K2

C53 330N 2 1 4 3 10 4

+26V 7 3 6 5 8 9 1 2

11

10

12

A1-F

A1-C

A1-J

A1-D

A2-H

A1-A

A1-G

A2-G

A2-C

A2-D

A1-H

A2-A

A1-K

A1-B

A2-E

A1-I

A2-F

A1-L

A2-J

SC1/ SC2 CINCH

OUT SC

CUFFIA

AP

BB

A2-B

A1-E

A2-I

Scala:

Data:

Disegnato:

R20 22K

TR7 BC848

05/07/2000

12

+6V

Di Maio

VDDA359

L4

R44

C39 22 16V

C48 22 16V

Approvato:

MUTE

NC

C71 22 16V

Sost.schema:

R38 47K

R39 47K

Stereo-Nicam per Telaio F19

C38 22 16V

C49 22 16V

Cod. Schema:

TR9 BC848

Stabilimento di Sessa Aurunca (CE)

511.04S

1.511.05S

A3-C

C37 470N

A3 C5

1.511.05S TOP SILK

C49

C48

C57

C56

C52

C53

J5

J6
C55

C47 R30 R29 R37 R44 J4 R33 L7 IC2 C69 C4 C12 FOS1 C40 C3 L4 C71 C70 C38 L3 C15 C39 C41 C42 C45 C54

R59

R60
C51

C50

R74

J10

C46 IC3 L1 C1 F1 QZ1 L8 C32 J8 C17 C68 IC4 C58 C59 C63 J7

J9

L5

C66

C67

L2 TR4 TR5 FOS2

IC1

C60

A1

J2

C26 C20

R28 R20 C72

IC5

C62

12

A2

J3 C61

10

S50.115.1 .CELE.TOB

10

11 SOLO PER SINTESI DI TENSIONE SOLO PER SINTESI DI FREQUENZA SOLO PER MONO SOLO PER MONO BG

12 SOLO PER MONO BG/L L" SOLO PER STEREO SOLO PER DOPPIA SCART SOLO CON SINGOLA SCART

H
R102 15K

+5V
D100 1N4148 Status AV1 R138 15K R137 15K

J115

H
J113

+5V

EX.R. OUT

AM/FM IN

L. AP OUT

SW TV/AV

INTER.

+12V

+26V

C112 100n

IF1

6 SC1/SC2
PWM

+6V

R103 10K Status AV2

SDA

SCL

SWITCH

R140 5K6

A8

GND

+12V

GND

GND

R142 15K D101 1N4148 R143 10K

R SC in

L SC in

7 SC1 to SC2

R.SC OUT

L.SC OUT

R141 5K6

R183 10K

R. AP OUT

EX.L. OUT

COPY

+12V

STEREO NICAM
7

21
C259 10 16V R258 560 AV RIGHT IN LEFT IN

8 2 6 20 5 9 13 17 18 14 10 12

A13-C

A13-D

A13-H

A13-G

ADC 100n

R133R132 12K 12K

J116

A13-I

A13-J

+5V

10

A13-A

A13-B

A13-E

A13-F

10

+5V
R139 15K R168 47K PORT 3 R169 100K

10

12

5 J30 J38

11

+12V +12V
R273 47K TR211 BC848 C249 10 16V C279 100n

C261

10 16V R244 150

J25

R257 560

+12VC113
R185 10K

+5V
R177 15K R179 47K R184 100K Status PIP JS105 Status Cuffia 3 SYS

8 SWITCH CINCH/SC

TR110 BC848 C496 22 100V

J145 9 8 7 6 5 4 J91
IC400 TDA1521A TDA2613 C495 1n R424 82 R425 82 C404 1n JS450 C400 100n C405 1n L481 47H

+12V

JS13

J53 J31

J29

J33

+12V

VIDEO IN

J8
C274 C275 1n 1n R248 100

C484 22 100V

TR111 BC 548B

12
SWITCH L/L"

R166 15K

C454 1n

A400-B

+5V +5V

R167 15K R146 15K JS102 0

30

3
PORT 2

J142

C401 220 25V

J138 1 8 7 2 3 4 5

J101 4 CTI
Status

J114
JS104 0

R174 15K R128

J52

11

+5V
J87 J90

J102
R450 8,2 R402 8,2

+27,8V

C451 2200 35V

R491 82 JS490 R490 82 JS451

J139 J140
L480 47H

+5V
TR103 BC848 R150 270 R190 330

5
BLUE

Status Formato JS100 DSC 0

2
R157 1K

+5V
R172 2K7 GREEN C506 100 R509 5K6 R508 1K2 TR500 BC 550C

X13

C482 C481 C483 2200 2200 68n 35V 35V

R131 15K

C413 22n C406 1n C407 1n

A400-C

+5V
TR102 BC848 R186 270

33

1 Tuning
D I S P L A Y

Voltage

R507 220K

+5V F
TR101 BC848 R187 270 R188 330

R189 330

R158 1K

CORB

29

RED

34

+5V
R165 15K

+12V
R161 10K TR107 BC848 ADD SCL SDA +33V AGC +5V +5V IF2

R162 1K

15 SW TV/AV

R159 47K R160 100K

D103 1N4148 R173 1K

R163 0

BLNK

35

TEXT INTERFACE

+5V
R503 4K7

UHF TR501 BC858

VHIGH VLOW

TUN

AGC

+5V

+5V

IF2

5
C501 330n C500 100n

2
R502 33K R501 12K

14 UHF
PAGE RAM

J108 J111 J86 J107

R505 2K2

J35

R192 680

20
TELETEXT ACQUISITION

VHF-H

+5V
R512 4K7

J122 J63
R119 820 H 2Vpp

H 2,5Vpp C111 100n C110 100n R114 24K CVBS0 CVBS1

23 24 26 25 36
DATA SLICER ACQUISITION TIMING

21 VHF-L

TR503 BC858

C503 100n

C550 100n

C551 470 10V

X7 +5V

+5V
R267

R513 R123 R121 R122 2K2

J5

+5V
C109 100n D102 1N4148

I ref S.FILTER H.Sync

X5
PORT 0

15K

15K

15K

+5VSTBY
1 2 3 4 5 6 7
R504 KEY1-A ANAKEY1-B SEL KEY1-C ANA+ KEY1-D PKEY1-E P+ R115 1K 2K2

+5V
R511 4K7

TR502 BC858

C504 100n C502 330N C505 100n

JS502 C231 47 16V

R223 2K7 R261 18K

12K D104 1N4148

R506 10K R309

J3 J20

R145 22K

J148
R144 22K

18 KEY2 J126

R118 100

R551 100

R552 100

4K7 GND C267 D203 10 ZTK 100V 33B R202 100 R203 100 SCL SDA

+5V
R107 1K D108 1N4148 H 5,6Vpp

FRAME

27

DISPLAY TIMING

17 KEY1 J125 16 KEY0 J124

R117 100 R116 100

V.Sync

37

J133
X out X in

42 41 40
I2C OSCILLATOR

8 9 10

J14

J16
H 1,4Vpp SAT H 1Vpp H 1,4Vpp Y in

V 5Vpp +3V3 R105 1 D105 ZPD 2V4 R176 10K R178 R191 4K7 10K D106 1N4148 TR108 BC 548B

QZ100 12MHZ C103 18 C102 18 C101 470n D107 1N4148

X gnd

19 ON/OFF
R171 R170 5K6 5K6

J120 J121 J123 J127VDDP

RESET

+5V
R154 15K

44 43
80C51 MICROCONTROLLER DATA ADDRESS

+5VSTBY
50 49 52
MSDA MSCL SW 16/9 R100 R101 R153 100 100 100

J99

J76

D
+3V3 R106 1 C104 100 10V +3V3 R113 1 C106 100 10V C105 100n

VSSP VDDC

38 39

ROM 16K TO 128K

+5V
R164 15K

+12V
R156 10K R147 47K TR105 BC 548B

J97 J98

1 2 3 4 5 6

45
SRAM 256 Bytes

SW AM/FM INTO

47
PORT 1

J117J136
R104 4K7

IR Vcc GND

IRR100 R155 100K

+8V5 +12V

PIP A7
+8V
J54

VDDA C150 100n

31
DRAM 3K TO 28K

+5VSTBY
+5V COL.AUT.

+12V
R181 10K

J135 J149

LED1

+5VSTBY
R151 470

51 SW.XTAL

D109 1N4148 R126 5K6 R127 5K6

J137

R182 12K

R148 47K TR109 BC 548B

+5VSTBY
R39 1K R40 560 TR7 BC 547B D5 ZPD 2V7 TR8 BC 547B

VSSC VPE VSSA

13 28 22

46 48

SCL1 SDA1

+5VSTBY
C100 68n

R180 100K

A5
+5VSTBY
5 4 3 2 1

+3V3

C107 100 10V

IC100 SAA5553M3

TIMER/ Ctrs

8 7 6 5
A14-A A14-B

1 2 3 4

J119
R152 0 R175 15K

ONLY FOR AUTOMATIC TESTING

V 1,8Vpp

+5VSTBY

~
230V

IC101 ST24C04CB C229 1n C228 1n

A1
TASTO1

3 2 1

C6 C7 2n2 150 400V 400V

MOUNTED JS1 OR JS6

R30 R31 330K 330K R2 68K H 500Vpp D7 BYV95C C12 33n 630V T1

15

2 4

JS1 JS6

+148V +128V
D10 BYV95C

D9 BYV95C C19 100n 250V C20 100 250V

+148V/128V
J93

A6
FUS1 T2AH 250V L2 47MH C9 680N 400V L1 47MH

L4

R16

C18 330 500V

+28V STBY +27,8V

J88 J79

X2

1 2

3
C2 4n7 500V D1 1N4007 C3 4n7 500V D2 1N4007 R1 150K

R3 4K7 R33 4,7

0,1 C21 330 500V R17 0,1 D11 BYV95C

H 10Vpp R4 47

TR1 STH7N90FI D6 1N4148 C10 220n L5 R5 4,7 R6 47 R7

C14 470 2000V

C24 100n

C25 2200 35V IC10

R19 4K7

R20 4K7

TR4 TIP 115 IC202 L78M08CS

10 11 8

R25 2K2 TDA 8138 TR3 BC848

1 2 3

L3

J48 J74
C241 1000 10V

+8V
J82
D20 R51 C62 6n8 1N4148 TR11 BC858

BV53-117 2*47MH

D3 C4 4n7 500V

D4 C5 4n7 500V

C8 47 D13 25V BA157

1N4007 1N4007

10K

R24 2K2 C26 100n C28 1000 16V

R23 10K

X8

H 1Vpp D8 1N4148

A2

C23

1
C1 10n 250V PTC1

R8 390K R9 560K R12 820

R32 100K R13 3K9

9
R15 4M7

330 500V

3 2

1 J131 J132
C27 1000 10V TR6 BC 638

2 3
16V

3K3

R66 10K C54 22n

D23 BA 157 C66 4n7

R80 47

V 5Vpp

C51 2200 25V

J66

+12V
4 2
TR15 BC 639 R67 82K TR207 BC 338-40 H 40Vpp

LIVE AREA COMPONENTI SOTTO RETE

A Non inserire con modulo zero power Solo con modulo zero power

R14 2K2 C16 1 63V

D12 BYW95A C17 2n2 400V

JS10 R26 4K7 R28 220 TR5 BC 548B JS11

X3
R29 4K7

X4 +5VSTBY

4 5 6
C59 100 25V C56 10n R68 390 C82 100 25V

J1 J59 J70 J104

H 12Vpp C68 10n D24 BY228

C72 1 350V

D26 BA 157

J26

A600-A

16

J68 10 250V
R84 39

10 1 7
C77 150n

A3

1
1

A600-B

DEGAUSS

X1

5 4

IC1 TDA 4605

6 3

8 1
C32 100 C15 4n7

12
R18 0,1 C22 330 500V C30 1000 25V

A12

J12 J55 J96 J105 J106

+12V
J134 1

J92 J94

R10 C11 4K7 4n7

R11 220

C29 1000 16V

J103
R27 1K TR2 BC 548B

C31 1000 10V

J112 J128

+5V X14X6

R21 R22 47K 47K

+8V5

32

15K

+5V +5V

C450 22n

J100 C402 2200

35V

L400 47MH

4 3

A400-D

J118

+5V

L401 47MH

+12V
R291 47 R297 100 L207 1H TR213 BF 959

+12V
R298 4K7 D205 C285 1n TR214 BF 959 R294 47 BA 682 D206 BA 682

+12V
R299 2K7

+12V
R300 2K7

+12V

+8V5
J89
C290 330n IC203 L7806CV

C289 100n

J22 2

R272 560 R314 560 R274 12K

JS7

C245 10 16V

C246 10 16V

IC201 LA7955

C280 100n

R271 150 C248 10 16V

+12V
R277 47K R278 12K

1 2

A400-A

LEFT

J62

4 1 3 7 19 18 17 12 13

5 9

1 A15-A 2 A15-B
TR212 BC848 R233 47 R256 LEFT OUT R279 330 560 R255 C254 10 16V C273 1n 560 RIGHT OUT VIDEO OUT

C283 C282 100 100n 16V C281 1n

R290 2K7

1 2
R310 47K

F204 L9454M

J75

4 5

16 1

15 2

14 3

R296 1K

IC102 TDA 9830

13

12

11 6

10 7

9 8

J146
R288 150

C247 R287 10 100 16V C256 10 16V

20 16 11 15 2
C278 100N C255 10 16V

19 3 4 1

H1

R293 150

3
TR218 BC848

+12V
R306 1K5 C286 C287 47 47 16V 16V R308 4K7 C288 330n C291 10 16V R307 1K TR217 BC 548B JS201 JS202 JS525

J24
JS526 R286 120

C272 1n

R312 2K7 C295 100n

J72

J9
C257 10 16V

14 10 6

J2 J4
R304 47K R531 4K7 R285 120

RIGHT

R289 1K

R292 120

R295 C284 120 1n R311

+12V
C250 1000 16V C299 10 16V C298 10 16V

SC2

+12V

+27,8V
C575 220 25V R575 4K7 R576 4K7

8K2

TR219 BC848 R313 100K C296 100n

J45

+12VTR215 J21
R302 47K BC 548B TR216 BC 548B

R235 C251 1K5 100N JS9 JS8

J95 J47

1,5Vpp AUDIO out

R305 1K

C292 10 16V R303 47K

R530 4K7 C265 100 16V

+12V
R525 47 R526 330

J13 J15

+12V
R262 47K

J6

TR575 BC848

15
AFC

VOL.

0,5Vpp C577 1

R301 18K

IC200 HEF4053
10 15 2 1
IC200-B

J17

PLL
IF1

R577 4K7 R200 PLL IF

S.T.

5 4 3

SWITCH + VOLUME

SW.

EXT.S.in

J19

JS203

J27 J23

C240 10 16V C263 1n CH3 AUDIO RIGHT IN

IF1 L201 BV53 -106 1H F203 K3953 JS500

C214 100n

390

AFC

TR525 BC848 R528 100 R264 47K

+12V
R263 47K R265 47K

11 14 9 4

55
SOUND MUTE SOUND PRE AMP +MUTE

De Emph. C264 3n3 S.DEC C233 10 16V F575 C237 100 TR209 BC 548B

R527 1K

12 13
IC200-A

C239 10 16V

10 11
JS501 R510 390

1 2 3 J144 J44

5 4

IF IF

49 48
VIDEO IF AMPLIFIER + PLL DEMOD.

56

J32 5 3

C293 1n

CH2 AUDIO LEFT IN

J28

R240 100K C277 R269 100n 47K R209 390 R227 1K

ADJ.

PLL FM DEMOD.

14

GND

J49
R239 R241 10K 560 R242 680 C236 100

+8V
J40
R208 330

+12V
C244 100n

16

IC200-C IC200-D

R224 680 C232 1 16V C242 100n C230 22 16V

Tuner AGC IF AGC

54 53
AGC FOR IF + TUNER TOP POL VIDEO MUTE VIDEO AMPLIFIER VIDEO MUTE

LIMITER

1 SIF

C576 68 R578 390

F576

+8V
TR203 BC 548B R229 1K

6 7 J10

8
C216 47n

Bandgap C203 100N

TR210 BC848 C206 22 16V H 2,5Vpp R201 1K R259 2K7

+8V

L206 3,3H

F201 4,5-6,5

J41

J109

R268 75

CH1 VIDEO IN

R212 75 C235 10 16V TR200 BC848 R206 1K L205 6,8H TR201 BC858

F200 5,5

+12V
R231 75 R228 1K C238 1000 16V

J110

21

E
18
H 2,5Vpp R230 47 AV VIDEO OUT RIGHT OUT RIGHT IN LEFT OUT LEFT IN VIDEO IN

44

+8V
J42

CONTROL DAC 1x8 BITs 14x6 BITs 1x4 BITs

VIDEO out

TR204 BC848 R232 1K

8 19 1 2 3 6 20 4 5 9 13 14 17 15 11 7 16

12 Supply 7 8
I2C BUS TRANSCEIVER IDENT C207 100n

J43

C213

+8V
H 1Vpp R205 330

TR202 BC848 C201 18 C208 47n R214 75 R213 150

J39

C294 C258 C297 C260

10 16V 10 16V 10 16V 10 16V

R252 560 R254 560 R251 560

13
VIDEO IDENT CVBS SWITCH

CVBS int CVBS1 out CVBS input

1000 10V

R210 1K

38 17

C300 82 C204 100n

J61

J7

R253 560

27 31 32 28 30 29
CD MATRIX SAT CONTROL BLUE STRETCH SKIN TINT CORR LUMA DELAY PEAKING CORING SW CVBS -Y/C SWITCH

11 SVHS-Y

J18
C268 1n R282 220 R283 220 C269 1n R249 100 C270 C271 1n 1n RED IN GREEN IN BLUE IN D201 BAT 81 BLNK

+8V

J141
TR220 BC848 R260 330

JS4

B-Y in R-Y in Y out JS2 R-Y out B-Y out

10 23
BLACK STRETCH RGB MATRIX RGB1 INPUT

SVHS-C Rin Gin Bin FBlank

C212 C209 C210

2n2 22n 22n

J34

R G B FB
J78 J60

24 25 26

+5V
J77 12 11 10 9 8

+12V
J64 7 6 5

JS3

C211 22n

R284 220

C243 C262 470 470

BASE BAND REF DELAY LINE

R219 4,7 C223 C222 100n 100 10V TR208 BC 548B

CTI - 16:9
R236 470K R226 470K TR206 BFS 19 R225 470K QZ202 3,58205 C220 100n

A10
C221 3N3 R207 100K C215 220n VCC Colour PLL Chroma Ref SecPllDec XTAL 4,43 -3,58 XTAL 3,57 QZ200 3,57954 MHZ C252 100n V 3Vpp R270 39K 2% Vsawtooth V Iref VdriveA VdriveB R276 100K R280 10K

CHROMA TRAP + BANDPASS C253 1000 16V D200 ZPD 8V2

+12V
J50
TO RGB

R245 100 1 2 3 4 5 6 IC600 STV 5112

R246 100

R247 100

R250 75

SC1

37 36 33 16 35 34
HUE PAL/NTSC SECAM DECODER REF

1 2 3 4 5 6

FILTER TUNING

BLACKCURRENT STABILISER

18 19

BL.Curr.

R281 10K C276 100

12 11 4 3 5

2 8

7 6 9 10 1

Blue Green

R215 100 R216 100 R217 100

PIP

A11

R238 47K C218 22n

RGB CONTROL WHITE P . SYNC SEP . + 1st LOOP CONTR.BRIG. VCO + CONTROL + OUTPUT

R237 47K

20 21

J36 J65

QZ201 4,43 JS200

C205 C219 18

18

TS
11 12 13 14 15
H 100Vpp

Red

R211 47K C217 TR205 22n BFS 19

A9
C602 22 H 2Vpp H 2Vpp H 2Vpp RED 6 H 70Vpp R243 4K7 C266 22 100V D202 BA 157 BLUE GND R34 12K 4 3 GREEN 5

10

J51

22

Beam Current

51 52 47 46 50
VERT. SYNC SEPARATOR VERTICAL GEOMETRY H/V DIVIDER

6
A601-F R601 680 C603 82

R613 68K R614 R602 680 C604 27 R615 R603 680 R604 1K C615 100 D607 ZPD 9V1 R629 82 C601 C600 100n 47 16V D610 BAV103 D609 BAV103 R610 C611 1K 220 R611 C612 1K 220 D603 1N4148 R605 1K R606 1K D600 1N4148 D601 1N4148 D611 BAV103 R612 C613 1K 220 D604 1N4148 R618 1K8 R620 120K R619 100 TR600 BF 422 C606 22 250V R624 1M R625 18K C609 10 100V C607 22 250V D608 1N4004 C608 100n 250V R621 10M R626 1K8 C610 2n2 1KV X12 D605 1N4148 R616 C614 2n2 1KV 68K D602 1N4148 H 100Vpp 68K H 100Vpp

C234 2n2

J46

A601-E

+8V +8V

J37

EHT R275 33K AvlCap EW-drive R221 100

43

Phi-1

R220 15K R43 D21 R37 47K R59 39K C50 47n C224 100n R88 C81 680n C80 10 100V BA 157 JS12 D28 BA 157

J73
R36 47K 10K

4 3 2 1

A601-D A601-C

45 42

EWGEOMETRY

C227 4n7

J84
C60 68

C225 2n2

Phi-2

C226 1 16V

CUT OFF 2 +12V 1

R600 1K

R628

100

R38 47K 200V

A601-B

R54

Sand. H. out

41 40

2nd LOOP + HOR. OUT

39

Digi DEC

+8V
R65 1K

27K H 8Vpp

IC204 TDA 8844

1 2

A4

A601-A

1 2 3

R87 0,39

6V3

H 27Vpp

R617

1K8

11 6 8 10 9

B G R

0,1

1K8

110
5 7 1

11

EAT

D606 1N4148 R622 560

+8V

H 120Vpp 68n

C53

J147
+8V

J83

R93 4K7 C78 150n 100V T2 R92 22K

R91 150K

R90 150K R81 1K2 L22 BV52-105 BV52-109 C79 100n 400V C73 1 250V L24 BV53 -120 C74 D27 BA 157 L23 100H

12 3
G2 FOC

J71

+8V
R71 2K2

D53 1N4148 D50 1N4148 D204 1N4148

+28V STBY
R75 56 C65 470 35V

33K R50

R76 R77 R94 820 820 820

R79 1,5

L21 5,6 H BV53-130

1 3

TR16 BU 508D

R82 15K

R83 15K

R623 560

C605 100n 250V

EAT R627 470K X10 G2 FOC

2
2

A600-C

R56 1,8

V 11Vpp R73 47K

J85 R60
220 C67 22 100V R61 D22 R78 10K BA 157 10K

H 1200Vpp C70 C71 2n2 1 1,6KV 100V

+148V/128V
2

C75 5n6 400V C76 680n 250V

R64 0,1

8
R89 0,1

6
R86 0,1

V 12Vpp R70 0,1 L20

1,5KV

7 8 9
IC5 TDA 8351

A3
L26 1,2mH

R85 10 5W

C55 C52 220n 470 50V R53 270

R57 4,7

A3
VERT. YOKE

H 8Vpp

R266 220

110MH 3
C69 22n 400V D25 BA 157

J69

J57
R69 82K V 1Vpp TR12 BUK474 200A C61 100n 250V

J67

5
D52 BA 157 T3 R35 12K

3
C58 22n

R58 22 C57 220n V 45Vpp

J56 J130

L25 610H

* *
D51 BA 157

* MOUNTED L25 OR L26

H 60Vpp

Industrie Formenti Italia s.p.a.

H 150Vpp

A3
4

R55 0,1

Stabilimento di Sessa Aurunca (CE) Descr. Data: Scala: Disegnato:

R42 R41

75 75

TELAIO BASE F19 12/09/2000 Cod. Schema:

Sost.schema:

497.07B 497.06B

DI MAIO

Approvato:

10

11

12

P+ ANA+ KEY1 SEL L400 JP1 C263 R151 D109 GND R268 R104 R123 JS451 C407 C406 +5V STBY C405 L401 H1 FUS1 X5 R121 C404 CH3 ROSSO RIGHT IN CH2 BIANCO LEFT IN CH1 GIALLO VIDEO IN R122 C293 LED1 C216 IRR100 K3

P-

ANA-

T2AH
A1 230Vac
TASTO1 D4 C5

A400

R490

JS450

L481

L480

J140

J139

J138

GND

J135 J149

R491

JS490

J137 J136

R424

R425

R118 R117 R116

TR6 X2 X1

TR5

TR7 J126 J125 J124 D5 D2 J128 C106 JS10 C451 R113 D108
2,5Vpp

GND +5V X6 R2
1Vpp

J127 R114 X3 C3 JS11 PTC1 R13 IC1 R9 R8 R14 R12 D8 R21 IC10 R10 C16 C15 R1 D13 C10 C8 R11 C11 R7 R32 J143 C32 R26 X8 C28 J120 TR2 C240 R6 R15 C12 +12V C27 C1 DEGAUSS R30 R31 C2

R167 +5V

GND D107 C101 D105 A14 J113 C239 R24 C29 TR1 R4 R33 J115 L4 T1 R5 J116 L5 D6 D106 QZ100 J117
500Vpp

J121 TR111

R106 GND R159 R142 R102

C104

SCL SDA

IC101

X13 J112 DSC +5V

J101 J102 J100

R152 J145 C502 C267 C266 J95 J88 C56 TR4 IC5 C55 R56 D11 J70 GND R58 R57 J85 J84 J83 J82 J79 R50 C57 J71 C30 J67 GND GND C21 C22 C59 C82 JS12 C80 C61 C81 D21 D20 J57 R53
1Vpp

GND R181 J96 +12V +8V5 R243 D202 C575 J90 R18 R17 R16 J93 R20 J92 GND JS6 R153 R19 JP3 J94 GND D12

GND

D203

R25

C482 TR105 J103 +8V5

R156 +12V

R309 J106 +12V J105

C23

JS1

+128V

C25 D10

D9

C481

J98 J97 J89 J91 GND J86 J107 J108

+148V

C18

C14 C17 C20 C19 C24 C65 C76

A5
TR109

R100 R101 TR500 GND X14 +5V J104 R3 J109

R147

A7

NVM

J110

GND

IC400

C401 J73 J69 J81

11Vpp 1,8Vpp

C484 GND

D53

A11

R276

JP4 C78 D28 D50 J68 J76 J87 R144 J60 R145 J59 GND R240 J48 J63 J65 JS13 J147 J75 J141 IC202 J64 +12V +12V GND J61 JP5

J74

C54

C496

C67 D22 4

R75 T2 1

K5

A13

J130

R94 R76

R77

A10

R266 D204 R71 C241 J49 J78 D201 J53 TR208 QZ200 GND J51 J47 D200 J50 J62 J54 +5V J52 +12V J66 R219 R311 C287 F204 GND C286 J44 C283 F203 J43 J45 GND C222 C208
1Vpp 8Vpp

R70 R92 R89 GND J46 L25 C238 L26

TR15

C66
45Vpp

A3
TR12 J56 C68 3 D25 C71 C72

C75 R84 D23

+8V5

R79

J55

TR207

A9
RGB
C253 C213 C226 F201 J42

QZ202 QZ201

F200 TR203

J41 J39

R91 D26 R90

2,5Vpp

C73

R83

R82

3 L20

C79 D24 J35 J40 R200 L206 GND J34 1 L21 R201 C235 J144 GND J36 L205 R55

IC102

TR214

C252
3Vpp

J31 GND J30 J72 C265 J24 GND L201 J20 J19 GND J38 C291 TR217 +12V TR215

C230

F576 IC204 F575

J32 J28 J27 R86 GND

150Vpp

C69 T3

L22
1200Vpp

R81

L207

J37 TR213

GND

C206

J22

C51

D52 C70

C233 R527 IC200 J18 C577

A8

2,5Vpp

J23 TR209 J17 C249

J25

TR16

R80

J26

12Vpp

J21 C292

C52

HEF4053

LA7955

R244

TR216 R224 JS502 J16 J14 GND IC203 D104 JP2 R504 R513 R505 +5V R501 J5 C551

C232
0,5Vpp

C298 JS7 C260 J12 C231 J10 GND R230 AGC C501 J3 GND J6 J4 J2 C247 +12V C250 C248 IC201 C256 J8

C254 C74 J9 C261 C299 GND C259 J7 SDA SCL C258 C255

R64

27Vpp

J146

SC1 TUNER

C297

C294

C257

J1

R233

A15

SC2
D27 L23
120Vpp

R87

R88

A4

60Vpp

K2

C246

00 01 02 03 04 05 GFMAMGLASOND
C245

C77

D51

L24

K1

J77 +5V
2,5Vpp

C50

40Vpp 12Vpp

3 C58

R85

C6

R105

10Vpp

LIVE AREA
D7

TR108 J118 D101 D100

IC100

C107 J119

5Vpp

MICROCONTROLLER

J122

A12

R190 D103 D1 +5V STBY C7

G2

R627

D3

R626

497.06B

R618

R188 R189

X10

DIS1

R616

TR8

CRT

X4 +5V STBY

C31

D602

C402

J131

D601

IC600

D603

5,6Vpp

C610

D102

D604

D600

C605

J134 J148 R614 L3

C614 R628

R
J132 C608 L2 L1

GND J133 +5V STBY C9

C609

A600
R624 R625 X12

TR600
R623

R622
R621

C607

R619
R620 D608

D607 R629 C600 C601

R606

D606

R600
C602 R601

A601
R603 C604 C603 R613 R602

C606
R604

497.07B

F19

R605 R615 D605 R617

A6

A2

C4

K4

B70.794