FinFET

History,FundamentalsandFuture
TsuJaeKingLiu
DepartmentofElectricalEngineeringandComputerSciences
UniversityofCalifornia,Berkeley,CA947201770USA
June11,2012
2012SymposiumonVLSITechnologyShortCourse
Source: ITU, Mark Lipacis, Morgan Stanley Research
http://www.morganstanley.com/institutional/techresearch/pdfs/2SETUP_12142009_RI.pdf
#

D
E
V
I
C
E
S

(
M
M
)
YEAR
Market
Growth
Investment
Transistor
Scaling
Higher Performance,
Lower Cost
ImpactofMooresLaw
CMOSgeneration:1um 180nm 32nm
2
0.25mCMOStechnologywasstateoftheart
DARPAAdvancedMicroelectronics(AME)ProgramBroad
AgencyAnnouncementfor25nmCMOStechnology
1999 2002 2005 2008 2011 2014 2017 2020
TechnologyNode 180
nm
130
nm
100
nm
70
nm
50
nm
35
nm
25
nm
18
nm
GateOxide
Thickness,T
OX
(nm)
1.92.5 1.51.9 1.01.5 0.81.2 0.60.8 0.50.6
DriveCurrent,I
DSAT
1998InternationalTechnologyRoadmapforSemiconductors(ITRS)
1996:TheCallfromDARPA
EndofRoadmap
Solutions
beingpursued
Noknown
solutions
3
UCBerkeleyprojectNovelFabrication,DeviceStructures,
andPhysicsof25nmFETsforTerabitScaleElectronics
June1997throughJuly2001
MOSFETFundamentals
Sisubstrate
Gate
Source Drain
GATELENGTH,L
g
GATEOXIDETHICKNESS,T
ox
0.25micronMOSFETXTEM
http://www.eetimes.com/design/automotivedesign/4003940/LCDdriverhighlyintegrated
MetalOxideSemiconductor
FieldEffectTransistor:
4
MOSFETOperation:GateControl
CurrentbetweenSourceandDrain
iscontrolledbytheGatevoltage.
gateoxide
P N+
Gate
N+
NchannelMOSFET
crosssection
Desired
characteristics:
HighONcurrent
LowOFFcurrent
ElectronEnergyBandProfile
i
n
c
r
e
a
s
i
n
g

E
distance
n(E) exp(E/kT)
Source
Drain
V
DD
I
ON
I
OFF
Inverseslopeis
subthreshold swing,S
[mV/dec]
log I
D
increasing
V
GS
V
TH
GATEVOLTAGE
0
D
R
A
I
N

C
U
R
R
E
N
T
L
eff
Nchannel&PchannelMOSFETs
operateinacomplementarymanner
CMOS=ComplementaryMOS
Source Drain Body
5
CMOSDevicesandCircuits
0 1
1 0
STATICMEMORY(SRAM)CELL
D S
G
D
S
G
CIRCUITSYMBOLS
Nchannel
MOSFET
Pchannel
MOSFET
GND
V
DD
S
S
D
D
CMOSINVERTERCIRCUIT
V
IN
V
OUT
V
OUT
V
IN
0
V
DD
V
DD
INVERTER
LOGICSYMBOL
BITLINE
WORDLINE
BITLINE
CMOSNANDGATE
NOTAND(NAND)
TRUTHTABLE
6
or or
logI
D
V
GS
V
DD
I
ON
ThegreaterthecapacitivecouplingbetweenGateandchannel,the
bettercontroltheGatehasoverthechannelpotential.
Body
Gate
Drain
C
ox
C
dep
higherI
ON
/I
OFF
forfixedV
DD
,orlowerV
DD
toachievetargetI
ON
/I
OFF
reduceddraininducedbarrierlowering(DIBL):
Source
Source
Drain increasing
V
DS
ox
total
C
C
S
logI
D
V
GS
increasing
V
DS
I
OFF
ImprovingtheON/OFFCurrentRatio
7
inv D
Q v W I =
DRAINVOLTAGE,V
DS
D
R
A
I
N

C
U
R
R
E
N
T
,

I
D
q
) (
TH GS ox inv
V V C Q
eff
v
Substrate
Gate
Source Drain
MOSFETinONState(V
GS
>V
TH
)
8
velocity inversionlayerchargedensity width
mobility
gateoverdrive
gateoxide
capacitance
M.H.Naetal.(IBM),IEDMTechnicalDigest,pp.121124,2002
NMOSDRAINVOLTAGE=V
OUT
V
IN
=V
DD
V
IN
=0.83V
DD
V
IN
=0.75V
DD
V
IN
=0.5V
DD
N
M
O
S

D
R
A
I
N

C
U
R
R
E
N
T
I
H
I
L
V
DD
0.5V
DD
I
DSAT
V
2
I
H
(DIBL=0)
I
EFF
=
I
H
+I
L
2
t
pHL
t
pLH
V
1
TIME
V
DD
V
DD
/2
V
1
V
2
V
3
CMOSinverterchain:
GND
V
DD
S
S
D
D
V
IN
V
OUT
V
3
EffectiveDriveCurrent(I
EFF
)
9
CMOSTechnologyScaling
Gatelengthhasnotscaledproportionatelywithdevice
pitch(0.7xpergeneration)inrecentgenerations.
Transistorperformancehasbeenboostedbyothermeans.
90nmnode 65nmnode 45nmnode 32nmnode
T.Ghani etal.,
IEDM 2003
K.Mistry etal.,
IEDM 2007
P.Packan etal.,
IEDM 2009
XTEMimageswiththesamescale
courtesyV.Moroz (Synopsys,Inc.)
(afterS.Tyagi etal.,IEDM 2005)
10
P.Packan etal.(Intel),IEDMTechnicalDigest,pp.659662,2009
Strainedchannelregions
eff
|
Highkgatedielectricandmetalgateelectrodes C
ox
|
CrosssectionalTEMviewsofIntels32nmCMOSdevices
MOSFETPerformanceBoosters
11
A.Asenov,Symp.VLSITech.Dig.,p.86,2007
ProcessInducedVariations
Subwavelengthlithography:
Resolutionenhancement
techniquesarecostlyandincrease
processsensitivity
SiO
2
Gate
Source Drain
A.Brownetal.,
IEEETrans.
Nanotechnology,
p.195,2002
Randomdopant fluctuations(RDF):
Atomisticeffectsbecome
significantinnanoscale FETs
courtesyMikeRieger (Synopsys,Inc.)
12
Gatelineedgeroughness:
photoresist
AJourneyBackthroughTime
WhyNewTransistorStructures?
Offstateleakage(I
OFF
)mustbesuppressedasL
g
isscaleddown
allowsforreductionsinV
TH
andhenceV
DD
Leakageoccursintheregionawayfromthechannelsurface
Letsgetridofit!
Drain Source
Gate
L
g
UltraThinBody
MOSFET:
BuriedOxide
Source Drain
Gate
Substrate
Siliconon
Insulator(SOI)
Wafer
14
ThinBody MOSFETs
I
OFF
issuppressedbyusinganadequatelythinbodyregion.
Bodydopingcanbeeliminated
higherdrivecurrentduetohighercarriermobility
Reducedimpactofrandomdopantfluctuations(RDF)
UltraThinBody(UTB)
BuriedOxide
Substrate
Source Drain
Gate
T
Si
L
g
T
Si
<(1/4) L
g
DoubleGate(DG)
Gate
Source Drain
Gate
T
Si
T
Si
<(2/3) L
g
15 R.H.Yanetal.,IEEETED1992 B.Yuetal.,ISDRS1997
EffectofT
Si
onLeakage
I
off
=19A/m I
off
=2.1nA/m
LeakageCurrent
Density[A/cm
2
]
@V
DS
=0.7V
10
6
10
1
3x10
2
0.0
4.0
8.0
12.0
16.0
20.0
G
G
S D
G
G
S D
SiThickness[nm]
L
g
=25nm;T
ox,eq
=12
T
Si
=10nm T
Si
=20nm
16
DoubleGateMOSFETStructures
L.Geppert,IEEESpectrum,October2002 17
PLANAR:
VERTICAL FIN:
DELTAMOSFET
D.Hisamoto,T.Kaga,Y.Kawamoto,andE.Takeda(HitachiCentralResearchLaboratory),
Afullydepletedleanchanneltransistor(DELTA) anovelverticalultrathinSOIMOSFET,
IEEEElectronDeviceLetters Vol.11,pp.3639,1990
W
l
=0.4m
Improvedgatecontrol
observedforW
g
<0.3m
L
eff
=0.57m
18
DoubleGateFinFET
Selfalignedgatesstraddlenarrowsiliconfin
Currentflowsparalleltowafersurface
S
o
u
r
c
e
D
r
a
i
n
Gate 2
Fin Width, W
fin
Fin Height, H
fin
Gate Length, L
g
Current
Flow
Gate 1
G
G
S
D
19
1998:FirstNchannelFinFETs
D.Hisamoto,W.C.Lee,J.Kedzierski,E.Anderson,H.Takeuchi,K.Asano,T.J.King,J.Bokor,andC.Hu,
AfoldedchannelMOSFETfordeepsubtenthmicronera,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.10321034,1998
DeviceswithL
g
downto17nm
weresuccessfullyfabricated
L
g
=30nm
W
fin
=20nm
H
fin
=50nm
L
g
=30nm
W
fin
=20nm
H
fin
=50nm
PlanView
20
1999:FirstPchannelFinFETs
X.Huang,W.C.Lee,C.Kuo,D.Hisamoto,L.Chang,J.Kedzierski,E.Anderson,H.Takeuchi,Y.K.Choi,
K.Asano,V.Subramanian,T.J.King,J.Bokor,andC.Hu,Sub50nmFinFET:PMOS,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.6770,1999
L
g
=18nm
W
fin
=15nm
H
fin
=50nm
Transmission
Electron
Micrograph
21
2000:VestedInterestfromIndustry
SemiconductorResearchCorporation(SRC)& AMDfundproject:
DevelopmentofaFinFET processflowcompatiblewitha
conventionalplanarCMOSprocess
DemonstrationofthecompatibilityoftheFinFET structure
withaproductionenvironment
(October2000throughSeptember2003)
DARPA/SRCFocusCenterResearchProgramfundsprojects:
ApproachesforenhancingFinFET performance
(MSDCenter,April2001throughAugust2003)
FinFETbasedcircuitdesign
(C2S2Center,August2003throughJuly2006)
22
FinFETStructures
Source
Drain
Gate
Si Fin
Drain Source
Gate
Original:
Gatelast
processflow
23
Improved:
Gatefirst
processflow
FinWidthRequirement
Toadequately
suppressDIBL,
L
g
/W
fin
>1.5
Challengefor
lithography!
N.Lindert etal.(UCBerkeley),IEEEElectronDeviceLetters,Vol.22,pp.487489,2001 24
MeasuredFinFET DIBL
SubLithographicFinPatterning
BOX
SOI
1. Deposit & pattern sacrificial layer
BOX
SOI
2. Deposit mask layer (SiO
2
or Si
3
N
4
)
BOX
SOI
3. Etch back mask layer
to form spacers
BOX
fins
4. Remove sacrificial layer;
etch SOI layer to form fins
Note that fin pitch is 1/2 that of patterned layer
SpacerLithography
a.k.a.SidewallImageTransfer(SIT)andSelfAlignedDoublePatterning(SADP)
25
Y.K.Choietal.(UCBerkeley),IEEETrans.ElectronDevices,Vol.49, pp.436441,2002
BenefitsofSpacerLithography
Spacerlitho.providesforbetterCDcontrolanduniformfinwidth
SEMimageof
FinFET with
spacerdefinedfins:
26
SpacerDefinedFinFETs
Y.K.Choi,N.Lindert,P.Xuan,S.Tang,D.Ha,E.Anderson,T.J.King,J.Bokor,andC.Hu,
"Sub20nmCMOSFinFET technologies,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.421424,2001
27
TransferCharacteristics OutputCharacteristics
L
g
=60nm,W
fin
=40nm
2001:15nmFinFETs
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
N-body=
2x10
18
cm
-3
P+Si
0.4
Ge
0.6
Gate
NMOS
PMOS
V
d
=-0.05 V
V
d
=-1.0 V
V
d
=0.05 V
V
d
=1.0 V

D
r
a
i
n

C
u
r
r
e
n
t
,

I
d

[
A
/
u
m
]
Gate Voltage, V
g
[V]
-1.5 -1.0 -0.5 0.0 0.5 1.0 1.5
0
100
200
300
400
500
600
0
100
200
300
400
500
600
Voltage step
: 0.2V
|V
g
-V
t
|=1.2V
NMOS
PMOS


D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
[
u
A
/
u
m
]
Drain Voltage, V
d
[V]
W
fin
=10nm;T
ox
=2.1nm
TransferCharacteristics OutputCharacteristics
Y.K.Choi,N.Lindert,P.Xuan,S.Tang,D.Ha,E.Anderson,T.J.King,J.Bokor,C.Hu,
"Sub20nmCMOSFinFET technologies,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.421424,2001
28
2002:10nmFinFETs
B.Yu,L.Chang,S.Ahmed,H.Wang,S.Bell,C.Y.Yang,C.Tabery,
C.Hu,T.J.King,J.Bokor,M.R.Lin,andD.Kyser,
"FinFET scalingto10nmgatelength,"
InternationalElectronDevicesMeetingTechnicalDigest,pp.251254,2002
SEM
image:
Thesedeviceswere
fabricatedatAMD,using
opticallithography.
TEMimages
29
OutputCharacteristics
HoleMobilityComparison
0
20
40
60
80
100
120
140
160
0 0.5 1
Effecti ve Fi el d (MV/cm)
M
o
b
i
l
i
t
y
(
c
m
2
/
V
-
s
e
c
)
Vg-Vth=.8V
<100> channel
FinFET
Bulk FET
DGFEThashigherhole
mobilityduetolower
transverseelectricfield
Forthesamegate
overdrive,holemobility
inDGFinFET is2 thatin
acontrolbulkFET
30
MeasuredFieldEffectHoleMobility
FinFET ProcessRefinements
Y.K.Choi,L.Chang,P.Ranade,J.Lee,D.Ha,S.Balasubramanian,A.Agarwal,T.J.King,andJ.Bokor,
"FinFET processrefinementsforimprovedmobilityandgateworkfunctionengineering,"
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.259262,2002
31
Finsidewallsmootheningfor
improvedcarriermobilities
Gateworkfunctiontuning
forV
TH
adjustment
FinFETReliability
Narrowerfinimproved
hotcarrier(HC) immunity
HClifetimeandoxideQ
BD
arealsoimprovedby
smootheningtheSifin
sidewallsurfaces(byH
2
annealing)
10
0
10
1
10
2
10
3
-30
-20
-10
0
10
20
30
L
g
=80nm
A
V
T

/

V
T

[
%
]


A
I
d

/

I
d

[
%
]
Stress Time [sec]
W
fin
=18nm W
fin
=26nm
W
fin
=34nm W
fin
=42nm
StressBiasCondition:V
g
=V
d
=2.0V
Y.K.Choi,D.Ha,J.Bokor,andT.J.King,ReliabilitystudyofCMOSFinFETs,
IEEEInternationalElectronDevicesMeetingTechnicalDigest,pp.177180,2003
32
TriGateFET
B.Doyleetal.(Intel),IEEEElectronDeviceLetters,Vol.24,pp.263265,2003 33
L
g
=60nm
W
fin
=55nm
H
fin
=36nm
SOIMultiGateMOSFETDesigns
afterYangandFossum,IEEETrans.ElectronDevices,Vol.52,pp.11591164,2005
H
S
i
/

L
e
f
f
W
Si
/L
eff
bodydimensions
requiredfor
DIBL=100mV/V
UTBFET
UltrathinSOI
H
Si
~L
g
/5
FinFET
Narrowfin
W
Si
~L
g
/2
TriGateFET
Relaxedfindimensions
W
Si
>L
g
/2;H
Si
>L
g
/5
T
ox
=1.1nm
34
DoubleGatevs.TriGateFET
TheDoubleGateFETdoesnotrequireahighlyselective
gateetch,duetotheprotectivedielectrichardmask.
Additionalgatefringingcapacitanceislessofanissuefor
theTriGateFET,sincethetopfinsurfacecontributesto
currentconductionintheONstate.
DoubleGateFET TriGateFET
channel
35 afterM.Khare,2010IEDMShortCourse
ThegateelectrodesofadoublegateFETcanbeisolated
byamaskedetch,toallowforseparatebiasing.
Onegateisusedforswitching.
TheothergateisusedforV
TH
control.
IndependentGateOperation
Source
Drain
Back
Gated
FET
Gate1
Gate2
36
L.Mathewetal.(Freescale Semiconductor),
2004 IEEEInternationalSOIConference
D.M.Friedetal.(CornellU.),
IEEEElectronDeviceLetters,
Vol.25,pp.199201,2004
BulkFinFET
C.H.Leeetal. (Samsung),SymposiumonVLSITechnologyDigest, pp.130131,2004
FinFETs canbemade
onbulkSiwafers
lowercost
improvedthermal
conduction
withsupersteep
retrogradewell
(SSRW)orpunch
throughstopperat
thebaseofthefins
90nmL
g
FinFETs
demonstrated
W
fin
=80nm
H
fin
=100nm
DIBL=25mV
37
Bulkvs. SOIFinFET
H.Bu (IBM),2011IEEEInternationalSOIConference
(comparedtoSOIFinFET)
38
2004:Highk/MetalGateFinFET
D.Ha,H.Takeuchi,Y.K.Choi,T.J.King,W.Bai,
D.L.Kwong,A.Agarwal,andM.Ameen,
MolybdenumgateHfO
2
CMOSFinFET technology,
IEEEInternationalElectronDevicesMeetingTechnical
Digest,pp.643646,2004
39
I
DSAT
BoostwithEmbeddedSiGe S/D
25%improvementinI
DSAT
isachievedwithsilicon
germaniumsource/drain,
dueinpart toreduced
parasiticresistance
Processflow:
P.Verheyen etal.(IMEC),SymposiumonVLSITechnologyDigest,pp.194195,2005
I
OFF
vs.I
ON
40
L
g
=50nm
W
fin
=35nm
H
fin
=65nm
FinDesignConsiderations
S
o
u
r
c
e
D
r
a
i
n
FinWidth
FinHeight
GateLength
P
fin
FinWidth
DeterminesDIBL
FinHeight
Limitedbyetchtechnology
Tradeoff:layoutefficiency
vs. designflexibility
FinPitch
Determineslayoutarea
LimitsS/Dimplanttiltangle
Tradeoff:performancevs.layoutefficiency
41
FinFETLayout
LayoutissimilartothatofconventionalMOSFET,except
thatthechannelwidthisquantized:
BulkSiMOSFET
Source
Drain
Source
Gate
Gate
Source
Drain
Source
FinFET
P
fin
Intel
Corp.
42
TheS/Dfinscanbemergedbyselectiveepitaxy:
M.Guillorn etal.(IBM),Symp.VLSITechnology2008
ImpactofFinLayoutOrientation
(Seriesresistanceismore
significantatshorterL
g
.)
Ifthefinisoriented||or to
thewaferflat,thechannel
surfacesliealong(110)planes.
lowerelectronmobility
higherholemobility
Ifthefinisoriented45 tothe
waferflat,thechannelsurfaces
liealong(100)planes.
L.Changetal.(IBM),SISPAD 2004 43
FinFETBasedSRAMDesign
BestPaperAward:Z.Guo,S.Balasubramanian,R.Zlatanovici,T.J.King,andB.Nikolic,
FinFETbasedSRAMdesign,IntlSymposiumonLowPowerElectronicsandDesign,pp.27,2005
6TSRAMCellDesigns CellLayouts
ButterflyCurves
44
Reducedcellareawith
independentlygatedPGs
StateoftheArtFinFETs
45 C.C.Wuetal.(TSMC),IEDM 2010
22nm/20nmhighperformance
CMOStechnology
L
g
=25nm
XTEMImagesofFin
LookingtotheFuture
2010InternationalTechnologyRoadmapforSemiconductors(ITRS)
2012 2014 2016 2018 2020 2022 2024
GateLength 24nm 18nm 15nm 13nm 11nm 10nm 7nm
GateOxide
Thickness,T
OX
(nm)
DriveCurrent,I
DSAT
EndofRoadmap
(always~15yrs away!)
46
FinFET vs.UTBBSOIMOSFET
K.Chengetal.(IBM),SymposiumonVLSI
TechnologyDigest,pp.128129,2011
CrosssectionalTEMviews
of25nmUTBSOIdevices
NFET
*C.C.Wuetal.
(TSMC),IEDM
2010
B.Doris(IBM),2011
IEEEInternational
SOIConference
PFET
T
Si
=5nm
T
Si
=5nm
47
ProjectionsforFinFET vs. UTBBSOIMOSFETs
2x10
12
4x10
12
6x10
12
8x10
12
10
13
Open: FinFET
Closed: FDSOI
Unstrained
Longi.
Trans.
Vertical
Inversion Charge Concentration (cm
-2
)


2x10
12
4x10
12
6x10
12
8x10
12
10
13



Inversion Charge Concentration (cm
-2
)
Unstrained
Longi.
Trans.
Vertical
Open: FinFET
Closed: FDSOI
2x10
12
4x10
12
6x10
12
8x10
12
10
13
100
150
200
250
300
FDSOI
Inversion Charge Concentration (cm
-2
)
E
l
e
c
t
r
o
n

M
o
b
i
l
i
t
y

(
c
m
2
/
V
.
s
)


Unstrained
Longi.
Trans.
Vertical
FinFET
2x10
12
4x10
12
6x10
12
8x10
12
10
13
60
90
120
150
180
210
240
270
300
H
o
l
e

M
o
b
i
l
i
t
y

(
c
m
2
/
V
.
s
)
Inversion Charge Concentration (cm
-2
)

Unstrained
Longi.
Trans.
Vertical

FinFET
FDSOI
2x10
12
4x10
12
6x10
12
8x10
12
10
13
0
0
0
0
0
0
0
0
0
FDSOI
Inversion Charge Concentration (cm
-2
)
Unstrained
Longi.
Trans.
Vertical
FinFET
20nm
t
SOI
=7nm; t
FIN
=10nm
14/16nm
t
SOI
=5nm; t
FIN
=7.5nm
10/12nm
t
SOI
=3.5nm; t
FIN
=5nm
2x10
12
4x10
12
6x10
12
8x10
12
10
13



Inversion Charge Concentration (cm
-2
)
Unstrained
Longi.
Trans.
Vertical
FinFET
FDSOI
NMOS:
Electron
Mobility
PMOS:
Hole
Mobility
N.Xu etal. (UCBerkeley),IEEEElectronDeviceLetters,Vol.33,pp.318320,2012 48
TechnologyNode:
RemainingFinFET Challenges
V
TH
adjustment
Requiresgateworkfunction(WF)orL
eff
tuning
DynamicV
TH
controlisnotpossibleforhighaspectratiomultifindevices
Fringingcapacitancebetweengateandtop/bottomofS/D
Mitigatedbyminimizingfinpitchand
usingviacontacted,mergedS/D
Parasiticresistance
UniformS/Ddopingis
difficulttoachievewith
conventionalimplantation
Variability
Performanceisverysensitivetofinwidth
WFvariationdominantforundoped channel
49
M.Guillorn,Symp.VLSITechnology2008
e.g.Y.Sasaki,IEDM2008
H.Kawasaki,IEDM2008
T.Matsukawa,Symp.VLSITechnology 2008
Conformaldopingisneeded
RandomDopantFluctuationEffects
Channel/bodydopingcanbeeliminatedtomitigateRDFeffects.
However,duetosource/draindoping,atradeoffexistsbetween
performance&RDFtoleranceforL
g
<10nm:
1E-10
1E-8
1E-6
1E-4
6.5 5.5 4.5
I
O
F
F

(
A

/

m
)
T
Si
(nm)
0
25
50
75
100
o
SD
= 3nm
o
V
T

(
m
V
)
0.4
0.8
o
SD
=3nm

6.5 5.5 4.5
I
O
N

(
m
A

/

m
)
T
Si
(nm)
V. Varadarajan et al. (UC-Berkeley), IEEE Silicon Nanoelectronics Workshop, 2006
I
OFF
ando
VT
vs.T
Si
I
ON
vs.T
Si
SOIFinFET w/atomistic
S/Dgradientregions:
L
g
=9nm,EOT=0.7nm
50
Bulkvs.SOIMultiGateFETDesign
X.Sunetal.(UCBerkeley),IEEEElectronDeviceLetters, Vol.29,pp.491493,2008
51
Toeasethefinwidth
requirement,thefin
heightshouldbe
reduced.
Thebulktrigatedesign
hasthemostrelaxed
bodydimension
requirements.
SSRW(atthebaseof
thefin)improves
electrostaticintegrity
trigateSOI(thickBOX)
[J.G.Fossum etal.,IEDM 2004]
H
S
i
/

L
e
f
f
W
Si
/L
eff
SOIMOSFETEvolution
TheGateAllAround(GAA)structureprovidesforthegreatest
capacitivecouplingbetweenthegateandthechannel.
http://www.electroiq.com/content/eiq-2/en/articles/sst/print/volume-51/issue-5/features/nanotechnology/fully-gate-all-around-silicon-nanowire-cmos-devices.html
52
ScalingtotheEndoftheRoadmap
32nm
planar
P.Packanetal.(Intel),
IEDM2009
beyond10nm
stackednanowires
C.Dupretal.(CEALETI)
IEDM2008
53
Stackedgateallaround
(GAA)FETsachievethe
highestlayoutefficiency.
22nm
multigate
segmentedchannel
B.Ho(UCB),ISDRS 2011
IntelCorp.
3D:
quasiplanar:
Summary
TheFinFET wasoriginallydevelopedformanufactureof
selfaligneddoublegateMOSFETs,toaddresstheneed
forimprovedgatecontroltosuppressI
OFF
,DIBLand
processinducedvariabilityforL
g
<25nm.
TriGateandBulkvariationsoftheFinFET havebeen
developedtoimprovemanufacturabilityandcost.
Ithastaken~10yearstobring3Dtransistorsintovolume
production.
MultigateMOSFETsprovideapathwaytoachieving
lowerpowerand/orimprovedperformance.
FurtherevolutionoftheMOSFETtoastackedchannel
structuremayoccurbytheendoftheroadmap.
54
Acknowledgments
55
YangKyu
Choi
DighHisamoto Hideki Takeuchi XuejueHuang Wen-Chin Lee JakubKedzierski
PushkarRanade, Charles Kuo, DaewonHa
Stephen Tang
Leland Chang Nick Lindert
ZhengGuo
Sriram
Balasubramanian
Kyoungsub
Shin
PeiqiXuan
Prof. Nikolic
Radu
Zlatanovici
Profs.Hu,King,Bokor
Prof.
Subramanian
CollaboratorsatUCBerkeley
Earlyresearchfunding:DARPA,SRC,AMD
UCBerkeleyMicrofabrication Laboratory
(birthplaceoftheFinFET)