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nrd.v: The RTL netlist nrd.mapped.v: The gate level netlist cells.v: Primitive cells lec.do: Conformal script
(Note: The file "cells.v" is identical to the verilog simulation files in the OSU cell library, except for the DFFSR cells, which required a small modification to work with Conformal)
Starting Conformal
To start the tool, type
lec
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Now that the cells are loaded we can bring in the netlist. Do "File -> Read Design" and double-click on "nrd.mapped.v". Note that Conformal changed the "Type" for us to "Revised". The window should look like this:
Note the table that was printed. It lists the primary inputs (PI) and primary
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outputs (PO) in both the revised and golden design. They are equal, which is a good sign. There could be a difference, e.g. if the revised design had differential outputs. Conformal has commands to specify those conditions. The final step is to do "Run -> Compare" and to hit "OK". Now Conformal will reduce both designs to a canonical representation and check if they are equal. Or more precise, if all outputs compute the same Boolean expressions. In our example Conformal shows that all 18 outputs are equivalent. So we know that both netlists are equal.
Schematic view
A handy feature in Conformal is to view a schematic both netlists. This can be helpful in debugging. In the "Revised" column, click with the right mouse button on "nrd" and select "Schematic". It should look as follows:
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Conclusion
This short tutorial showed how to start Conformal, how to read in a golden and a revised design and how to prove that they are identical. All steps can also be coded in a script and run on the command line:
lec -nogui -do lec.do
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