M.

Tech Projects

VLSI
S.NO

Projects Titles
Low-Power and Area-Efficient Carry Select Adder Platform-Independent Customizable UART Soft-Core Accumulator Based 3-Weight Pattern Generation An efficient FPGA implementation of the Advanced Encryption Standard algorithm Implementation of a Flexible and Synthesizable FFT Processor An On-Chip Delay Measurement Technique Using Signature Registers For Small-Delay Defect Detection Period Extension And Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG Single Cycle Access Structure For Logic Test A Lightweight High-Performance Fault Detection Scheme For The Advanced Encryption Standard Using Composite Fields A Low-Power Single-Phase Clock Multiband Flexible Divider ON MODULO 2n + 1 ADDER DESIGN Measurement And Evaluation Of Power Analysis Attacks On Asynchronous S-Box Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics Design and Implementation of a High Performance Multiplier using HDL An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC

Year 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2011

1 2 3 4 5 6 7 8 9

10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35

Reliable and Cost Effective Anti-coll ision Technique for RFID UHF Tag

2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2011 2010 2010 2010 2010

Ddr3 Based Lookup Circuit For High Performance Network Processing Design And Implementation Of High Performance AHB Reconfigurable Arbiter For On-Chip Bus Architecture Self-Immunity Technique to Improve Register File Integrity against Soft Errors 16-Bit RISC Processor Design For Convolution Application Radix-8 Booth Encoded Modulo 2n-1 Multipliers With Adaptive Delay For High Dynamic Range Residue Number System A Spurious-Power Suppression Technique for Multimedia/DSP Applications (MAC) High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree An Efficient Implementation of Floating Point Multiplier Reducing the Computation Time in (Short Bit-Width) Twos Complement Multipliers Design and Characterization of Parallel Prefix Adders using FPGAs A New VLSI Architecture Of Parallel Multiplier Accumulator Based On Radix-4 Modified Booth Algorithm. An Efficient Architecture For 3-D Discrete Wavelet Transform. Low Power ALU Design By Ancient Mathematics Design Of On-Chip Bus With OCP Interface An Efficient Architecture For 2-D Lifting-Based Discrete Wavelet Transform Multiplication Acceleration Through Twin Precision Efficient FPGA Implementation Of Convolution Implementation Of FFT/IFFT Blocks For OFDM

2009 2009 2009 2009

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