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Source Book: GATE Multiple Choice Questions ECE Author: RK Kanodia ISBN: 9788192276205 Publisher : Nodia and Company Visit us at: www.nodia.co.in Edition: 6th
The concentration of minority carriers in an extrinsic semiconductor under equilibrium is (A) Directly proportional to the doping concentration (B) Inversely proportional to the doping concentration (C) Directly proportional to the intrinsic concentration (D) Inversely proportional to the intrinsic concentration
SOL 1.1
Hence (B) is correct option. For n -type p is minority carrier concentration np = n i2 np = constant Since ni is constant p\ 1, n Thus p is inversely proportional to n. A diode has forward voltage drop 0.7 V at current 1 mA and = 1. It is operated at 0.5 V. What is the value of current (A) 3.35 A (B) 0.335 A (C) 0.335 mA (D) 3.35 mA
T
MCQ 1.2
SOL 1.2
Hence (A) is correct option. I = Is eV/V = Is e0.7/0.25 = 5 # 103 Is = 5 # 103 # e0.7/0.025 = 3.46 # 1015 A
MCQ 1.3
In a bipolar transistor, IC = Is expVBE and IC = IB . What is the value of r of VT small signal model VT (B) (A) IC IC VT (C) VT IC (D) VT IC
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Page 2 SOL 1.3 Electronic Devices Test Paper-1
Hence (B) is correct option. We have collector current IC = Is exp c VBE m, IC = IB VT Trans-conductance gm = 2IC 2VBE = 1 exp bVBE l = IC VT VT VT VT r = 2VBE = 2VBE = = 1 2I gm IC 2IB C Consider the following statements S1 and S2 . S1 : The threshold voltage (VT ) of a MOS capacitor decreases with increase in gate oxide thickness. S2 : The threshold voltage (VT ) of a MOS capacitor decreases with increase in substrate doping concentration. Which Marks of the following is correct ? (A) S1 is FALSE and S2 is TRUE (B) Both S1 and S2 are TRUE (C) Both S1 and S2 are FALSE (D) S1 is TRUE and S2 is FALSE
MCQ 1.4
SOL 1.4
Hence (C) is correct option. Increase in gate oxide thickness makes difficult to induce charges in channel. Thus VT increases if we increase gate oxide thickness. Hence S 1 is false. Increase in substrate doping concentration require more gate voltage because initially induce charges will get combine in substrate. Thus VT increase if we increase substrate doping concentration. Hence S 2 is false. The typical number of diffusions used in making epitaxial-diffused silicon integrated circuit is (A) 1 (B) 2 (C) 3 (D) 4
MCQ 1.5
Hence (C) is correct option. In n -well CMOS fabrication substrate is (A) lightly doped n -type (B) lightly doped p -type (C) heavily doped n -type (D) heavily doped p -type
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Page 3 Electronic Devices Test Paper-1
(A) an important characteristic of a diffused region especially when used to form diffused resistors (B) an undesirable parasitic element (C) a characteristic whose value determines the required area for a given value of integrated capacitance (D) a parameter whose value is important in a thin-film resistance
SOL 1.7 MCQ 1.8
Hence (A) is correct option. A MOS capacitor has oxide thickness tox of 50 nm. The capacitance is (B) 69 nF/cm2 (A) 101 nF/cm2 (C) 84 nF/cm2 (D) None of the above
SOL 1.8
MCQ 1.9
Hence (B) is correct option. 1014 = 69 nF/cm2 ' C ox = ox = 3.9 # 8.85 # 7 tox 50 # 10 In bipolar transistor biased in the forward-active region the base current is IB = 50 A and the collector currents is IC = 2.7 mA. The is (A) 0.949 (B) 54 (C) 0.982 (D) 0.018
SOL 1.9
Hence (C) is correct option. F F = IC , F = IB 1 + F 2. 7m = = 0.982 F = IC 2.7m + 50 IC + IB A silicon pn junction at T = 300 K has Nd = 1014 cm3 and Na = 1017 cm3 . The built-in voltage is (A) 0.63 V (B) 0.93 V (C) 0.026 V (D) 0.038 V 1017 # 1014 = 0.63 V d Vbi = Vt ln c Na N 2 m 0.0259 ln ni (1.5 # 1010) 2
MCQ 1.10
SOL 1.10
For a particular semiconductor material following parameters are observed: n = 1000 cm2 /V-s, p = 600 cm2 /V-s, Nc = Nv = 1019 cm3 These parameters are independent of temperature. The measured conductivity
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Page 4 Electronic Devices Test Paper-1
of the intrinsic material is = 106 ( - cm) 1 at T = 300 K. The conductivity at T = 500 K is (A) 2 # 104 ( - cm) 1 (B) 4 # 105 ( - cm) 1 (C) 2 # 105 ( - cm) 1 (D) 6 # 103 ( - cm) 1
SOL 1.11
Hence (D) is correct option. 1 = eni (n + p) 106 = (1.6 # 1019) (1000 + 600) ni At T = 300 K, ni = 3.91 # 109 cm3
v n i2 = Nc Nv ec kT m & Eg = kT ln c Nc N n i2 m 1019 & Eg = 2 (0.0259) ln c = 1.122 eV 3.91 # 109 m Eg
&
ni = 2.29 # 1013 cm3 = (1.6 # 1019) (2.29 # 1013) (1000 + 600) = 5.86 # 103 ( cm) 1
MCQ 1.12
Listed below in Table A diode current I , the corresponding diode voltage V , and diode voltage at a current I/10. Table B contains and Is , match them Table : 1 I, (P) (Q) (R) (S) 10. mA 1 mA 10 A 10 A V1 , V 700 mV 600 mV (1) 700 mV 600 mV (2) 800 mV 700 mV (3) 700 mV 600 mV (4) Table : 2 1.737 1.737 1.737 2.08 Is 109 1010 107 1.47 # 109
(A) P-1, Q-2, R-3, S-4 (C) P-4, Q-1, R-2, S-3
SOL 1.12
(B) P-2, Q-1, R-4, S-3 (D) P-4, Q-2, R-1, S-3
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Page 5 Electronic Devices Test Paper-1
Is = IeV /V So we can match the corresponding values. P " 1, Q " 2, R " 3, S " 4
1 T
MCQ 1.13
Two ideal pn junction have exactly the same electrical and physical parameters except for the band gap of the semiconductor materials. The first has a band-gap energy of 0.525 eV and a forward-bias current of 10 mA with Va = 0.255 V . The second pn junction diode is to be designed such that the diode current I = 10 a at a forward-bias voltage of Va = 0.32 V . The band-gap energy of second diode would be (A) 0.77 eV (B) 0.67 eV (C) 0.57 eV (D) 0.47 eV I \ n i2 ecV m \ ec V m ecV m
Va
t
SOL 1.13
Va
t
&
I \ ec
Va Eg Vt m Va Eg1 Vt m a2 E g2 m V
t
I1 = e c V I2 ec 10 # 10 = e 10 # 106
3
A uniformly doped silicon epitaxial npn bipolar transistor is fabricated with a base doping of NB = 3 # 1016 cm3 and a heavily doped collector region with NC = 5 # 1017 cm3 . The neutral base width is xB = 0.7 m when VBE = VBC = 0 . The VBC at punch-through is (A) 26.3 V (B) 18.3 V (C) 12.2 V (D) 6.3 V
SOL 1.14
Hence (B) is correct option. C Vbi = Vt ln c NB N n i2 m 16 17 # 10 = 0.824 V = 0.02591n e 3 # 10 # 5 10 o 2 (1.5 # 10 ) At punch-through xB = 0.7 # 104 = x p (VBC = Vpt) x p (VBC = 0) = >)
2 2 (Vbi + Vpt) NC 1 3 e NB (NC + NB) 1
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Page 6 Electronic Devices Test Paper-1
=)
'
&
0.7 # 104 = 2.02 # 105 (Vbi + Vpt) 1.83 # 105 Vbi + Vpt = 19.11 & Vpt = 19.11 0.824 = 18.3 V
MCQ 1.15
What is the ratio of transistors cross-sectional area ? (A) 2.16 (B) 20 26 (C) 1 13
SOL 1.15
(D) 4 14
IC =
AE qDn n i2 V (e NE WB
BE
/VT
1)
BE
IC . If AE qDn n i2 V (e NE WB
1 BE 1 1
AE qDn n i2 V (e NE WB
2
/VT
IC = IC ,
/VT
)=
AE qDn n i2 V (e NE WB
2
BE 2
/VT
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Page 7 Electronic Devices Test Paper-1
AE = e(V AE
2 1
BE 1
VBE 2) VT
= e20/26 . 2.16
MCQ 1.16
In an n+ polysilicon-silicon dioxide n -type silicon MOS capacitor impurity c when equivalent trapped concentration is 1015 cm3 . The oxide thickness is 500 A ' oxide charge is Q ss = 1010 C/cm2 .The flat-band voltage is (A) 0.29 V (B) 0.29 V (C) 1.2 V (D) 1.2 V Hence (B) is correct option. Q' VFB = ms ss ' C ox 14 ' C ox = ox = 3.9 # 8.85 #10 = 6.9 # 108 F/cm2 tox 500 # 10 8 For n+ polysilicon gate to n -type silicon E ms =b g fn l, 2e fn = Vt ln b Nd l ni = 0.0259ln c 1015 = 0.288 V 1.5 # 1010 m
SOL 1.16
For an n -channel MOSFET and its transfer curve shown in the fig. the threshold voltage is
(A) 1 V and the device is in active region (B) 1 V and the device is in saturation region (C) 1 V and the device is in saturation region (D) 1 V and the device is in active region
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Page 8 SOL 1.17 Electronic Devices Test Paper-1
Hence (C) is correct option. From the graph it can be easily seen that Vth = 1 V Now VGS = 3 1 = 2 V and VDS = 5 1 = 4 V Since VDS > VGS " VDS > VGS Vth Thus MOSFET is in saturation region. For a particular NMOS device the parameters are VTN = 1 V , L = 2.4 m , c . When device is biased in the saturation region n = 600 cm2 /V -s and tox = 400 A at VGS = 5 V , the drain current is ID = 1.2 mA . The channel width of device is (A) 7.21 m (B) 10.46 m (C) 5.23 m (D) 20.92 m Hence (A) is correct option 14 ' C ox = ox = 3.9 # 8.85 #10 = 8.63 # 108 F/cm2 8 tox 400 # 10 ' 8 C Kn = n ox bW l = 600 # 8.63 # 10 b W l 2 2 2. 5 L & Kn = 1.04 # 105 W , ID = Kn [VGS VTN ] 2 1.2 # 103 = 1.04 # 105 W (5 1) 2 & W = 7.21 m
MCQ 1.18
SOL 1.18
&
MCQ 1.19
A uniformly doped npn bipolar transistor has following parameters: NE = 1018 cm3 , NB = 5 # 1016 cm3 NC = 2 # 1019 cm3 DE = 8 cm2 /s , DB = 15 cm2 /s , DC = 14 cm2 /s xE = 0.8 m , xB = 0.7 m The emitter injection efficiency is (A) 0.999 (B) 0.977 (C) 0.982 (D) 0.934
SOL 1.19
Hence (B) is correct option. 1 = N 1 + B . DE . xB NE DB xE 1 = 0.977 16 5 10 8 0.7 # 1+ 1018 15 0.8 An n n isotope doping profile is shown in below. The built-in potential barrier is (ni = 1.5 # 1010 cm3) =
MCQ 1.20
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Page 9 Electronic Devices Test Paper-1
For
Nd = 1015 cm3 EF EFi = 0.0259ln 1015 = 0.287 eV 1.5 # 1010 Vbi = 0.347 0.287 = 0.06 V
MCQ 1.21
In a sample of silicon at T = 300 K, the electron concentration varies linearly with distance, as shown in fig. The diffusion current density is found to be Jn = 0.19 A/ cm2 . If the electron diffusion coefficient is Dn = 25 cm2 /s, The electron concentration at is
Hence (B) is correct option Jn = eDn dn dx 5 1014 n (0) 0.19 = (1.6 # 1019) (25) c # m, 0.010 n (0) = 2.5 # 1013 cm3
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Page 10 Electronic Devices Test Paper-1
The majority carrier concentration is (A) 8 # 1015 cm3 , n -type (C) 4 # 1015 cm3 , n -type
SOL 1.22
Hence (B) is correct option. VH is positive p -type VH = Ix Bx & p = Ix Bz epd eVH d p = (0.75 # 103) (101) (1.6 # 1019) (5 # 105) = 8.08 # 1021 m3 = 8.08 # 1015 cm3 (B) 215 cm2 /V-s (D) 195 cm2 /V-s
MCQ 1.23
The majority carrier mobility is (A) 430 cm2 /V-s (C) 390 cm2 /V-s
SOL 1.23
Hence (C) is correct option p = Ix L epVx Wd (0.75 # 103) (101) (1.6 # 1019) (5.8 # 103) (105) p = 3.9 # 102 m2 /V-s = 390 cm2 /V-s =
If gate is n+ polysilicon the required silicon doping required is (A) 4 # 1011 cm3 (B) 4 # 1013 cm3 (C) 4 # 1016 cm3 (D) Cannot use n+ polysilicon gate
SOL 1.24
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Page 11 Electronic Devices Test Paper-1
0.35 =b 1.11 fn l & fn = 0.205 2 fn = Vt ln b Nd l ni & Nd = 1.5 # 1010 eb 0.0259 l = 4 # 1013 cm3
0.205
MCQ 1.25
If gate is p+ polysilicon, then the required silicon doping is (A) 8 # 1011 cm3 (B) 8 # 1013 cm3 (C) 8 # 1015 cm3 (D) Cannot use n+ polysilicon gate
SOL 1.25
Hence (D) is correct option. For p+ polysilicion gate E ms = b g + fs l 2e & 0.35 = b 1.11 + fn l & fn = 0.905 V 2 The is impossible, cannot use a p+ polysilicon gate.
Answer Sheet
1. 2. 3. 4. 5.
6. 7. 8. 9. 10.