Lez1 PDF

Simone Buso - University of Padova
September 1999
Digital Control Applications in Power Electronics

Simone Buso
University of Padova - Italy Department of Electronics and Informatics Power Electronics Laboratory
e-mail email: : simone simone@dei. @dei.unipd unipd. .it
Lesson 1
Digital Control Tools: Microcontrollers and Digital Signal Processors .
September 1999
Simone Buso - University of Padova - Lesson 1
Lesson #1
September 1999
Introduction
Digital Control Advantages: Advantages: Flexibility Ease of upgrade Man to Machine Interface (MMI) Sophisticated control techniques Reduced number of components Unsensitivity to components ageing Digital Control Disadvantages: Disadvantages: Design complexity Cost Dynamic performance (sampling (sampling frequency, frequency, quantization...) quantization ...)
September 1999 Simone Buso - University of Padova - Lesson 1 3
Introduction
Available tools for digital control implementation Microcontrollers ( C) CISC ( (C Complex I Instruction nstruction S Set et C Computer omputer) ) machines (micro(micro-coded coded instructions) instructions) RISC (R (Reduced I Instruction nstruction S Set et Computer omputer) ) machines ( (with with/ /without hardware multiplier multiplier) ) 4 to 32 bit CPU and bus Digital Signal Processors (DSP) Fixed Fixed- point arithmetic Floating Floating-point arithmetic
September 1999
Lesson #1
September 1999
Introduction
General C features: features: specifically designed for control tasks A/D converters almost always included on chip capture and compare input pins available several programmable I/O pins timers and counters available (PWM) different kinds of external memory available (ROM, EEPROM, FLASH) different computational powers available ( (from from 32 bit RISC to simple 8 bit CPUs and even less less) ) lots of third party development tools (EV(EV-Boards Boards, , in incircuit emulators ( (ICEs ICEs)) ))
Introduction
General DSP features features: : not specifically designed for control tasks A/D converters not always included on chip useful peripheral units ( (CapCom CapCom, , timers timers, , PWM) normally not present on chip very high computational power available (32 bit RISC CPUs both fixed and floating point) point) relatively few third party development tools (EVBoards) Boards ) new DSP solutions for power electronic applications are now becoming available (TMS320F240, ADMC401)
Lesson #1
September 1999
Microcontrollers
A C is essentially a computing machine where, where, on the same chip, chip, a CPU core is interfaced with different peripheral units, units, allowing it to perform various control functions. functions . In modern Cs Cs, , the typical CPU architecture is the sosocalled Harvard architecture architecture, , based on separate program and data memories and buses. buses . An hardware multiplier is quite often present in state of the art products products. . The typical peripheral units include: include :

September 1999
A\D converters Timers and counters PWM modulators

Simone Buso - University of Padova - Lesson 1 7
Microcontrollers
In the selection of a C unit for any given control application some key parameters must be considered: considered : performance parameters cost parameters As in any project, project, these two aspects typically have to be tradedtraded-off off. .
September 1999
Lesson #1
September 1999
Microcontrollers
Typical performance parameters are: CPU clock period instruction cycle instruction set (RISC or CISC) memory area interrupt management peripheral unit availability The cost is indirectly determined also by: by : avaliability of development tools cost of the evalution board, board, ICE, etc etc. . etc etc. . and strongly depends on production volume
Microcontrollers
The C market is very large and rich of products. products. A lot of manufacturers offer complete sets of C solutions solutions, , with increasing complexity, complexity, level of performance and cost. cost . An exhaustive overview is practically impossible impossible; ; some examples can be shown of different products with different complexities, complexities, which allow to get a glimpse of what can be found on the market. market. Common features in terms of system architecture and peripheral units can be easily identified. identified.
September 1999
10
Lesson #1
September 1999
Example: Example : ST6 microcontroller [1]

Very simple (16 pins pins) ) and low cost C, with 8-bit CPU and 9 I/O pins pins. . Low supply voltage (3V, 6V). Low clock frequency (8Mhz max max.) .) Minimum instruction cycle 1.625s. Low computational power: power: only 40 simple instructions are available (no multiply instruction). instruction ). Peripheral units limited to Timer and A\D converter (8 bit). Typical applications: applications: sequence control, control, display driver, simple and low speed closed loop controls. controls .
September 1999
11
ST6 microcontroller block diagram
September 1999
12
Lesson #1
September 1999
ST6 microcontroller
CPU block diagram
September 1999
13
Example: Example : Siemens 8xC166 C [2]

Typical ( (but but not widely used) used) 16-bit C. High clock frequency (20MHz maximum (internal internal)). )). RISC machine with a large majority of singlesingle-cycle instructions (100ns) thanks to an internal pipeline pipeline. . Von Neumann architecture (a single memory space is used both for data and program code). code ). Medium computational power (no hardware multiplier multiplier). ). Available peripheral units: units: 2 general purpose timers 16 bit; 2 independent serial communication channels; channels ; 10 channels channels, , 10-bit, 10 s A\D converter; 16 capture and compare (CAPCOM) channels channels. .
Lesson #1
September 1999
Siemens 8xC166 series overview

Prefix Memory Type Code Type Designation Memory Size Code Package Code Temp. Range Code
ROMLess 80 Metal Mask ROM SAB
C166 C166W
(-) (-) 5 5 32KBytes 5 5
M M M M M M
M = Metric Quad Flatpack
C166 83 C166W C166 C166W

W = without prescaler
88 Flash EEPROM
(-) T3 (-) T3 T4 (-) T3 (-) T3 T4 (-)
0 / 70 -40 / 85 0 / 70 -40 / 85 -40 / 110 0 / 70 -40 / 85 0 / 70 -40 / 85 -40 / 110 0 / 70 0 / 70 (-)
(-) no suffix
September 1999
15
SAB 80C166 Block Diagram

up to 32 KByte ROM / Flash EPROM
16
Data Instr./Data
Dual Port 16
32
SAB 8xC166 CPU CORE
RAM
Data
1 KByte
XTAL
OSC
External Instr./Data
PEC Watchdog
19 ext. IR 16
Peripheral Data
Interrupt Controller
Interrupt Bus 16
t
o P r ot
Bus Controller
16 Channels
ASC BRG
ASC BRG Port 3
T3 T4
T5 T6
16
Port 1
Port 5
Port 2
16
2 16 10 16
September 1999
Timer 0
T2
Timer 1
External
10-Bit ADC
USART
USART GPT1 GPT2
CAPCOM
16
Lesson #1
September 1999
SAB 80C167 Block Diagram

C166-Core
up to 16
Data Instr./Data
128 KByte ROM / Flash EPROM

PLL
Dual Port
CPU
32
RAM 2 KByte
Data
16
XTAL
(input: 5 MHz)
OSC
(output: 20MHz)
External Instr./Data
PEC Watchdog
36 ext. IR 16
XBUS (16-bit NON MUX Data /Addresses)
Interrupt Controller
16
2KB
XRAM
Interrupt Bus
Peripheral Data
P r o t r o P r ot
Multi Funktional
Timer 1
XBUS Control, 5 * CS Logic
T2 T3 T4 T5
16 Channels
ASC SSC BRG BRG
32 Channels
Timer 7 Timer 8
Timer 0
External Bus ,
10-Bit
USART
ADC
Sync. Channel (SPI)
GPT1 GPT2
CAPCOM1, 2
PWM Module
PT 1 PT 2 PT 3 PT 4
T6
16
Port 1
Port 5
Port 3
Port 2
Port 8
Port 7
167
16
16
16
16
September 1999
17
Peripherals Set of the SAB 80C167

2 General Purpose Timer units (GPT1 & GPT2) 5 Timers (200/400ns) with multiple Input/Output, Input/Output, Reload and Capture functions and complex concatenation capabilities Capture/Compare unit (CAPCOM) 2 timers (400ns) each with Reload register and 16 independent 16-bit Capture/Compare channels programmable to 6 modes of operation 4 high resolution PWM channels with independent time-base of up to 50ns resolution and programmable operation modes ...
September 1999
4 0 6
18
Lesson #1
September 1999
Peripherals Set of the SAB 80C167

Fast and accurate A/D Converter 10-bit resolution resolution, , 10 input channels, channels , 9.7s conversion time, continuous and scan modes I/O Ports 8 ports provide 111 I/O lines Watchdog Watchdog: : 16-bit Reload Reload-timer causes reset on overflow 2 independent identical USARTs max 625KBaud asynchronous max 2.5Mbit/ 2.5Mbit/sec sec synchronous data transfer
September 1999
19
Pulse Width Modulation Unit (PWM)

4 completely independent PWM channels each with its own time-base 50ns or 12.8s timer timer- resolution provides a very wide frequency range to generate PWM signals Programmable output polarity Up to 78 KHz at 8-bit PWM resolution FPWM =
2 1
8-bit
=78 KHz
x 50ns
Four operation modes Standard, edge edge-aligned PWM Symmetrical Symmetrical, , center center- aligned PWM for asynchronous motor control Burst Burst-mode for modulated PWM signals Single Single-shot mode
Lesson #1
10
September 1999
Pulse Width Modulation Unit (PWM)

PMW Unit Frequencies and Resolution in Mode 0 Operation (EDGE-ALIGNED)
Resolution Input Clock (CPU @ 20 MHz) CPU Clock (50ns Resolution ) CPU Clock / 64 (3.2s Res.) 8 Bit 10 Bit 12 Bit 14 Bit 16 Bit
78.1 KHz 1.22 KHz
19.5 KHz 305 Hz
4.88 KHz 1.22 KHz 76.3 Hz 13.1 Hz
305 Hz 4.77 Hz
PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL)

Resolution Input Clock (CPU @ 20 MHz) CPU Clock (50ns Resolution ) CPU Clock / 64 (3.2s Res.) 8 Bit 10 Bit 12 Bit 14 Bit 16 Bit
39.1 KHz 610 Hz
9.77 KHz 152.6 Hz
2.44 KHz 38.15 Hz
610 Hz 9.54 Hz
152.6 Hz 2.4 Hz
September 1999
21
PWM unit Mode 0 and 1...

PWM Mode 0: Standard PWMs or Edge-Aligned PWMs PWM Mode 1: Symmetrical or Center-Aligned PWMs
iod Tim
Tim
Pe er
rio
Contents of the Period Register (PPx)
Tim
Interrupt Request and Latch of the Shadow Register PWM Signal
P er
er
er
Pe
rio
Contents of the PWx Register
Contents of the PWx Register PWM Signal
IR and Latch of the Shadow Register
If all channels are programmed to mode 0, edge-aligned PWM signals will be generated. A duty cycle from 0 to 100% is programmable PWMx PWMy
If all channels are programmed to mode 1, center -aligned PWM signals will be generated . A duty cycle from 0 to 100% is programmable
Possible PWM Signals from other channels programmed to the same mode September 1999 Simone Buso - University of Padova - Lesson 1 22
Lesson #1
11
September 1999
PWM unit Mode 0 and 1

Burst Mode : Burst Sequence by combining PWM channel 0 and 1
ri Pe od PT 0
Single Shot : Only one PWM Pulse is generated Mode available for channel 2 and 3
e rP rio d
Period Value
Ti m e
Period Value
Tim
er
Internal Signal of Channel 0 Period of Timer PT1

Int. Signal of Channel 1
Pulse width Value

Timer is automatically stopped
Timer is released by Software again
Period Value
Output Signal
Output Result: Channel 1 is modulated by Channel 0
The Timer can be dynamically changed to lengthen (retrigger) or shorten the output pulse
23
September 1999
Example: Example : Hitachi H8S series [3]

Recent 16-bit C ( (evolution evolution of H8/500 series). High clock frequency (20MHz and higher). higher). Single cycle instructions (200ns @20MHz). Rich set of instruction (CISC machine machine). ). Hardware multiplier and accumulator for DSP-like DSP-like applications. applications . Medium Medium/ / high computational power . Available peripheral units: units: timer unit for CAPCOM or PWM functions serial communication interface 8 channel channel, , 10-bit, 1 s A\D converter 2 channel channel, , 10 s D\A converter ( (only only in some versions) versions )
Lesson #1
12
September 1999
CPU
Timer
H83032 microcontroller block diagram
A\D Converter
September 1999
25
Example: Example : Microchip PIC17C7xx [4]

State of the art 16-bit C (5V supply supply, , stand stand-by current < 1 A). High clock frequency (33MHz maximum maximum). ). Single cycle instructions (121ns @33MHz). RISC machine (58 single single-word 16-bit instructions instructions). ). Modified Harvard architecture with hardware multiplier. multiplier . High computational power . Available peripheral units: units: 4 timers 8-16 bit; serial communication interface; 12-16 channels channels, , 10-bit, 16 s A\D converter; 3 PWM 10 bit outputs outputs. .
Lesson #1
13
September 1999
Microchip PIC17C7xx
September 1999
27
CPU
Microchip PIC17C7xx
Data memory
Program memory
September 1999
28
Lesson #1
14
September 1999
Example: Example : Hitachi SH7000 Series [3]

State of the art 32-bit C (5V or 3.3V supply supply). ). High clock frequency (28MHz @ Vcc = 5V). RISC machine (61 single single-word 16-bit instructions instructions). ). Single cycle instructions (35ns) thanks to internal fivefive -stage pipeline. pipeline. Modified Harvard architecture with hardware multiplier (MAC: 32x32 bit, 64 bit 64 bit). High computational power . Available peripheral units: units: 16 bit, 5 channels multifunction timer unit (PWM); 16 bit, 2 channel compare and match; match; 8 channels channels, , 10-bit, 2.9 s, A\D converter; watchdog timer. timer.
SH7040 A\D converter
September 1999
30
Lesson #1
15
September 1999
Digital Signal Processors [5]

First development in the late 70s (TMS320C10 - 1979). Typically designed for open loop digital signal processing e.g.: real time FFT calculation calculation; ; digital filtering of sampled signals. signals. The market for this kind of applications is enormous (10 billion US$/ US$/year year) ) and is steadily growing, growing, including telecom and consumer electronics. electronics. Applications in industrial electronics ( (control control tasks) tasks) are rather insignificant in volume. The manifacturers offer very few control oriented solutions. solutions .
Digital Signal Processors

Two types of DSPs can be found: found : fixed point DSP (16, 24 bit); floating point ( (typically typically 32 bit or more). For control applications, applications, fixed point DSPs are very close to modern toptop-level Cs (RISC machines with Harvard architecture and hardware multiplier multiplier) ) in terms of performance. They are normally much less effective in terms of peripherals peripherals. . Globally Globally, , they appear more expensive expensive. . Floating point DSPs are very advantageous, advantageous, but only for those applications where high cost for the control system can be afforded. afforded. The lack of peripheral units is almost total ( you must add them them). ).
Lesson #1
16
September 1999

Schematic diagram of a DSP with Harvard architecture. architecture . Parallel processing of instructions and data is allowed by multiple bus architecture. architecture . The instruction processor takes care of address computations. computations.
33
Instruction Memory
Data Memory
Instruction Stream
Data Stream
Instruction Stream Instruction Processing Processor Unit
September 1999

Modern DSPs normally adopt modified Harvard architectures featuring: featuring: improved instruction processors with more than a single address generator; generator; improved processing units with multiple independent logic units (ALU, MAC, SHIFT); application specific hardware modules (e.g. registers, registers , timers etc. etc. ) in the CPU to speed speed-up typical calculations (e.g. DFT); different internal memory structures with multiple data memories and buses or mixed program and data memories ( (useful useful for filter coefficients). coefficients).
Lesson #1
17
September 1999
Example: Example : Analog Devices ADSP2186 [5]

State of the art fixed point DSP. 25 ns instruction cycle for 40 MIPS performance. Single Single-cycle instruction execution. execution. Single Single-cycle context switch. switch. 3-bus architecture for dual operand fetch in every instruction cycle. cycle . Dual address generator. generator. Independent ALU, MAC and SHIFTER units units. . 40 kbyte on chip RAM. Dual purpose program memory allowing both instruction and data storage storage. .
September 1999
35
Example: Example : Analog Devices ADSP2186

1: Address Bus
2: Data Bus
3: Internal Result Bus

Lesson #1
18
September 1999
Example: Example : Analog Devices ADSP2186

A very high level of parallelism is achieved by means of multiple processing units, units, multiple buses and complex address generators. generators. In a single cycle the DSP can: can : generate the next program address; address; fetch the next instruction; instruction ; perform one or two data moves; update one or two data address pointers; pointers; perform a computational operation operation. . The program sequencer allows conditional jumps, jumps, subroutine calls and returns in a single cycle. cycle .
September 1999
37

State of the art floating point DSP. 25 ns instruction cycle for 40 MIPS performance. Single Single-cycle instruction execution. execution. 32 bit single precision and 40 bit extended precision IEEE floating point data format (24 bit mantissa 8 bit exponent / 11 bit exponent exponent) ) or 32 bit fixed point data format. format . 48 bit instruction word for various parallel operations. operations. 4 independent buses for dual data fetch fetch, , instruction fetch and I/O (super-Harvard (super-Harvard architecture). architecture). 3 independent 32 bit floating point computational units. units . Specific instructions for accelerated FFT computation computation. .
Lesson #1
19
September 1999
September 1999
39
New DSP solutions

Recently, new DSP solutions have been proposed Recently, by some manufacturers which merge the DSP computational capabilities with some typical C peripheral units. units. The idea is to provide the designer with a control oriented DSP, allowing the direct implementation of closed loop digital control of power converters with minimum additional interface circuitry circuitry. . The main advantage with respect to any C is in the very high computational capability of the DSP. Since these devices are not very popular yet yet, , the cost factor may be their weak point point. .
Lesson #1
20
September 1999
Example: Example : Analog Devices ADMC401 [5]

Fixed Fixed-point DSP core features features: : 26 MIPS performance; ADSP 21xx compatible compatible; ; Single cycle instruction execution (38.5 ns @ 13 MHz clock frequency); frequency); 16 bit arithmetic and logic unit; unit; Single Cycle 16 bit X 16 bit MAC. Built Built-in peripheral units: units: High resolution multi multi-channel ADC; Three Three-phase 16 bit PWM generation unit unit; ; dual channel event timer unit (CAPCOM); Incremental encoder interface unit unit. .
Example: Example : Analog Devices ADMC401 Functional Block Diagram
21xx core
September 1999
C peripheral units
Simone Buso - University of Padova - Lesson 1 42
Lesson #1
21
September 1999
ADMC401: Analog to Digital Converter

8 analog inputs. inputs. 12 bit resolution resolution. . conversion time: 2 s ( (all all channels thanks to four stage pipeline architecture architecture). ). 4 V p-p input voltage range 2 channels can be simultaneously sampled sampled. . conversion can be synchronized to PWM or externally triggered triggered. .
September 1999
43
ADMC401: PWM Generation Unit

6 PWM outputs outputs. . 16 bit counter resolution. resolution. programmable output polarity. polarity . static or chopped output signals. signals . programmable dead dead-time -time and minimum pulse width width. . single update and double update mode (for asymmetrical PWM patterns patterns). ). switching frequency from 198 Hz to 102 kHz.
Lesson #1
22
September 1999
ADMC401: Incremental Encoder Interface

16 bit up up-down counter (frequency and direction of rotation detection). detection ). programmable input noise filter (to avoid spurious triggering). triggering ). two additional strobe inputs (to latch the counter contents into registers). registers). 16 bit loop timer (position and speed loops set point generation). generation ).
ADMC401: Event Timer Unit

16 bit dedicated timer with programmable frequency. frequency. 2 independent channels channels. . 2 programmable ( (rising rising edge or falling edge) edge ) events for each channel. channel. single shot and free free-running modes of operation. operation. only capture function function, , no possibility of compare mode mode. .
September 1999
46
Lesson #1
23
September 1999
ADMC401: Other Ancillary Fuctions 2 auxiliary 8 bit PWM timers 16 bit watchdog timer Programmable digital I/O port (12 pin pin) ) 2 synchronous serial ports
September 1999
47
Example: Example : Texas Instruments TMS320F240 [6]

Fixed Fixed-point DSP core features features: : 20 MIPS performance; TMS320C25 source code compatible; compatible; Single cycle instruction execution (50 ns @ 20 MHz CPU clock frequency); frequency); 16 bit arithmetic and logic unit; unit; Single Cycle 16 bit X 16 bit signed product. product. Main builtbuilt -in peripheral units: units: 10 bit resolution resolution, , 16 channel ADC; 12 channel 16 bit PWM generation unit unit; ; 3 16 bit general purpose timers timers; ; 4 independent capture circuits circuits. .
Lesson #1
24
September 1999
TMS320F240 Functional Block Diagram Central Arithmetic Logic Unit (CALU) Event Manager: Manager: Timers Compare Units ... Dual 10 bit ADC
September 1999
49
TMS320F240 Central Arithmetic and Logic Unit

Advanced Harvard architecture with multiple bus. 16 bit X 16 bit hardware multiplier with 32 bit accumulator (1 cycle execution). execution ). 16 bit input scaling shifter (used for data alignment before logic or arithmetic operations). operations ).
September 1999
50
Lesson #1
25
September 1999
TMS320F240 Event Manager

3 general purpose timers for 16 bit up up/ /down counts and compare functions ( (including including additional PWM generation generation). ). 6 full compare ouputs for PWM applications with deaddeadtime generators (0 to 102 s). 3 simple compare units units. . The 12 available PWM outputs have all 50 ns resolution and 16 bit dynamic range. 4 channel capture unit operating on GPT1 or GPT2, with 2 level FIFO.
TMS320F240 Analog to Digital Converter

2 10 bit ADCs with builtbuilt -in S/H circuits circuits. . 16 input channels available, available , but only 2 can be sampled simultaneously. simultaneously . Minimum conversion time 6.1 s. Single shot or continuous mode of operation. operation . 2 level FIFO for result storing. storing .
Lesson #1
26
September 1999
TMS320F240 Ancillary Peripheral Functions 4 pin serial peripheral interface watchdog timer Quadrature - encoder pulse circuit 28 programmable I/O pins
September 1999
53
References
[1] ST 1999 Product and Company Information [2] Siemens 1999 Technical Product Information - Edition 7 [3] Hitachi 1998 Electronic Components Databook [4] Microchip 1999 Technical Library [5] P. Pirsch Pirsch, , Architectures for Digital Signal Processing, Processing, 1998, John Wiley and Sons (ISBN 0-471-97145-6) [6] Analog Devices Winter 1999 Designers Reference Manual [7] Texas Instruments 1999 TMS320 DSP Solutions CD-ROM
September 1999
54
Lesson #1
27

Lez1 PDF

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Lez1 PDF

Uploaded by

Copyright:

Available Formats

Simone Buso - University of Padova

Digital Control Applications in Power Electronics

e-mail email: : simone simone@dei. @dei.unipd unipd. .it

Digital Control Tools: Microcontrollers and Digital Signal Processors .

Simone Buso - University of Padova - Lesson 1

Simone Buso - University of Padova

Simone Buso - University of Padova - Lesson 1

Simone Buso - University of Padova

Simone Buso - University of Padova

A\D converters Timers and counters PWM modulators

Simone Buso - University of Padova - Lesson 1

Simone Buso - University of Padova

Simone Buso - University of Padova - Lesson 1

Simone Buso - University of Padova

Example: Example : ST6 microcontroller [1]

Simone Buso - University of Padova - Lesson 1

ST6 microcontroller block diagram

Simone Buso - University of Padova - Lesson 1

Simone Buso - University of Padova

Simone Buso - University of Padova - Lesson 1

Example: Example : Siemens 8xC166 C [2]

Simone Buso - University of Padova

Siemens 8xC166 series overview

ROMLess 80 Metal Mask ROM SAB

(-) (-) 5 5 32KBytes 5 5

C166 83 C166W C166 C166W

(-) T3 (-) T3 T4 (-) T3 (-) T3 T4 (-)

0 / 70 -40 / 85 0 / 70 -40 / 85 -40 / 110 0 / 70 -40 / 85 0 / 70 -40 / 85 -40 / 110 0 / 70 0 / 70 (-)

Simone Buso - University of Padova - Lesson 1

SAB 80C166 Block Diagram

SAB 8xC166 CPU CORE

ASC BRG Port 3

Simone Buso - University of Padova - Lesson 1

USART GPT1 GPT2

Simone Buso - University of Padova

SAB 80C167 Block Diagram

128 KByte ROM / Flash EPROM

XBUS (16-bit NON MUX Data /Addresses)

XBUS Control, 5 * CS Logic

ASC SSC BRG BRG

Sync. Channel (SPI)

Simone Buso - University of Padova - Lesson 1

Peripherals Set of the SAB 80C167

Simone Buso - University of Padova - Lesson 1

Simone Buso - University of Padova

Peripherals Set of the SAB 80C167

Simone Buso - University of Padova - Lesson 1

Pulse Width Modulation Unit (PWM)

Simone Buso - University of Padova

Pulse Width Modulation Unit (PWM)

78.1 KHz 1.22 KHz

19.5 KHz 305 Hz

4.88 KHz 1.22 KHz 76.3 Hz 13.1 Hz

PMW Unit Frequencies and Resolution in Mode 1 Operation (SYMMETRICAL)

39.1 KHz 610 Hz

9.77 KHz 152.6 Hz

2.44 KHz 38.15 Hz

Simone Buso - University of Padova - Lesson 1

PWM unit Mode 0 and 1...

Contents of the Period Register (PPx)

Contents of the PWx Register

Contents of the PWx Register PWM Signal