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Mixed-Signal SoCs With In Situ Self-Healing Circuitry

Christopher Maxey Booz Allen Hamilton Sanjay Raman Defense Advanced Research Projects Agency Kari Groves, Tony Quach, Len Orlando, and Aji Mattamana Air Force Research Laboratory
dimensions. Therefore, a major consequence of the Editors notes: drive towards ever smaller This article discusses the goals and recent achievements of the HEALICs program. The program_s aim is to enhance wireless systems with sensors, transistor gate lengths is a actuators, and mixed-signal control loops in order to improve their dramatic increase in intraperformance yield. wafer and intradie process VHaralampos-G. Stratigopoulos, TIMA Laboratory, and variability (as measured by Alberto Valdes-Garcia, IBM T. J. Watson Research Center standard deviation) in critical device parameters such as threshold voltage, h ADVANCES IN INTEGRATED circuit technologies effective channel length, etc. Figure 1 plots intrahave increasingly enabled the single-chip integra- wafer variability for several process nodes based on tion of multiple analog and digital functions, result- lithographic limitations published by the ITRS [3] ing in the development of complex mixed-signal along with projections of yield reduction in these systems-on-a-chip (SoCs). In particular, scaling nodes from Monte Carlo simulations corroborated channel lengths in CMOS processes to 32 nm and by measurements of representative circuits [4]. In below has pushed the fmax and ft of silicon CMOS aggregate, variability in several parameters simultatransistors in excess of 230 and 440 GHz, respec- neously can greatly exacerbate circuit performance tively [1] and the fmax and ft of SiGe BiCMOS transis- degradation. Such variation can have significant tors in excess of 350 and 300 GHz, respectively [2]. impact on digital circuits, but the effect is magniIn this regime, it is possible to realize state-of-the-art fied for analog and mixed-signal circuits due to the RF performance on the same platform used to fa- heightened sensitivity of such designs to device bricate digital processors and dense memory cores. mismatch and the integration of numerous individOn the other hand, pattern variations partly due to ual subblocks that can vary greatly in noise characthe complex masks needed for subwavelength litho- teristics, operating frequency, etc. Consequently, graphy and random variables such as dopant loca- mixed-signal circuit performance yield degrades tion effects become statistically significant at these more rapidly with technology scaling than with digital circuits. To deal with the impact of variability in advanced technologies, designers often must conservatively Digital Object Identifier 10.1109/MDT.2012.2226014 accommodate worst-case corner case simulations Date of publication: 23 October 2012; date of current version: and relax target performance specifications to 17 January 2013.

Gregory Creech Ohio State University Jay Rockway SPAWAR Systems Center Pacific

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Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC

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Figure 1. Variability in critical transistor parameters for submicron process nodes plotted along with the associated impact on performance yield for digital and mixed signal circuits [3], [4].

guarantee a sufficient postfabrication parametric yield. These traditional corner-based design techniques require coverage of an extensive and exponentially growing parameter space that becomes intractable for large designs. Furthermore, efforts to control variability through aggressive fabrication process management or extensive Design-for-Yield (DFY) procedures are costly and ultimately limited in effectiveness [5]. An alternative approach advocated in the Self-HEALing Mixed Signal Integrated Circuits (HEALICs) program initiated by the authors is to recover lost performance by employing on-chip sensors (meters), actuators (knobs) and analog/digital control loops that measure the effects of device variability in situ and consequently adjust tunable circuit parameters to drive the chip towards a more optimal performance point. This control circuitry can be applied at both the sub-block and system level allowing the designer to focus on performance goals and not on yield related issues. As with any control system, challenges related to stability, response times, system bandwidth, etc. cannot be overlooked when implementing self-healing, and overcoming these challenges while maintaining performance has been an important aspect of the program. Further-

more, HEALICs design teams must also address the possibility that process variability adversely impacts the self-healing circuitry itself, and compensation for this effect has been a particular point of emphasis. Calibration techniques for mixed-signal circuits such as analog-to-digital converters (ADCs) have been studied extensively; however, they typically focus on fully digital techniques that rely on known-good states stored in on-chip memory [6]. Furthermore, analog calibration techniques have been investigated for individual circuit blocks [7], [8], but they have not been studied extensively for full SoC applications. HEALICs technology combines analog and digital techniques for low-power overhead, embedded comprehensive healing for SoCs that compensates not only for process variation, but also for the extreme environments and long operational lifetimes experienced by the Department of Defense (DoD) electronic systems, as well as other systems: aviation, automotive, industrial automation, etc. For this reason, we anticipate that the technology developed under this program will greatly enhance long-term reliability in addition to improving performance yield.

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Table 1 HEALICs program goals for self-healing.

Program objectives and plan


To measure the efficacy and power efficiency of self-healing, the program design teams have targeted the yield-improvement and power consumption overhead goals described in Table 1. Performance yield is defined as the percentage of die per wafer that meets or exceeds a set of predefined circuit performance metrics. The performance yield for the baseline (or nonself-healing) die is calculated using the following formula: Baseline Performance Yield DBaseline NBaseline (1)

formula used for calculating posthealing performance yield and accounting for self-healing area overhead: Posthealing Performance Yield %PosthealingYield NHEALICs NBaseline (3)

where DBaseline is the number of baseline die that meet or exceed the same set of performance metrics and NBaseline is the maximum number of baseline die that can be fabricated on a single wafer. Without selfhealing, baseline die are expected to yield poorly if held to the same performance standards as the selfhealing chips. In most cases, the defined performance criteria exceed state-of-the-art for each design. In Phase I, the program targeted mixed-signal cores or sub-blocks, and in Phase II the program targets larger system-on-a-chip designs. Posthealing performance yield can be calculated using: Posthealing Performance Yield DHEALICs NBaseline (2)

where DHEALICs is the number of self-healing die per wafer that meet or exceed all metrics. By dividing DHEALICs by NBaseline, the performance yield is subject to an area overhead correction to ensure that the portions of the chip that are exclusively for selfhealing do not consume an excessive fraction of the die area. Combining (1) and (2) yields the following

where NHEALICs is the number of self-healing die that can be fabricated on a single wafer and %PosthealingYield is the percentage of self-healing die that meet all defined metrics. In some cases, self-healing can enable a smaller chip to meet the performance metrics compared to a baseline design, i.e., NHEALICs > NBaseline . In this case, (3) allows for the performance yield to exceed 100%, which can be interpreted as reducing the fabrication costs for a given part. While not an explicit program requirement, we also expect that self-healing will result in a reduction of performance variance as measured over the full set of die, indicating that techniques are truly compensating for process variability and not for poor initial design or inaccurate device models. This effect will be readily apparent in the yield measurements reported in the following section of this paper. Self-healing designs are also required to incur minimal power consumption overhead relative to the baseline design. Power overhead may be measured at an appropriate healing duty cycle if selfhealing is not expected to be continuously operating. While the extreme scaling of silicon transistors is primarily responsible for the variability described as the motivating factor for self-healing technology, it simultaneously makes it possible to incorporate substantial processing capabilities on-chip for selfhealing at low area and power overhead. To date, the HEALICs program has demonstrated advancements in self-healing yield and performance

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Table 2 Summary of target self-healing demonstration circuits.

in RF transceivers and subblocks, including ADCs, phase-locked loops (PLLs), and power amplifiers (PAs). These designs have been fabricated in processes ranging from 180 nm SiGe BiCMOS to 32 nm silicon-on-insulator (SOI) CMOS, demonstrating the efficacy of self-healing across a range of technologies and variability effects. Table 2 summarizes the individual program design teams and the mixed-signal SoCs they have targeted for demonstrating their self-healing methods. This paper will describe results obtained by the IBM, Raytheon, and UCLA teams, however, several other important self-healing research activities in this program are not covered in detail because of space constraints. Examples include self-healing image reject mixers [9] and LNAs [10] developed at Georgia Tech (a member of the NGES team), novel I-gate MOSFETs for self-healing circuits [11] developed at University of Texas at Dallas (a member of the IBM team), and built-in self-test synthesis techniques for self-healing [12] developed at Auburn University (a member of the BAE Systems team).

Recent accomplishments
This section will cover the measurement and yield improvement results for several of the fabricated and measured Phase I designs.

Self-healing PA and PLL designs A research team led by IBM has demonstrated a self-healing 28 GHz PA in 45 nm SOI and a selfhealing 2127 GHz PLL in 32 nm SOI. Together, these components were designed for a Ka-band radio transceiver. The high-level schematic of the self-healing PA designed by CalTech is shown in Figure 2 [13]. The onchip integrated sensors include RF power sensors at the input and output to estimate gain, junction temperature sensors to assist with the estimation of power added efficiency (PAE), and dc current sensors to determine power consumption. The power sensor is calibrated by measuring the output of a few representative die and calculating a ratio between sensed power and actual power. These data are included in the healing algorithm for each of the chips. On-chip control knobs include bias actuation mechanisms at each of the PA stages and tunable transmission lines at the PA output used to adjust matching impedances. An embedded fully custom microprocessor is used to determine the knob settings necessary to minimize power consumption for a desired output power (thus maximizing PAE). The control algorithm affords a level of flexibility in operation and the target output power can be designated at run time. Through this control loop, the PAE is increased from 5.6% in the

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Figure 2. Self-healing PA: (a) high-level schematic and (b) die photograph (1.8 mm 0 1.7 mm).

baseline case to 7.3% in the healed state. PAE is defined as: PAE 100 RF Output Power RF Input Power dc power consumption: (4)

Furthermore, the 1 decibel compression point and the gain are increased from 11.3 to 13.8 dBm and from 20.3 to 23.7 dB, respectively. This PA chip was also an excellent platform for investigating the potential efficacy of self-healing for

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Figure 3. Self-healing result for intentionally damaged PA: (a) no damage; (b) 1/8 stage removed; (c) 1/4 stage removed; and (d) 1/2 of stage removed. Micrographs of PA: (e) before and (f) after damage.

improving RF/mixed-signal circuit reliability. To this end, CalTech performed an extreme test of reliability healing by intentionally and sequentially inducing damage in one of the PA output stages through the use of laser ablation and initiating the healing algorithm after each stage of damage. Notably, self-healing was capable of recovering significant amounts of lost output power by autonomously adjusting the output matching to compensate for the change in impedance loading. A set of curves showing output power data for the undamaged and for three successive ablations is shown in Figure 3 along with before and after photos of the PA. Ultimately, the self-healing algorithm is shown to recover up to 4.8 dBm of output power compared to the baseline settings. Concurrent with the design of the PA, the IBM team designed and tested a 25-GHz self-healing PLL fabricated in 32 nm SOI technology. The PLL architecture was a hybrid analog/digital design with proportional and integral paths following the phase/frequency detector. A peak detector at the output of the oscillator acts as the primary sensing path for the self-healing algorithm, which, in this case, is primarily responsible for reducing phase

noise at a 10-MHz offset from the carrier to G124 dBc/Hz. The bias values and VCC are measured along with the frequency to complete the in situ virtual phase noise model of the PLL performance [14]. During testing, a quadratic relationship is derived that relates the output amplitude, output frequency, bias voltage, bias current, tuning band, and VCC value to the measured phase noise. Once this equation is determined, the coefficients for each term are stored in on-chip memory. After self-healing is initiated, the knob settings are stepped through incrementally. An on-chip processor then evaluates the stored equation for the sampled sensor values and returns an estimate of the phase noise. If phase noise is at a minimum, the algorithm stops and the knob settings are held constant. The algorithm is implemented completely on-chip in a 16-bit arithmetic logic unit which uses a 32-word data memory and a 256-word instruction memory for low healing overhead. Using this algorithm, the performance yield of the PLL is improved from $20% in the baseline case to 100% posthealing for 55 measured die. Healing power overhead was $10% and healing area overhead was 12.7%.

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Self-healing pipelined ADC Researchers from UCLA have pursued the design of a self-healing ultralow-power pipelined 1 Gsps ADC with a flash output stage in 65 nm CMOS [15]. Therefore, canonical selfhealing involved adding control loops and processors to the baseline chip with the constraint of minimizing the overhead created by these auxiliary blocks. For this ADC design, however, the application of self-healing was found to significantly decrease the size of the yielding part relative to a nonyielding baseline part by enabling the use of minimum sized devices in critical analog parts of the design. Flash ADCs are well known for realizing extremely high sample rate data converters at the expense of high comparator count for high numbers of digital output bits. Furthermore, these comparators exhibit significant capacitance and gain mismatch in deeply scaled CMOS that would otherwise be an attractive fabrication process for such ADCs. One method to combat the mismatch (the baseline approach) is to use devices with larger than minimum dimensions that exhibit lower variability standard deviation; but this obviates the speed, the size, and Figure 4. (a) High-level ADC schematic showing the self-healing required the power advantages of using for each stage. Inset: op-amp comparator schematic and (b) comparison 65 nm or better technology. of self-healing design to recently published ADCs in various submicron Alternatively, a self-healing alCMOS technologies. (All data points except for self-healing points gorithm designed to mitigate compiled from [16]). the effect of comparator mismatch would enable the use of minimum size devices. Specifically, in this imple- ing four stages. The final three stages have sufficient mentation, capacitance and gain mismatch healing performance margin to not require additional is employed in the 4-bit input stage and capaci- healing. Figure 4(a) shows the general ADC tance mismatch healing is employed in the follow- architecture schematic.

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Through this approach, the ADC demonstrated 56.7 dB of signal-to-noise-and-distortion ratio (SNDR) equivalent to 8.38 effective bits with a 491 MHz input signal sampled at 1 Gsps. More importantly, the power consumption was merely 33 mW, resulting in an ADC figure-of-merit (FOM) of $99 fJ/conversion step. The ADC FOM is calculated as follows: FOM 2ENOB Power : Sampling Frequency (5)

Compared to a baseline design utilizing larger comparator transistors, this design was 41 smaller and $100 less power consumptive. A conservative clock tree design consumed approximately a third of the power and could have been further reduced with aggressive design. Furthermore, simulation results indicate approximately a 16% reduction in the FOM if the design was ported to 45 nm technology. A plot comparing this result to others in recent literature is shown in Figure 4(b).

Self-healing radar receivers In addition to subblocks dedicated for use in communications systems, self-healing has been shown to dramatically increase performance yield for DoD-relevant radar and EW receivers as well. For example, a team led by Raytheon developed a 618 GHz self-healing radar receiver with several onchip sensors and actuators designed to reduce I/Q phase mismatch, PLL output spur level, and gain fluctuations across the spectral field of regard [17]. Figure 5a shows the design schematic. Unique to this team, an on-board ARM processing core was synthesized and fabricated to run a modified Nelder-Mead optimization algorithm used to efficiently minimize mismatch, suppress spurs and flatten gain response. The ARM core utilizes 130.4 KB of memory, but only 36 KB are specific to the healing circuitry. In this case, HEALICs techniques are shown to take advantage of baseline processing and memory capabilities to reduce healing area and power overhead. To reduce phase mismatch, for example, an auxiliary mixer is used to produce a dc value proportional to the amount of phase offset between the I and Q paths. Feedback to variable amplifiers in each path are used to fine tune the phase offset, and the Nelder-Mead algorithm is used to establish values for each amplifier that minimizes mismatch. The search routine is applicable to

bound-constrained and discretized optimization problems and has shown efficacy for the types of self-healing required for the radar receiver designed in this effort. Furthermore, Nelder-Mead is particularly robust in the presence of noisy measurement data, which is expected from the low-power sensors typically incorporated in self-healing designs. To heal PLL spur levels, a similar algorithm is used with slightly different knobs and sensors. A power detector on the output is fed to the algorithm, which independently sets two knobs: charge injection on the VCO control line and a trigger setting to establish the precise timing of the charge injection. Finally, to heal gain flatness, the output power sensor is monitored and the tunable amplifiers are further adjusted while maintaining optimum phase matching. Figure 5b shows histograms for healed mismatch and gain flatness. The area shaded in green represents the performer-defined metric that sets the standard for yield in the case of this design. For both of these metrics, yield was improved from 0% in the baseline case to 100% in the healed case. The Raytheon team is also investigating the effects of ageing on circuits, which is of particular interest given that some defense, as well as commercial, electronic systems are fielded for decades. The main cause of aging in PMOS is negative bias temperature instability (NBTI) which shifts the threshold voltage over time and is especially deleterious for gate lengths shorter than 100 nm. Hotcarrier injection (HCI) is an important in ageing mechanism for NMOS and has an amplified impact on mixed signal circuits compared to pure digital circuits. NCSU, a member of the Raytheon team, is developing techniques for the purposes of designing self-healing knobs and sensors specifically for ageing and has published initial results in [18].

Self-healing 60 GHz radio transceiver Another research group at UCLA has successfully incorporated self-healing sensors, actuators and control loops to substantially improve the performance yield of a 60 GHz, 4 Gbps communications transceiver fabricated in 65 nm CMOS [19]. The schematic for this design, identifying additions specific to self-healing, and the photograph of the fabricated die are shown in Figure 6. Circuitry dedicated solely to self-healing represented 8% of the total area. Likewise, the power consumption of these blocks amounted to only 3.7%

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Figure 5. (a) Radar receiver schematic showing location and connections for self-healing sensors and knobs; histograms showing improvement in performance yield for phase error (b) and gain flatness (c).

of the chips total. On-chip sensors include an envelope sensor for tracking the output spectrum; a temperature sensor for estimating the kT noise level; a power sensor for estimating the path gain; and an auxiliary ADC for quantizing the sensor outputs. Selfhealing control knobs include phase offset and dc offset for the individual I/Q paths; PA and mixer current biases; variable gain LNAs; and an auxiliary DAC for generating control signals. The transceiver utilizes a loop-back healing approach, where the Tx is used to drive the Rx for the purposes of measuring the radios performance. This minimizes the need for off-chip calibration of the on-chip sensors. The

central component for mediating the self-healing algorithms is the parameter estimator (PE) block shown in the block diagram in Figure 6a. The (PE) comprises a 128-point FFT processor synthesized in digital logic along with spectrum magnitude estimation for both the I and Q channels. The PE is responsible for estimating LO leakage power, image tone power, among other parameters and consumes only 0.56 mm2 of die area and 4.8 mW. The DAC controller, meanwhile, provides test tones for measuring circuit response to 1-tone and 2-tone tests. Critical performance parameters for this design include receiver noise figure; transmitter linearity;

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Figure 6. 60 GHz, 4 Gbps self-healing transceiver: (a) high-level schematic; (b) die photograph (4 mm 4 mm); and performance yield enhancement for (c) image tone rejection and (d) receiver NF.

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and image tone power. The target noise figure was 6 dB, and self-healing was able to correct the baseline value of 9.4 dB to 4.9 dB for 100% of the chips. Likewise, the target Tx third-order output intermodulation product level (OIM3) and the target image tone rejection level were both 40 dBc, and the on-chip algorithm was able to correct baseline values of 32.4 dBc and 32.8 dBc to 42.6 dBc and 41.8 dBc, respectively, on 100% of the die. To heal the image tone power, the envelope sensor captures the spectrum of the transmitter output and the PE estimates the magnitude of the power in each of the FFT frequency bins. After the estimation is performed, the phase offset, relative gains and dc offsets between the I/Q channels are adjusted to minimize the power at the image frequency. A coarse/fine search algorithm is implemented in custom logic to close the control loop and minimize the

measured image power. Likewise, to heal the noise figure, the temperature sensors are sampled by the auxiliary ADC to estimate the current kT level. Given the relationship between stage gain and overall noise figure, the NF can be optimized by adjusting the gain in each of the three stages. Figure 6c and d show histograms for each of these performance parameters comparing the healed state to the baseline state. Since the area of the baseline design is constrained by the number of bond pads and since the self-healing circuitry fit in vacant parts of the die, there is no area overhead correction necessary for this part.

IN SITU SELF-HEALING has been shown to dramatically improve the performance yield of RF/mixedsignal designs at deep-submicron nodes. A wide range of cores and subblocks from PAs to entire

Table 3 Summary of yield improvement through self-healing for the circuits described in this paper.

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transceivers have been co-integrated with sensors, actuators, and control loops, resulting in the restoration of lost performance at low power and die area overhead. A summary of some of the performance yield improvement capabilities highlighted in this paper is included in Table 3. Activities that promise to extend these capabilities to the system-on-a-chip level are already underway, and a repository of self-healing IP has been established at the Air Force Research Laboratory to facilitate a more widespread adoption of these techniques throughout the DoD design community.

[4] K. Bernstein et al. High-performance CMOS variability in the 65-nm regime and beyond, IBM J. Res. Dev., vol. 50, no. 4.5, pp. 433449, Jul. 2006. [5] J. Hartmann, Towards a new nanoelectronic cosmology, in Proc. 2007 IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 1115, 2007, pp. 3137. [6] J. A. McNeill et al. FSplit ADC_ calibration for all-digital correction of time-interleaved ADC errors, IEEE Trans. Circuits Systems II: Expr. Briefs, vol. 56, no. 5, pp. 344348, May 2009. [7] Y. Liu et al. CMOS RF power amplifier variability and reliability resilient biasing design and analysis, IEEE Trans. Electron Devices, vol. 58, no. 2, pp. 540546, Feb. 2011. [8] K. Jayaraman et al. Design and analysis of 160 GHz,

Acknowledgments
The authors would like to thank all of the performers on the HEALICs program for their efforts towards achieving the program goals; in particular, those who contributed to the work outlined in this paper: principal investigators Dr. Jose Tierno and Mr. Daniel Friedman from IBM, Prof. Behzad Razavi from UCLA, Mr. Gerry Sollner from Raytheon, Prof. Frank Chang also from UCLA, and their teams. The HEALICs program was developed at and funded by the Defense Advanced Research Projects Agency. The work presented in this paper was supported through Air Force Contracts FA8650-09-C-7924, FA8650-09-C-7925, and FA8650-09-C-7926; Navy grants N66001-09-1-2029 and N66001-09-1-2030; and Navy contract N66001-09-C-2023. The views, opinions, and/or findings contained in this article are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense. h

RF CMOS peak detectors for LNA calibration, in Proc. 2009 Int. Symp. VLSI Design, Automat. Test, Apr. 2830, 2009, pp. 311314. [9] P. K. Saha et al. An adaptive, wideband SiGe image reject mixer for a self-healing receiver, in Proc. 2011 IEEE Bipolar/BiCMOS Circuits Technol. Meeting (BCTM), Oct. 911, 2011, pp. 99102. [10] D. C. Howard et al. A UWB SiGe LNA for multi-band applications with self-healing based on DC extraction of device characteristics, in Proc. 2011 IEEE Bipolar/BiCMOS Circuits Technol. Meeting (BCTM), Oct. 911, 2011, pp. 111114. [11] C. Wu et al. I-gate body tied silicon-on-insulator MOSFETs with improved high frequency performance, IEEE Electron Device Lett., vol. 21, no. 1, pp. 4345, Jan. 2011. [12] G. J. Starr et al. Automated generation of built-in self-test and measurement circuitry for mixed-signal circuits and systems, in Proc. 24th IEEE Int. Symp. Defect Fault Tolerance in VLSI Syst., Oct. 79, 2009, pp. 1119. [13] S. M. Bowers et al. A fully-integrated self-healing power amplifier, in Proc. 2012 RFIC Symp., Montreal, PQ, Canada, Jun. 2012. [14] S. Yaldiz et al. Virtual phase noise sensor for self-healing voltage controlled oscillators, in Proc. 2011 Government Microcircuit Applicat. Critical Technol. Conf., Mar. 2011. [15] B. D. Sahoo et al. A 10-Bit 1-GHz 33-mW CMOS ADC, in Proc. 2012 IEEE Symp. VLSI Technol., Jun. 2012. [16] J. Mulder et al. An 800 MS/s dual-residue pipeline ADC in 40 nm CMOS, in Proc. 2011 IEEE Int. Solid-State Circuits Conf., Feb. 1923, 2011, pp. 184186.

h References
[1] C.-H. Jan et al. RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications, in Proc. 2010 IEEE Int. Electron Devices Meeting (IEDM), Dec. 68, 2010, pp. 27.2.127.2.4. [2] M. Khater et al. SiGe HBT technology with fmax =fT 350=300 GHz and gate delay below 3.3 ps, in Proc. 2004 IEEE Int. Electron Devices Meeting (IEDM), Dec. 1315, 2004, pp. 247250. [3] International Technology Roadmap for Semiconductors, 2011 Edition, 2011.

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[17] G. Sollner et al. Tunable receiver for 618 GHz with autonomous self-healing, in Proc. 2011 Government Microcircuit Applicat. Critical Technol. Conf., Mar. 2011, pp. 4952. [18] M. B. Yelten et al. Analog Negative Bias Temperature Instability (NBTI) monitoring circuit, IEEE Trans. Device Mater. Reliab., vol. 12, no. 1, pp. 177179, Mar. 2012. [19] A. Tang et al. A low overhead self-healing embedded system for ensuring high performance yield and long-term sustainability of a 60 GHz 4 Gbps radio-on-a-chip, in Proc. 2012 IEEE Int. Solid-State Circuits Conf. (ISSCC), Feb. 1923, 2012.

correcting RF/mixed-signal circuits; heterogeneous integration; and sensor microsystems. He has a PhD in electrical engineering from the University of Michigan in 1998. He is a senior member of the IEEE.

Kari Groves is an RF Engineer with the Air Force


Research Laboratory.

Tony Quach is an RF Engineer with the Air Force Research Laboratory. Len Orlando is an RF Engineer with the Air Force Research Laboratory. Aji Mattamana is an RF Engineer with the Air
Force Research Laboratory.

Christopher Maxey is an Associate with Booz Allen Hamilton. His research interests include mixedsignal and RF circuits. He has a Masters degree in electrical engineering from Virginia Polytechnic Institute and State University (Virginia Tech) in 2004. He is a member of the IEEE. Sanjay Raman is a Program Manager at DARPA,
currently on assignment from Virginia Polytechnic Institute and State University (Virginia Tech), where he is a Professor of Electrical and Computer Engineering. His research interests include siliconbased RF/microwave millimeter-wave circuits; self-

Gregory Creech is recently retired from the Air Force Research Laboratory. He is now with Ohio State University. Jay Rockway is with SPAWAR Systems Center
Pacific.

h Direct questions and comments about this article


to Christopher Maxey, Booz Allen Hamilton; maxey_christopher@bah.com.

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