Boolean Algebra and Logic Gates.

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY
EDAPALAYAM, REDHILLS, CHENNAI-52.

EC2302-DIGITAL ELECTRONICS

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R.RAMADHURAI B.E.,M.TECH AP/ECE

SYLLABUS
UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
Minimization Techniques: Boolean postulates and laws De-Morgans Theorem - Principle of
Duality - Boolean expression - Minimization of Boolean expressions Minterm Maxterm - Sum of
Products (SOP) Product of Sums (POS) Karnaugh map Minimization Dont care conditions -
Quine-McCluskey method of minimization. Logic Gates: AND, OR, NOT, NAND, NOR, ExclusiveOR
and ExclusiveNORImplementations of Logic Functions using gates, NANDNOR implementations
Multi level gate implementations- Multi output gate implementations. TTL and CMOS Logic and
their characteristics Tristate gates.
UNIT II COMBINATIONAL CIRCUITS
Design procedure Half adder Full Adder Half subtractor Full subtractor - Parallel binary
adder, parallel binary Subtractor Fast Adder - Carry Look Ahead adder Serial Adder/Subtractor -
BCD adder Binary Multiplier Binary Divider - Multiplexer/ Demultiplexer decoder - encoder
parity checker parity generators - code converters - Magnitude Comparator.
UNIT III SEQUENTIAL CIRCUITS
Latches, Flip-flops - SR, JK, D, T, and Master-Slave Characteristic table and equation Application
table Edge triggering Level Triggering Realization of one flip flop using other flip flops serial
adder/subtractor- Asynchronous Ripple or serial counter Asynchronous Up/Down counter -
Synchronous counters Synchronous Up/Down counters Programmable counters Design of
Synchronous counters: state diagram- State table State minimization State assignment -
Excitation table and maps-Circuit implementation - Modulon counter, Registers shift registers -
Universal shift registers Shift register counters Ring counter Shift counters - Sequence
generators.
UNIT IV MEMORY DEVICES
Classification of memories ROM - ROM organization - PROM EPROM EEPROM EAPROM, RAM
RAM organization Write operation Read operation Memory cycle - Timing wave forms
Memory decoding memory expansion Static RAM Cell- Bipolar RAM cell MOSFET RAM cell
Dynamic RAM cell Programmable Logic Devices Programmable Logic Array (PLA) -
Programmable Array Logic (PAL) - Field Programmable Gate Arrays (FPGA) - Implementation of
combinational logic circuits using ROM, PLA, PAL

UNIT V SYNCHRONOUS AND AYNCHRONOUS SEQUENTIAL CIRCUITS
Synchronous Sequential Circuits: General Model Classification Design Use of Algorithmic State
Machine Analysis of Synchronous Sequential Circuits. Asynchronous Sequential Circuits:Design of
fundamental mode and pulse mode circuits Incompletely specified State Machines Problems in
Asynchronous Circuits Design of Hazard Free Switching circuits. Design of Combinational and
Sequential circuits using VERILOG


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UNIT I MINIMIZATION TECHNIQUES AND LOGIC GATES
TWO MARKS
1. Why binary number system is used in digital system?
Digital system is a system that manipulates discrete elements of information. Discrete
elements of information are represented with groups of bits called binary codes. Therefore binary
number system is used in digital system.

2. Represent the following numbers in 2s complement form: + 3, + 25,- 5, -11.
No.s 2s complement form (with 8 binary digits)
+3 00000011
+25 00011001
-5 11111011
-11 11110101

3. Define the laws of Boolean algebra. (April 2003)
a. Associative law: A binary operator - on a set S is said to be associative whenever
) ( ) ( z y x z y x - - = - - for all s z y x e , ,
b. Commutative law: A binary operator - on a set S is said to be associative whenever
) ( ) ( x y y x - = - for all s y x e ,
c. Distributive law: If - and - are two binary operators on a set S , - is said to be
distributive over - whenever
) ( ) ( ) ( z x y x z y x - - - = - - for all s z y x e , ,

4. If A and B are Boolean variables check if
) ( ) ( ) ( ) ( B B B B A A A A + = - .
L.H.S
= ) ( ) ( A A A A -
= ) 1 0 ( 1 ) ( = A A
= 1 .(i)
R.H.S
) ( ) ( B B B B + =
) ( 1 B B =
= ) ( 1 BB B B +
) ( 1 B B =
) 1 ( 1 =
) 0 ( 1 = =1
5. For a switching function of n variables, how many distinct minterms and maxterms are
possible?
For a switching function of n variables, 2
n
distinct minterms and maxterms are possible.
6. Find the octal equivalent of the decimal number 64.
Soln:
8 64
8 8 0
1 0
6410 = (100)8

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7. Find the hexadecimal equivalent of the octal number 153.4.
Soln:
(153.4)8 = 001101011.100
= 0000 0110 1011.1000
= (6 B . 8)16

8. Show that the excess-3 code is self-complementing.
Self-complementing property is that the 9s complement of each decimal digit is obtained by
forming the 1s complement (changing 1s to 0s and 0s to 1s in the code) of its respective code
group. Eg: 2421 codes, Excess-3 code.
Eg: Decimal 395 in excess3 code = 0110 1100 1000
The 9s complement 604 is represented as = 1001 0011 0111

9. Convert (2101)3 to base 5 number.
Soln:
(2101)3 = 2 x 3
3
+ 1 x 3
2
+ 0x 3
1
+ 1 x 3
0

= 2 x 27 + 1 x 9 + 0 + 1
= (64)10

(64)10 = 5 6 4
5 1 2 -4
2 -2
(64)10 = (224)5

10. Subtract the unsigned number (10101)2 from (11011)2 using ones complement and 2s
complement.
Step (i):
M = 11011 N=10101
2s complement of N,
1s complement +1 =01010
1
01011
Step (ii): M + 2s complement of N,
= 11011
01011
1 00110
(a) If carry occurs means discard the carry,
Ans: (110)2
11. Define canonical form. Express AC C B F + = in a canonical SOP form.
C B B A C B A A F ) ( ) ( + + + =
C B B A C B A A ) ( ) ( + + + =
C B A ABC C B A C AB + + + = or
= m6 + m2 + m7 + m5

12. Determine the decimal equivalent of binary 0.1101 (April 2004)
(0.1101)2 = 1x 2-
1
+ 1 x 2-
2
+ 0 x 2-
3
+ 1 x 2-
4

= (1/2) + (1/4) + (1/16)
= 0.5 + 0.25 + 0.0625
= 0.8125

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13. Add (1A8)16 and (67B)16.
Soln:
1 A 8 +
6 7 B
8 2 3
= ( 8 2 3)16

14. State two absorption properties of Boolean algebra.
a) x + xy = x
b) x (x + y) = x

15. Perform 2s complement subtraction of 010110 100101.
Soln:
M = 10110 N = 100101
Step1: 2s complement of N,
011010
1
011011
Step 2: M + 2s complement of N,
M = 010110
2s complement of N = 011011
= 110001
No carry occurs, therefore 2s complement of (110001)
= 001110
= 1
= 001111
Ans: - (1111)2

16. Convert (FACE)16 to base 8 number.
(FACE)H
= F (15)x 16
3
+A (10) x 16
2
+ C(12)x 16
1
+ Ex 16
0

= 61440 + 2560 + 192 + 14
= (64206)10

17. Add the decimals 67 and 54 using 8421 BCD code. (April 2005)
Soln:
6 7 = 0110 0111
5 4 = 0101 0100
Binary Sum = 1011 1011
BCD Sum = 0110 0110
1 0010 0001 = 121

18. Simplify the following Boolean Expression: abc c b a c b a + +
Soln:
= abc c b a c b a + +
= ) ( b b ac c b a + +
= ac c b a + ) ( b b + =1

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19. How will you use a four input NOR gate as a two input NOR gate?
By connecting unused inputs to logic 0 we can use 4 input NOR gate as a two input NOR gate.

20. How will you use a 4 input NAND gate as a 2 input NAND gate?
By connecting unused inputs to logic 1 we can use 4 input NAND gate as a two input NAND gate.

21. Show that NAND connection is not associative?
If NAND connection is not associative then we have to prove
Z B A . ) . ( - - = ) ( Z B A - -
L.H.S:
Z B A . ) . ( - - = Z X - Let X = B A-
= Z AB +
= Z AB +
R.H.S
) ( Z B A - - = Y A- Let Y= Z B-
= ) (BZ A+
L.H.S = R.H.S

22. Show that a positive logic NAND gate is same as a negative logic NOR gate.
Positive logic NOR gate:

Choosing the low level L to represent logic 1 defines a negative logic system.
Negative logic NOR gate: Positive logic NAND gate.

From the truth table we can show that a positive logic NAND gate is same as a negative logic
NOR gate.

23. How many inputs are needed for the expression?
EF D AC D B A W + + =
Six inputs are needed for the expression.

24. Define noise margin.
Noise margin is the maximum external noise voltage added to an input signal that does not
cause an undesirable change in the circuit output.

A B
(A+B)
0 0 1
0 1 0
1 0 0
1 1 0

A B
(A+B)
1 1 0
1 0 1
0 1 1
0 0 1

A B
(A.B)
0 0 0
0 1 1
1 0 1
1 1 1


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25. What are universal gates? (Nov 2004)
NAND and NOR are universal gates.
26. Implement EXOR gate using only NAND gates. OR Realize the function
f(A,B) = B A B A + by using only NAND gates.

27. Define fan in.
Fan in is the number of inputs available in a gate.

28. Obtain 3 level NOR-NOR implementation of f (a,b,c) = (ab+cd)ef.

29. What is tri-state logic?
Tri state logic is a logic that exhibits three states. Two of the states are signals equivalent to logic 1
and 0 as in a conventional state. The third state is a high-impedance state.


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30. Define power dissipation and propagation delay.
Power dissipation is the power consumed by the gate that must be available from the power supply.
Propagation delay is the average transition delay time for the signal to propagate from input to
output.

31. What happens when all the gates in a two level AND-OR gate network is replaced by NOR
The output will change. We will get complemented output when all applied inputs are
complemented.

32. Implement ) ( C B A AB Y + + + = using NAND gates only.
) ( C B A AB Y + + + =
= C B A B A + + +
= 1

33. Distinguish between positive logic and negative logic.
In binary logic, two voltage levels represent the two binary digits, 1 and 0.If the higher of
the two voltages represents a 1 and the lower voltage represents a 0, the system is called
a positive logic system. On the other hand, if the lower voltage represents a 1 and higher
voltage represents a 0, we have a negative logic system.

34. Find the octal equivalent of hexadecimal number AB.CD
Soln:
AB.CD =1010 1011.1100 1101
= 010 101 011. 110 011 010
= (2 5 3 . 6 3 2)8

35. Find the hexadecimal equivalent of decimal number 256.
(April/May -2003)
Soln:
16 256
16 16 0
1 0
25610 = 100H

36. What is mean by weighted and non-weighted coding?
Weighted Codes:
In weighted codes, each digit position of the number represents a specific weight. For
example, in decimal code, if number is 567 then weight of 5 is 100,weight of 6 is 10 and
weight of 7 is 1. In weighted binary codes each digit has a weight 8,4,2, or 1.The codes
8421
Non-Weighted codes:
Non-weighted codes are not assigned with any weight to each digit position, i.e., each digit
position within the number is not assigned fixed value. Excess-3 and grey codes are the
non-weighted codes.

37. Convert A3BH and 2F3H into binary and octal respectively.
Soln:
A3BH -- 1010 0011 10112 -- 50738
2F3H -- 0010 1111 00112 -- 13638

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38. Find the decimal equivalent of (123)9. (April / May -2004)
Soln:
(123)9 =1 x 9
2
+ 2 x 9
1
+ 3 x 9
0

= 81 + 18 +3
= (102)10

39. Encode the ten decimal digits in the 2 out of 5 code?

Decimal digit 2-out-of-5 code
0 11000
1 00011
2 00101
3 00110
4 01001
5 01010
6 01100
7 10001
8 10010
9 10100

40. Find the decimal equivalent of (346)7.
Soln:
(346)7 = 3x7
2
+ 4 x 7
1
+ 6 x 7
0

=(181)10

41. A hexadecimal counter capable of counting upto atleast (10000)10 is to be constructed.
What is the minimum number of hexadecimal digits that the counter must have?
Soln:
16 10000
16 625 - 0
16 39 - 1
16 2 - 7
(10000)2 = (2710)16
Counter must have minimum four hexadecimal digits.

42. Convert the decimal number 214 to hexadecimal.
Soln:
16 214
16 13 6
(D)
= (D6)16

43. Convert 231.34 to base 7.
(i) To decimal
231.34 = 2 x 4
2
+ 3 x 4
1
+ 1 x 4
0
+ 3 x 4-
1

= 32 + 12 + 1 + 0.75
= (45.75)10


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(ii) Integer Part to base 7
7 45
7 6 3
4510 = 637
(iii) Fractional Part:
0.75 x 7 = 5 0.25
0.25 x 7 = 1 0.75
0.75 x 7 = 5 0.25
0.25 x 7 = 1 0.75
=(0.5151)7
(45.75) = (63.5151)7

44. If A and B are Boolean variables and if A=1 and 0 = + B A , find B.
Given:
0 = + B A
Taking complement on both sides,
0 ) ( = + B A
A + B = 1
If A=1 then,
1 + B = 1
and therefore B can be either 0 or 1.

45. Express the switching function fAB = A in terms of minterms.
fAB = A
= A ) ( B B +
= AB + A B

46. Apply Demorgans theorems to simplify C B A+ .
C B A+ = C B A+
= ) ( C B A + -
= C A B A +

51. Express yz x + as the sum of minterms.
yz x + = ) ( ) )( ( x x yz z z y y x + + + +
= yz x xyz z y x z xy z y x xyz + + + + +
= yz x z y x z xy z y x xyz + + + +

47. What is prime implicant?
While eliminating the number of literals in Boolean expression by tabulation method the terms
that did not match during the process are called prime implicants.


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48. What are minterms and maxterms?
Each individual term in standard SOP form is called minterms and each individual term in
standard POS is called maxterm. With n variable/literal, there are 2
n
minterms and maxterms are
possible. Eg: For 3 variable, the minterms and maxterms are

49. Find the complement of x + yz
yz x + = ) ( yz x
= ) ( z y x +

50. State and prove consensus theorem.
Consensus theorem:
(i) yz z x xy + + = z x xy +
Proof:
yz z x xy + + = ) ( x x yz z x xy + + +
= yz x xyz z x xy + + +
= ) 1 ( ) 1 ( y z x z xy + + +
= z x xy +
(ii) ) )( ( ) )( )( ( z x y x z y z x y x + + = + + + it can be proved by duality.

51. Show that B A B A A + = + using the theorems of Boolean algebra.
L.H.S
= + B A A ) )( ( B A A A + +
= ) ( 1 B A+ -
= (A+B) This is R.H.S
Hence the proof.

Variable Minterms Maxterms
A B C mi Mj
0 0 0
C B A = m0
C B A + + =Mo
0 0 1
C B A = m1 C B A + + = M1
0 1 0
C B A = m2
C B A + + = M2
0 1 1
BC A = m3 C B A + + = M3
1 0 0
C B A = m4 C B A + + = M4
1 0 1
C B A = m5 C B A + + = M5
1 1 0
C AB = m6 C B A + + = M6
1 1 1 ABC = m7
C B A + + = M7

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52. Distinguish between Boolean addition and Binary addition.
Boolean Addition:
In Boolean addition when we add any two variables it produces HIGH output
when any one of the input is HIGH or all the inputs are HIGH. For Eg:
(i) 0+0 = 0
(ii) 0+1 = 1
(iii) 1+0 = 1
(iv) 1+1 = 1
Binary Addition:
In binary addition when we add numbers it produces the corresponding binary
sum. For Eg:
(i) 0+0 = 0
(ii) 0+1 = 1
(iii) 1+0 = 1
(iv) 1+1 = 10

16 MARKS
1. Prove that NOR gate is a universal gate. Also prove the same for NAND gate .
The NAND and NOR gates are known as universal gates, since any logic function can be
implemented by using NAND or NOR gates.

NAND GATE:
The NAND gate can be used to generate the NOT function, the AND function, the OR function
and the NOR function.
NOT function:
An inverter can be made from a NAND gate by connecting all of the inputs together.

Symbol: Truth table:

2m:
How can a NAND gate be used as an inverter
AND Function:
A AND function can be generated by simply inverting the output of the NAND gate.
Symbol:

Truth Table:
T A B Y=(AB)
0 0 0 1
1 1 1 0

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OR Function:
OR function can be generated by using only NAND gates . For that
Y = A + B
= A + B
= (A . B)

Symbol:

Truth Table:

NOR Function:
NAND gate can be used to generate NOR function. For that

Y = (A + B)
= A + B
= (A + B)
Symbol:

A B AB
0 0 0
0 1 0
1 0 0
1 1 1

A B
(AB) (AB)
0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

A B
A. B ((A.B)
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1


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Truth Table:

NOR GATE:
NOR gate is a universal gate. Since it can be used to generate the NOT,AND,OR, and NAND
functions.
NOT function:
An inverter can be made from a NAND gate by connecting all of the inputs together.
Symbol:

OR Function:
OR function can be generated by simply inverting output of NOR gate.
Symbol:

Truth Table:

A B A+B
0 0 0
0 1 1
1 0 1
1 1 1

AND Function:
AND function can be generated by using only NOR gates. For that
Y = A . B
= A . B
T A B Y=(AB)
0 0 0 1
1 1 1 0
A B
(A+B)
0 0 1
0 1 0
1 0 0
1 1 0

A B
(A+B) (A+B)
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1


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= (A + B)
Symbol:

Bubble at the input of NOR gate indicates inverted input
Truth Table:

NAND Function:
NAND function can be used to generate NOR function. For that
Y = (A . B)
= A + B
= (A + B)
Symbol:

Truth table

A B
A.B
0 0 0
0 1 0
1 0 0
1 1 1

A B
A+ B ((A+B)
0 0 1 0
0 1 1 0
1 0 1 0
1 1 0 1

A B
(A.B)
0 0 0
0 1 1
1 0 1
1 1 1


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2. State and prove the postulates, theorems of Boolean algebra (U.Q).
Huntington listed six theorems of Boolean algebra and four of its postulates.
Postulatepdfd*-
/fdrfsdcddfdsfgfgdfgfggdfgdfgdfgdfsefsdfsfsdfgdgdfgdgdgdfgdg

Postulate 2 :
(a) x + 0 = x
L.H.S
Let x = 0
0 + 0 = 0 x
Let x = 1
1 + 0 = 1 x
In both cases,
L.H.S = R.H.S
Therefore,
x + 0 = x
(b) x .1 = x
L.H.S
Let x = 0
0.1 = 0 x
Let x = 1
1 .1 = 1 x
In both cases,
L.H.S = R.H.S, Therefore, x .1 = x
Postulate 5:
(a) x + x = 1
L.H.S
Let x = 0
0 + 1 = 1 x
Let x = 1
1 + 0 = 1 x
In both cases,
L.H.S = R.H.S
Postulates and theorems of Boolean algebra.

Postulate 2 a) x + 0 = x b) x . 1 = x
Postulate 5 a) x + x= 1 b) x . x = 0
Theorem 1 a) x + x = x b) x.. x = x
Theorem 2 a) x + 1 = 1 b) x.. 0 = 0
Theorem 3 a) (x) = x
(Involution)
Postulate 3 a) x + y = y + x b)xy = yx
(Commutative)
Theorem 4 a) x +(y +z) = (x +y )+z b)x(yz) = (xy)z
(Associative)
Postulate 4 a) x (y +z) = xy +xz b) x+ yz = (x+y) (x+z)
(Distributive)
Theorem 5 a) (x +y)= xy b) (xy)= x+y
Demorgans
Theorem 6 a)x + xy = x b) x (x+y) = x


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Therefore,
x + x = 1
(b) x . x = 0
L.H.S
Let x = 0
0.1 = 0 x
Let x = 1
1 .0 = 1 x
In both cases,
L.H.S = R.H.S
Therefore, x . x = 0

Theorem 1:
a) x + x = x
L.H.S
x + x = (x+x).1 by postulate 2(b)
= (x+x).(x+x) 5(a)
= xx + xx + xx +xx = x x+ xx= x + xx 4(b)
= x + 0 5(b)
= x R.H.S 2(a)
b) x . x = x
L.H.S
x . x = xx + 0 by postulate 2(a)
= xx + xx by postulate 5(b)
= x(x + x) 4(a)
= x .1 5(a)
= x R.H.S 2(b)

Theorem 2
(a) x +1 = 1
L.H.S
x + 1 =1.(x+1) by postulate 2(b)
= (x+x) (x +1) 5(a)
= x + x.1 4(a)
= x + x 2(b)
= 1 5(a)
(b) x . 0 = 0
It is proved by duality.

Theorem 3:
From postulate 5, we have x + x = 1 and x . x = 0, which defines the complement of x.
The complement of x is x and also (x). Therefore, since the complement is unique, we have
that (x) = x


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Postulate 3: (Commutative)
(a). x + y = y + x
This states that the order in which the variables are ORed makes no difference in the output.

L.H.S R.H.S

b) x y = y x
The commutative law of multiplication states that the order in which the variables are ANDed
makes no difference in the output.

L.H.S R.H.S

Theorem 4, associative.
a) x + (y+z) = (x+y) + z
This law states that in the ORing of several variables, the result is the same regardless of the
grouping of the variables.

L.H.S R.H.S

x y z y+z x+(y+z) x y z x+y (x+y)+z
0 0 0 0 0 0 0 0 0 0
0 0 1 1 1 0 0 1 0 1
0 1 0 1 1 0 1 0 1 1
0 1 1 1 1 0 1 1 1 1
1 0 0 0 1 1 0 0 1 1
1 0 1 1 1 1 0 1 1 1
1 1 0 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1

x y yx
0 0 0
0 1 0
1 0 0
1 1 1
x y x y
0 0 0
0 1 0
1 0 0
1 1 1
x y x + y
0 0 0
0 1 1
1 0 1
1 1 1
x y y + x
0 0 0
0 1 1
1 0 1
1 1 1

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b) x(yz) = (xy)z
This associative law of multiplication states that it makes no difference in what order
the variables are grouped when ANDing several variables.

L.H.S R.H.S

x y z yz x(yz)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 1 0
1 0 0 0 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Postulate 4: distributive
a) x (y +z) = xy + xz
This distributive law states that ORing several variables and ANDing the result with a
single variable is equivalent to ANDing the result with a single variable with each of
the several variables and then ORing the products.

L.H.S R.H.S

b) x + yz = (x + y) (x + z)
L.H.S R.H.S
x y z yz x+yz x y z x+y x+z (x+y)(x+z)
0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 1 0
0 1 0 0 0 0 1 0 1 0 0
0 1 1 1 1 0 1 1 1 1 1
1 0 0 0 1 1 0 0 1 1 1
1 0 1 0 1 1 0 1 1 1 1
1 1 0 0 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1

x y z xy x(yz)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 0 0
1 1 0 1 0
1 1 1 1 1
x y z xy xz) xy+xz
0 0 0 0 0 0
0 0 1 0 0 0
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 0 0 0
1 0 1 0 1 1
1 1 0 1 0 1
1 1 1 1 1 1
x y z y+z x(y+z)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 1 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

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Theorem 5: Demorgans Theorem:
a) (x+y)=xy
The complement of a sum is equal to the product of the complements.
Logic diagram:

LHS RHS

b) (xy) = x+y
The complement of a product is equal to the sum of the complements.
Logic diagram:

LHS RHS

Theorem 6, Absorption
a) x + xy = x
x + xy = x.1+ xy by postulate 2(b)
= x(1+y) 4(a)
= x(y+1) 3(a)
= x.1 2(a)
= x 2(b)
b) x(x+y) = x
This can be proved by duality.
Other possible questions.
1. State and prove the postulates of Boolean algebra.
2. State and prove the theorems of Boolean algebra.
3. State and prove demorgans law.

x y x + y (x+y)
0 0 0 1
0 1 1 0
1 0 1 0
1 1 1 0
x y x y x. y
0 0 0 1 1
0 1 0 0 0
1 0 0 1 0
1 1 1 0 0
x y x y (xy)
0 0 0 1
0 1 0 1
1 0 0 1
1 1 1 0
x y x y x+ y
0 0 1 1 1
0 1 1 0 1
1 0 0 1 1
1 1 0 0 0

20

3. Mention the steps involved in converting AND-OR logic to NAND - NOR logic.
Steps:
1. AND-OR logic drawn.
2. If NAND hardware has been chosen, add bubbles on the output of each AND
gate, and bubbles on input side to all OR gates.
3. If NOR hardware has been chosen add bubbles on the output of each OR
gate, and bubbles on input side to all AND gates.
4. Add or subtract an inverter on each line that received a bubble in step 2 or 3.
5. Replace bubbled OR by NAND and bubbled AND by NOR.
6. Eliminate double inversions.
Eg:
Convert the Boolean expression ((A+B) C))D to NAND circuits and NOR circuits.
Step 1:
AND/OR logic diagram.

NAND Circuit:
Step 2:
Bubbles are added on the output of each AND gate and input side to all OR gates.

Step 4:
An inverter is added on each line that received a bubble in step 2. Double inversions are
eliminated.


21

Step 5:
Replace bubbled OR by NAND. Inverter is replaced by an equivalent NAND circuit.

NOR Circuit:
Step 3:
Bubbles are added on the output of each OR gate and input side to all AND gates.

Step 4:
An inverter is added on each line that received a bubble in step 3. Double inversions are
eliminated.

Step 5:
Replace bubbled AND by NOR. Inverter is replaced by an equivalent NOR circuit.


22

4.Convert (329.678)10 to an equivalent number in base 6 having a conversion error less than
0.001. (4)

(a) Integer Part:
6 329
6 54 5
6 9 0
(905)6
(b) Fractional Part:
0.678 x 6 4 0.068
0.068 x 6 0 0.408
0.408 x 6 2 0.448
0.448 x 6 2 0.688
(0.4022)6
= (905.4022)6

5. Use Quine McClusky method to obtain the minimal sum for the following function.
F(X1X2X3X4) = (0, 1, 3, 6, 7, 14, 15)

Step1: List all minterms in the binary form
Step2: Arrange the minterms according to the 1s.

Minterm Binary Representation Minterm Binary Representation
m0
m1
m3
m6
m7
m14
m15
0000
0001
0011
0110
0111
1110
1111
m0 0000
m1 0001
m3
m6
0011
0110
m7
m14
0111
1110
m15 1111

Step3: Compare each binary number with every term in the adjacent next higher
category and if they differ, only by one bit position, put s check mark and copy
the term in the next column with - in the position that they differed.

Step 4: Step 3 is repeated until a single pass through cycles yield no further
elimination of literals.

m0,m1 000- m0,m1
m1, m3
m3,m7
m6,m7,m14,m15
m6,m14,m7,m15

000-
00-1
0-11
-11-
-11-
m1, m3 00-1
m3,m7
m6,m7
m6,m14
0-11
011-
-110
m7,m15
m14,m15
-111
111-


23

Step5: List the prime implicants.

Step 6: Select the minimum number of prime implicants which must cover all the minterms.

Prime Implicants m0 m1 m3 m6 m7 m14 m15
m0,m1 * *
m1, m3 * *
m3,m7 * *
m6,m7,m14,m15 * * * *

The selection procedure is as follows,
(i) Search the single dot columns and select the prime implicants corresponding to that dot
by putting the check mark infront of it.
(ii) Search for multi dot column one by one. If the corresponding minterm is already
included in the final expression ignore the minterm and go to next multi-dot column;
otherwise include the corresponding prime implicant in the final expression.
The simplified expression is,
F (X1X2X3X4) = (000-) + (-11- ) + (00-1) =
4 2 1 3 2 3 2 1
x x x x x x x x + +

6. Simplify the function using Karnaugh map.
(i) F (ABCD) = (0, 1, 2, 4, 5, 7, 11, 15)
(ii) F (WXYZ) = (2, 3, 10, 11, 12, 13, 14, 15)

(i) F(A,B,C,D) = (0,1,2,4,5,7,11,15)

= ACD BCD C A D B A + + +

Prime Implicants Binary Representation
m0,m1 000-
m1, m3 00-1
m3,m7 0-11
m6,m7,m14,m15 -11-
1 1 1
1 1 1
1
1

24

(ii) F(W,X,Y,Z) = (2,3,10,11,12,13,14,15)

= wx y x +

7. (i) Find a minimal sum of products representation for
f(A,B,C,D,E) =m(1,4,6,10,20,22,24,26) + d(0,11,16,27) using karnaugh map method.
Draw the circuit of the minimal expression using only NAND gates.

= E C AB E C B D C B A D C B E D B + + + +

Logic Diagram:

1 1

1 1 1 1
1 1
x 1
1 1

x 1
x
1 1

1 x 1

25

ii. Prove that ) ( ) ( ) (
3 1 2 3 3 1 2 1
x x x x x x x x - + + - - + =
2 1
x x
L.H.S
= ) ( ) ( ) (
3 1 2 3 3 1 2 1
x x x x x x x x - + + - - +
= )) ( )( ( ) (
3 1 2 3 3 1 2 1
x x x x x x x x - + - - +
= )) ( )( ( ) (
3 1 2 3 3 1 2 1
x x x x x x x x + - + - - +
= ) ( ) ( ) (
3 2 1 2 3 3 1 2 1
x x x x x x x x x + - + - +
= ) ( ) ( ) (
3 2 1 2 3 1 2 1
x x x x x x x x + - + - + B A B A A + = +
= ) ( ) (
3 2 1 2 3 2 2 1 3 1
x x x x x x x x x x + - + +
= ) (
3 2 1 3 2 1 1 2
x x x x x x x x + +
= ) 1 ( (
3 3 1 2
x x x x + +
= ) (
1 2
x x (1 + x = x) This is R.H.S
= This is the proof.

8. (i) Explain how you will construct an (n+1) bit Grey code from an n bit Grey code.
(ii) Determine the MSP form of the switching function,
F = (0,1,4,5,6,11,14,15,16,17,2022,30,32,33,36,37,48,49,52,53,59,63).
Soln:
(a) Assume the generation of 4 bit grey code from a 3 bit gray code.
3-bit grey codes are,
0 0 0
0 0 1
0 1 1
0 1 0
1 1 0
1 1 1
1 0 1
1 0 0
(b) 4-bit gray codes are constructed from the 3 bit gray code by placing 0 before the
left of the 3(n) bit gray code and 1 before the newly generated gray code (mirror
image).
Taking mirror image we get
1 0 0
1 0 1
1 1 1
1 1 0
0 1 0
0 1 1
0 0 1
0 0 0

4(n+1) bit gray codes are
0 0 0 0
0 0 0 1
0 0 1 1

26

0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0

1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0

(ii) F = (0,1,4,5,6,11,14,15,16,17,20,21,22,30,32,33,36,37,48,49, 52, 53, 59, 63).

6 Variable Map:

Minterms are plotted in 6 variable map as,


27

OR
B A = 00 B A = 01

10 = B A 11 = AB

9. Simplify the Boolean function using K-map and tabular methods. Compare the methods.
F (A, B, C, D) =m(4,5,6,7,8) + d (A, B, C, D) = m(11,12,13,14,15).
Soln:

F (A, B, C, D) = D C A B +

1
1 1
1 1
1 1 1 1
1 1
1 1 1
1

1 1
1 1

1 1
1 1 1
1 1
1

1 1 1 1
x x x x
1 x

28

Tabulation method:

(i) Arranging the minterms according to the number of 1s

m4
m5
m6
m7
m8
0100
0101
0110
0111
1000
m4
m8
0100
1000
m5
m6
m12
0101
0110
1100
m11
m12
m13
m14
m15
1011
1100
1101
1110
1111
m7
m11
m13
m14
0111
1011
1101
1110
m15 1111

Elimination of literals:

Minterm
Binary
Representation
Minterm Binary
Representation
4,5
4,6
4,12
8,12
010-
01-0
-100
1-00
4,5,6,7
4,6,5,7
4,12,5,13
5,7,13,15
5,13,7,15
6,7,14,15
6,14,7,15
01--
01--
-10-
-1-1
-1-1
-11-
-11-
5,7
5,13
6,7
6,14
01-1
-101
011-
-110
7,15
11,15
13,15
14,15
-111
1-11
11-1
111-

Further elimination of literals:

Minterm Binary Representation
4,5,6,7*
5,7,13,15*
4,5,12,13,6,7,14,15*
8,12
11,15
01--
-1-1
-1--
1-00
1-11


29

Selecting the minimum number of prime implicants as

Prime Implicants m4 m5 m6 m7 m8 m11 m12 m13 m14 m15
4,5,6,7 * * * *
5,7,13,15 * * * *
4,5,12,13,6,7,14,15 * * * * * * * *
8,12 * *
11,15 * *

= D C A B +

10. State and prove demorgans theorem and expand the function F = ( ) ) ( ( D C C B A + +
Soln:
( ) ) ( ( D C C B A + + = D C C B A - + ) (
= ) ( ) ) ( ( D C C B A + - + +
= ) ( ) ) (( D C C B A + - + -
= ) )( ( D C C B C A + +
= D C B D C A C C B C C A + + +
= D C B D C A +

11. (i) Express the function f(x,y,z) = Z X XY + as a product of sum terms form.
(ii) Express the following function as the minimal sum of products, using a K-map.
F (a,b,c,d) =m(0,2,4,5,6,8,10,15) + (7,13,14) .
Soln:
(i) f(x,y,z) = Z X XY +
= ) ( Z Y X +
= ) )( ( Z Y X X Z Z Y Y X + + - - + - +
=
) (
) )( )( )( )( (
Z Y X
Z Y X Z Y X Z Y X Z Y X Z Y X
+ +
+ + + + + + + + + +

= ) )( )( )( )( ( Z Y X Z Y X Z Y X Z Y X Z Y X + + + + + + + + + +
= M0 M1 M2 M3 M5
= M (0,1,2,3,5)


30

(ii) F (a,b,c,d) =m(0,2,4,5,6,8,10,15) + (7,13,14)

= bcd b a d b + +

12. Perform the following arithmetic using 9s arithmetic. Compare them.
(I) 835 274
(II) 429 - 476 using BCD and excess 3 codes.

9s complement subtraction:
Steps:
(i) Add the minuend (M) to the (r-1)s complement of subtrahend N.
(ii) Check the result obtained in step 1.
(a) If an end carry occurs add 1 to the LSB (end around carry).
(b) If an end carry doesnt occur, take the (r-1)s complement of the number obtained
in step1 and place a negative sign in front of it.

(I) 835 274 (using 9s complement)
Step 1:
9s complement of 274 = r
n
-r
m
-N
= 10
3
-1-274
= 999 274
= 725

Step 2:
M + (r-1)s complement = 835 +
= 725
= 1 560
End carry occurs, therefore adding 1 we get
= 560
= 1
= 561
(II) 429 - 476 using BCD and excess 3 codes.
BCD addition procedure:
(i) Add two BCD numbers using ordinary binary addition.
(ii) If four-bit is equal to or less than 9, no correction is needed. The sum is in proper
BCD form.
(iii) If the four bit sum is greater than 9 or if a carry is generated from the four bit sum
1 1
1 1 x 1
x 1 x
1 1

31

the sum is invalid.
(iv) To correct the invalid sum, add 01102 to the four bit sum. If a carry results from
this addition, add it to the next higher order BCD digit.

(a) Using BCD subtraction:
Step 1: (9s complement):
9s complement of 476 = r
n
-r
m
-N
= 10
3
-10
0
- 476
= 999 476 = 523
Step 2:
M + (r-1)s complement = 0100 0010 1001
= 0101 0010 0011

= 1001 0100 1100
0110
= 1001 0101 0010
= 9 5 2
9s complement 952 = 10
3
-10
0
-952
= 999 952
= - 47

(b) Excess 3 code (9s complement).
To perform excess 3 subtraction we have to
Complement the subtrahend.
Add complemented subtrahend to minuend.
If carry =1 result is positive. Add 3 and end around carry.
If carry =0 result is negative. Subtract 3.
Excess 3 code for 476 = 0111 1010 1001
Step 1:
9s complement of 476 = 1000 0101 0110
Step2:
M + 9s complement of N = 0111 0101 1100
= 1000 0101 0110

= 1111 1011 0010
(-3)0011(-3) 0011 (+3) 0011
= 1100 1000 0101
No carry occurs therefore taking 9complement we get,
= - 0011 0111 1010
= - 3 7 A
(-37A) is the excess 3 code for (-047)


32

13. Implement the following with either NAND gate or NOR gate gates. Use only 4 gates. Only
the normal inputs are available.
(i) d = WYZ
(ii) F = Z Y WX X YZ W XZ W + + + (8) (April).
Soln:
Using NAND gate:
(i) d = WYZ
Step 1:
AND OR logic has been drawn.

Step 2:
Add bubbles at the output of each AND gate and to the input of each OR gate.

Step 3:
Add inverter that received a bubble in Step2 and then eliminate double inversions.

Step 4:
Replace bubbled OR by NAND and NOT by equivalent NAND.


33

(ii) F = Z Y WX X YZ W XZ W + + + (8) (April).
Step 1:

Step 2:

Step 3:

Step 4:


34

14. Show that if all the gates in a two level OR-AND gate network are replaced by NOR gates,
the output function doesnt change.
Soln:
Y = (A+B) (C+D)

Step 1:
OR-AND gate network has been drawn.

Step 2:
Add bubbles at the output of each OR gate and to the input of each AND gate.

Step 3:

Step 4:
Replace bubbled AND by NOR and NOT by equivalent NOR.

Thus if all the gates in a two level OR-AND gate network are replaced by NOR gates the
output doesnt change.


35

15. Design a logic circuit to simulate the function f(A,B,C) = A(B+C) by using only NAND
gates.
Soln:
f(A,B,C) = A(B+C) = AB +AC
Step 1:

Step 2:

Step 3:

Step 4:


36

16. Implement the switching function whose octal designation is 274 using NAND gates only
Soln:
The switching function with octal designation of 274 can be given as,
F = C B A ABC C B A + +

Step 1:

Step 2:

Step 3:

Step 4:


37

17. Implement the switching function whose octal designation is 274 using NOR gates.
Soln:
The switching function with octal designation of 274 can be given as,
F(A,B,C) = C B A ABC C B A + +
F(A,B,C) = ) , , ( C B A F = C B A ABC C B A + +
= C B A ABC C B A - -
= C B A C B A C B A + + - + + - + + ( ) ( ) (
= ) ( ) ( ) ( C B A C B A C B A + + - + + - + +
The equivalent NOR circuit has been drawn as,

18. What are codes? Explain the different types of codes with example?

The digital data is represented, stored and transmitted as groups of bits, known as binary code,
represent both numbers and letters of the alphabets as well as many special characters and control
functions.
The different binary codes can be classified as,
1. Weighted codes. 2. Non-weighted binary codes.
3. Error-detecting codes. 4. Error-correcting codes and
4. Alpha numeric codes.
Weighted binary codes:
Weighted binary codes obey their positional weighting principles. Each position of a
number represents a specific weight.
In a weighted binary code, the bits are multiplied by
the weights indicated; the sum of these weighted bits gives the equivalent decimal
digits. Eg: 8421, 2421, 5421,7536 and Biquinary (5043210) codes.


38

BCD (or) 8421 Code:
The Binary-coded-decimal (BCD) uses the binary number system to specify the
decimal numbers 0 to 9. It has four bits.
Reading from left to right the weights are 8-4-2-1
(2
3
-2
2
-2
1-
2
0
), and hence it is called 8421 code. Eg: Decimal number 12 is represented in
BCD as 0001 0010.
2421 Code:
This is weighted binary code; its weights are 2, 4, 2 and 1. A decimal number is
represented in 4-bit form and the total weight of the 4 bits =2+4+2+1 =9.Hence the 2421
code represents the decimal numbers from 0 to 9.
Upto 4, the 2421 code is same as that in BCD; however it varies for digits from 5 to 9. This
code is also a self complementing code i.e. the 9s complement of a number N is obtained
by complementing the 0s and 1s in the code word N.
For example, the 2421 code for 3 is 0011 and its natural complement 1100 gives 6 which
is the 9s complement of 3.

Reflective codes:
A code is said to be reflective when the code for 9 is the complement of the code for 0, 8
for 1, 7 for 2, 6 for 3, and 5 for 4. Eg: 2421, 5211, and Excess-3 code.
While finding the 9s complement, such as in 9s complement subtraction, reflectivity is
desirable in a code.
Sequential codes:
A code is said to be sequential when each succeeding code is one binary number greater
than its proceeding code. It helps mathematical manipulation of data. Eg: 8421 and
Excess-3 codes.
Non-Weighted codes:
Non-weighted codes are codes that are not positionally weighted. This mean that each
position within a binary is not assigned a fixed value. Eg: Excess-3 and Gray codes,
2- out-of -5 code.
Excess-3 code:
An excess-3 code is obtained by adding 3 to a decimal number. The decimal number 6
is encoded in excess-3 code as 9 and its binary equivalent is 1001.
Decimal
Digit
8421
code
2421
code
5421
code
7536
code
Biquinary code
5043210
0
1
2
3
4
5
6
7
8
9
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
0000
0001
0010
0011
0100
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
1000
1001
1010
1011
1100
0000
1001
0111
0010
1011
0100
1101
1000
0110
1111
0100001
0100010
0100100
0101000
0110000
1000001
1000010
1000100
1001000
1010000

39

It is a self complementing code and this helps in performing subtraction operation in
digital computers. It is also a reflective code.
Gray codes:
The gray code is a minimum-change code, in which only one bit in the code group
changes when moving from one step to the next.
Therefore, it is not suitable for arithmetic operations but finds applications in
input/output devices and in some types of analog to digital converters.
The gray code is a reflective code which has a special property of containing two adjacent
code numbers that differ by only one bit. Therefore it is called a unit-distance code.
It is often used when translating an analog such as a shaft position into digital form. In this
case a small change in the analog quantity will change only one bit in the code, which
gives more reliable operation than if two or more bits changed at a time.

2- out-of -5 code:
The 2-out-of-5 has the property that exactly 2 out of the 5 bits are 1 for every valid code
combination.
This code has useful error-checking properties since if any one of the bits in a code
combination is changed due to a malfunction of the logic circuitry, the number of no 1s no
longer exactly two.
Error Detection and Correction:
During the process of binary data transmission errors may occur. In order to detect and
correct such errors 2 types of codes namely (i) error detecting codes and (ii) error
correcting codes may be used.
The most simple and commonly used error detecting methods is the parity check, in
which an extra parity is included with the binary message to make the total no. of ones
either odd or even resulting in 2 methods. (i) Even parity method, (ii) Odd parity method.
In the even parity method the total no. of ones in the code group (including the parity bit)
must be an even number. In the odd parity method the total no. ones (including the parity
bit) must be an odd number.
A parity bit can be placed at either end of the code word such that the receiver able to
understand the parity bit and actual data. The parity code is meant for single error
detection, it detect any odd no. of errors. If an even no. of errors occur, then the parity
check is satisfied giving an erroneous result.

Decimal
Digits
Excess-3
code
2-out-of-5
code
Gray
Code
0 0011 00011 0000
1 0100 00101 0001
2 0101 00110 0011
3 0110 01001 0010
4 0111 01010 0110
5 1000 01100 1110
6 1001 10001 1010
7 1010 10010 1011
8 1011 10100 1001
9 1100 11000 1000

40

Check Sums:-
The Check sum method is used to detect double errors and pin point erroneous bits.
Initially word A 10110111 is transmitted; next the word B 00100010 is transmitted.
The binary digits in the words are added and the sum obtained is retained in the
transmitter. Then, a word C is transmitted and added to the previous sum and the new
sum is retained. In the same manner, each word is added to the previous sum; after
transmission of all the words, the final sum called the check sum is also transmitted.
The same operation is done at the receiving end and the final sum obtained here is
checked against the transmitted check sum. If the two sums are equal, then there is no
error.
Hamming code:
R.W.Hamming developed a system to detect and correct errors. In the Hamming code, k
parity bits are added to an n-bit data word, forming a new word of n+k bits.
The bit positions are numbered in the sequence from 1 to n+k. Those positions numbered
as a power of 2 (i.e. 2
0
, 2
1
, 2
2
, 2
3
.. = 1(P1),2(P2),4(P4),8(P8).) are reserved for the parity
bits. The remaining bits are data bits. Each parity bit is calculated as
P1 = XOR of bits (3, 5, 7, 9, 11)
P2 = XOR of bits (3, 6, 7, 10, 11)
P4 = XOR of bits (5, 6, 7, 12)
P8 = XOR of bits (9, 10, 11, 12)

An error-correcting code generates parity check bits. Each check bit is parity over a group
of bits in the data word. When the word is read from memory, they are checked again for
possible errors.
The parity is checked over the same combination of bits including the parity bit. They are
evaluated as,
C1 = XOR of bits (1, 3, 5, 7, 9, 11)
C2 = XOR of bits (2, 3, 6, 7, 10, 11)
C4 = XOR of bits (4, 5, 6, 7, 12)
C8 = XOR of bits (8, 9, 10, 11, 12)
If the check bits are correct i.e C = C1.C2.C4.C8.= 0, it signifies no error has occurred. If
C = 0, it generate a unique pattern, called a syndrome, that can be used to identify the bit
in error.
Single error correction, double error detection:
The Hamming can detect and correct only a single error. By adding another parity bit to
the coded word, the hamming code can be used to correct a single error and detect
double errors.
This parity bit is evaluated from the Ex-OR of the other 12 bits. If P=0, the parity is correct,
but if P=1, then the parity over the 13 bits is incorrect. The following four cases occur:
(i) If C = 0 and P = 0, no error occurred.
(ii) If C= 0 and P = 1, a single error occurred that can be corrected
(iii) If C= 0 and P = 0, a double error occurred that is detected but that can not be
corrected.
(iv) If C = 0 and P = 1 An error occurred in the parity bit.
Alphanumeric codes:
The codes that represent numbers numbers, alphabetic letters and special symbols called
alphanumeric codes. Eg: ASCII code, EBCDIC code and Hollerith code.
The standard code for alphanumeric character is ASCII (American standard Code for
Information Interchange).

41

It uses seven bits to code 128 characters. It is designated by b1 through b7 (M.S.B).
ASCII contains 94 graphic characters (26 uppercase letters, 26 lower case letters, 10
numeral and 32 printable characters) and 34 control characters.
There are three types of control characters:
(i) Format effectors control the layout of printing.
(ii) Information separators separate the data into divisions such as paragraphs
and pages.
(iii) Communication control characters useful during the transmission of text
between remote terminals. Table: Refer Text book.

IMPORTANT QUESTIONS

1.State De Morgans theorem.
De Morgan suggested two theorems that form important part of Boolean algebra.
They are, 1) The complement of a product is equal to the sum of the complements.(AB) = A + B
2) The complement of a sum term is equal to the product of the complements. (A + B) = AB
2). Define binary logic?
Binary logic consists of binary variables and logical operations. The variables are designated by the
alphabets such as A, B, C, x, y, z, etc., with each variable having only two distinct values: 1 and 0.
There are three basic logic operations: AND, OR, and NOT.
3). Define logic gates?
Logic gates are electronic circuits that operate on one or more input signals to produce an output
signal. Electrical signals such as voltages or currents exist throughout a digital system in either of
two recognizable values. Voltage- operated circuits respond to two separate voltage levels that
represent a binary variable equal to logic 1 or logic 0.
4).Define duality property.
Duality property states that every algebraic expression deducible from the postulates of Boolean
algebra remains valid if the operators and identity elements are interchanged. If the dual of an
algebraic expression is desired, we simply interchange OR and AND operators and replace 1s by 0s
and 0s by 1s.
5).Find the complements of the functions F1 = xyz + xyz and F2 = x(yz+ yz) by taking their
duals and complementing each literal.
F1 = xyz + xyz
The dual of F1 is (x + y + z)(x + y + z)
Complementing each literal: (x + y + z)(x + y + z)
F2 = x(yz + yz).
The dual of F2 is x + (y + z)(y + z).
Complement of each literal: x + (y + z)(y + z)

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6) What are called dont care conditions?
In some logic circuits certain input conditions never occur, therefore the corresponding output
never appears. In such cases the output level is not defined, it can be either high or low. These
output levels are indicated by X ord in the truth tables and are called dont care conditions or
incompletely specified functions.
7.Why are NAND and NOR gates known as universal gates?
The NAND and NOR gates are known as universal gates, since any logic function can be
implemented using NAND or NOR gates.
8). Reduce A(A + B)
A(A + B) = AA + AB
= A(1 + B) [1 + B = 1]
= A.
9. Reduce ABC + ABC + ABC
ABC + ABC + ABC = AC(B + B) + ABC
= AC + ABC [A + A = 1]
= A(C + BC) = A(C + B) [A + AB = A + B]
10. Simplify the following expression Y = (A + B)(A + C )(B + C )
Y = (A + B)(A + C )(B + C )
= (AA + AC +AB +BC )(B + C) [A.A = 0]
= (AC + AB + BC)(B + C )
= ABC + ACC + ABB + ABC + BBC + BCC
= ABC + ABC
11. Simplify the following using De Morgans theorem [((AB)C) D]
[((AB)C) D] = ((AB)C) + D [(AB) = A + B]
= (AB) C + D
= (A + B )C + D
12. Show that (X + Y + XY)( X + Y)(XY) = 0
(X + Y + XY)( X + Y)(XY) = (X + Y + X)(X + Y )(X + Y) [A + AB = A + B]
= (X + Y )(X + Y )(XY) [A + A = 1]
= (X + Y )(XY) [A.A = 1]
= X.X + Y.X.Y
= 0 [A.A = 0]


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13).Prove that ABC + ABC + ABC + ABC = AB + AC + BC
ABC + ABC + ABC + ABC =AB(C + C) + ABC + ABC
=AB + ABC + ABC
=A(B + BC) + ABC
=A(B + C) + ABC
=AB + AC + ABC
=B(A + C) + AC
=AB + BC + AC
=AB + AC +BC ...Proved
14).Convert the given expression in canonical SOP form Y = AC + AB + BC
Y = AC + AB + BC
=AC(B + B ) + AB(C + C ) + (A + A)BC
=ABC + ABC + ABC + ABC + ABC + ABC + ABC
=ABC + ABC +ABC + ABC [A + A =1]
15).Convert the given expression in canonical POS form Y = ( A + B)(B +C)(A + C)
Y = ( A + B)(B + C)(A + C)
= (A + B + C.C )(B + C + A.A )(A + B.B + C)
= (A + B + C)(A + B + C )(A + B +C)(A + B +C)(A + B + C)(A + B + C) [A + BC
= (A + B)(A + C)
Distributive law]
= (A + B + C)(A + B + C)(A + B + C)(A + B + C)(A + B + C)
16). Find the minterms of the logical expression Y = ABC + ABC + ABC + ABC
Y = ABC + ABC + ABC + ABC
=m0 + m1 +m3 +m6
17).Write the maxterms corresponding to the logical expression
Y = (A + B + C )(A + B +C)(A + B + C)
Y = (A + B + C )(A + B + C)(A + B + C)
=M1.M3.M6
18.Mention the important characteristics of digital ICs?
Fan out
Power dissipation
Propagation Delay
Noise Margin
Fan In

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Operating temperature
Power supply requirements
19. Define Fan-out?
Fan out specifies the number of standard loads that the output of the gate can drive
with out impairment of its normal operation.
20. Define power dissipation?
Power dissipation is measure of power consumed by the gate when fully driven by all
its inputs.
21. What is propagation delay?
Propagation delay is the average transition delay time for the signal to propagate from
input to output when the signals change in value. It is expressed in ns.
22. Define noise margin?
It is the maximum noise voltage added to an input signal of a digital circuit that does
not cause an undesirable change in the circuit output. It is expressed in volts.
23. Define fan in?
Fan in is the number of inputs connected to the gate without any degradation in the
voltage level.
24. What is Operating temperature?
All the gates or semiconductor devices are temperature sensitive in nature. The
temperature in which the performance of the IC is effective is called as operating
temperature. Operating temperature of the IC vary from 00 C to 700 c.
25.What are the types of TTL logic?
1. Open collector output
2. Totem-Pole Output
3. Tri-state output.
26. Why totem pole outputs cannot be connected together.
Totem pole outputs cannot be connected together because such a connection might produce
excessive current and may result in damage to the devices.
27. State advantages and disadvantages of TTL
Adv:
Easily compatible with other ICs
Low output impedance
Disadv:
Wired output capability is possible only with tristate and open collector types.

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Special circuits in Circuit layout and system design are required.
28. Give the classification of logic families.

29.Find the complement of the functions F1 = xyz + xyz and F2 = x(yz +yz). By applying De
Morgans theorem as many times as necessary.
F1 = (xyz + xyz) = (xyz)(xyz) = (x + y + z)(x + y +z)
F2 = [x(yz + yz)] = x + (yz + yz)
= x + (yz)(yz)
= x + (y + z)(y + z)
30. Reduce AB + (AC) + ABC(AB + C)
AB + (AC) + ABC(AB + C) = AB + (AC) + AABBC + ABCC
= AB + (AC) + ABCC [A.A = 0]
= AB + (AC) + ABC [A.A = 1]
= AB + A + C =ABC [(AB) = A + B]
= A + B + C + ABC [A + AB = A + B]
= A + BC + B + C [A + AB = A + B]
= A + B + C + BC
=A + B + C + B
=A + C + 1
= 1 [A + 1 =1]
31. Simplify the Boolean function F=AB+ BC + BC.
Solution. F = AB + BC + BC
= AB + C(B + B)
= AB + C
32. Simplify the Boolean function F= A + AB.
Solution. F = A+ AB
= (A + A) (A + B)
= A + B

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33. Simplify the Boolean function F= ABC + ABC + AB.
Solution. F = ABC + ABC + AB
= AC (B+B) + AB
= AC + AB
34. Simplify the Boolean function F = AB + (AC) + ABC(AB + C).
Solution. F = AB + (AC) + ABC(AB + C)
= AB + A + C+ ABC.AB + ABC.C
= AB + A + C + 0 + ABC (B.B = 0 and C.C = C)
= ABC + ABC + A + C + ABC (AB = AB(C + C) = ABC + ABC)
= AC(B + B) + C(AB + 1) + A
= AC + C+A (B + B = 1 and AB + 1 = 1)
= AC + (AC)
= 1
Example 4.16. Obtain the minimal sum of the products for the function F (A, B, C, D) = E (1, 4, 6, 7, 8, 9, 10, 11, 15).


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F = AB + BCD + ABD + BCD.

Obtain the minimal sum of the products for the function F (A,B,C,D) = E (1, 2, 3, 7, 8, 9, 10, 11, 14, 15) by the Quine-
McClusky method.


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F = BD + BC + AB+ CD + AC.

Using the Quine-McClusky method, obtain the minimal sum of the products expression for
the function F(A, B, C, D) = (1, 3, 4, 5, 9, 10, 11) + (6, 8).


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F = ABC + BD + AB.

Using the Quine-McClusky method obtain the minimal sum of the products expression for
the function F(A,B,C,D,E) = E (0, 2, 3, 5, 7, 9, 11, 13, 14, 16, 18, 24, 26, 28, 30).


50

F = BCE + ABE + ACDE + ABCE + ABDE + BCDE.

Boolean Algebra and Logic Gates.

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Boolean Algebra and Logic Gates.

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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EDAPALAYAM, REDHILLS, CHENNAI-52.

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