Digital

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY
EDAPALAYAM, REDHILLS, CHENNAI-52.
EC2302-DIGITAL ELECTRONICS 1. Explain T-flip-flop with suitable internal structure. Ans. The functional block diagram of T flip-flop is as shown in fig.
T flip-flop is known as Toggle flip-flop
When, T = 1 both NAND Gates 1 and 2 gets high A T flip-flop is designed by combining both the inputs of Gate 1 and 2 together. Thus, when J = K = 0, Q have same previous state i.e. hold state or no change state. When J = K = l, Q have toggle state i.e. invert the previous state. 2. Convert SR flip-flop to T flip-flop. Ans. Firstly write the truth table for SR to T flip-flop as shown:
R.RAMADHURAI B.E.,M.TECH AP/ECE

EC2302-DIGITAL ELECTRONICS K maps for S & R are: For S: For R:
Implementation:
3. Give applications of J-K flip-flops. 1. J-K flip-flops are used in shift registers. 2. J-K flip-flops are used in counters. 4. Give difference between latch and flip-flop.
Q 5. How race around condition can be eliminated? Race around condition can be eliminated in JK latch by two ways 1. Using the edge triggered J-K flip-flop. 2. Using the master slave J-K flip-flop.

EC2302-DIGITAL ELECTRONICS 6. What is a Glitch? Glitch is a short duration pulse or spike that appears in the outputs of a counter with MOD number 7. How many flip-flops are required to count 16 clock pulses? Why? To count n clock pulses m flip-flops are required, where,
Thus, for 16 clock pulses to count, 4 flip-flops are required as 2 = 16. 8. Give application of D and T flip-flops. D flip-flops are delay flip flops and are extensively used for temporary storage of data in registers. Hence, registers make use of D flip-flops. T flip-flops are toggle flip-flops and are used in counters. Hence, counter designing make use of T flip-flops. 9. For the given state diagram, draw the state reduction diagram. Stats Diagram:
Ans. State table is as shown:

EC2302-DIGITAL ELECTRONICS For modified reduced state diagram:
10. What do you mean by self starting type counter? Whenever there is no problem of lock out then the counter is self-starting type. So, if any time the counter goes into an invalid state, it comes out and goes into a valid state after application of one clock pulse. 11. Why is gated D latch called transparent latch? The edge triggered D flip-flop uses an edge-detector circuits so that the output will respond to D input only when the active transition of clock takes place. It is as shown in fig.
From fig. when enable is 1, the D input will given a 0 at either the or inputs of NAND latch. Thus, 0 becomes same as D. Thus, when enable is 1 the output Q will look exactly like D. Hence, the D latch is said to be transparent latch.

EC2302-DIGITAL ELECTRONICS 12. A presettable counter has eight flip-flops. If the preset number is 125, what is the modulus? 256 125 = 131 Thus, MOD 131. 14. Differentiate between sequential and combination circuits.
13. The clock frequency is 2MHz. How long will it take to serial load the eight shift register? n=8 Time taken to load serially the eight bit will be given by
14. What is flip-flop? Flip-flop : Flip-flop is a sequential circuit which is used to store single bit of information at a time i.e. either 1 or 0 at a time. It has two stable output states. It can stay in one of the two stable states unless state is changed by applying external inputs. Thus, it as a basic memory element for storage of data in binary form. There are various types of flip-flops 1. S-R flip flop 2. J-K flip-flop 3. D-type flip flop 4. T-type flip-flop

EC2302-DIGITAL ELECTRONICS 15. What is shift register? Shift register : A register capable of shifting its binary information either from right to left or left to right is known as shift register. It consists of flip-flops connected is cascade. All flipflops receive a common clock pulse which causes the shift from one stage to the next stage. It is of four basis types: 1. Serial in serial out register 2. Serial in parallel out register 3. Parallel in serial out register 4. Parallel in parallel out register. Bi-directional shift register and Universal shift registers are also used for different applications. 16. What is universal shift register? Universal shift register performs similar operation and function as that of bidirectional shift register i.e. it can shift data from left to right or right to left, in addition to it data can be shifted in and out and in serial as well as in parallel form. 17. Draw a logic symbol for a D-flip-flop and compare with RS flip-flop.
In case of RS two inputs are there hence four possible combined are used. But in case of D flip-flop it has only one input so and two combination are used. Also, in D flip-flop what ever we want to store will be put as input. If we want to store 1. 1 is the input and if 0 is input, 0 will be stored in D flip-flop.

EC2302-DIGITAL ELECTRONICS 18. Differentiate between synchronous and asynchronous counters.
19. What is buffer register? Buffer registers are also called as storage registers. They are primarily used for temporary storage, of binary information or data. They provide place to hold data until it is processed. That is why they are known as buffer registers. 20. Suggest four applications of shift registers. Applications of shift registers 1. It is used in ring counters. 2. It is used in sequence generators. 3. It is used for data conversion in computers i.e. serial to parallel, parallel to serial etc. 4. It is used for time delays i.e. serial in serial out shift register are used for this purpose. 5. It is used in Johnson counter / twisted ring counter.

EC2302-DIGITAL ELECTRONICS 21. Give the truth-table for each flip-flop type: (a) J-K ; (b) D ; and (c) T Truth table of J-K Flip-flop:
2. D Flip-flop:
Q output follows D input with each other. 3. T Flip-flop:
Toggle means 0 changes to 1 and 1 changes to 0 with the passage of each clock 22. Explain why there may be a race condition in a shift register. There is no race condition in Shift register as it make use of D flip flop, R S flip flop as D and J K flip flop So the condition of J = K = 1 never comes. 23. What is a ripple counter? Ripple Counter- Ripple counters are also known as asynchronous counters. It is as shown in fig for two bits

EC2302-DIGITAL ELECTRONICS
For ripple counter input clock is given to first flip-flop and the output of first flip-flop acts as a clock to next flip-flop and so on 24. Differentiate between static and dynamic shift registers.
25. What is the Mod of 6 bit Ring Counter ? The mod of 6 bit ring counter is given by 2 where n = number of bits. 2 = 64. and synchronous counters. Thus MOD-64. 26. Give expression for maximum frequency of operation of n-bit Asynchronous
Max. frequency of operation for asynchorous counter
It is same for synchronous counter unless no. of flip-flop, where the maximum frequency of synchronous counter is

EC2302-DIGITAL ELECTRONICS 27. Compare binary counters with non-binary counters.
28. Draw logic circuit diagram for 3-bit synchronous up-down counter with clear input, start input and done output. The counter should produce done output after completion of counter in either direction. 3-bit synchronous up-down counter:
29. Specially where Master-slave J-K flip flop is preferred for use. Master slave J-K flip-flop is preferred where we want to avoid multiple toggling and race around conduction. In this flip-flop, master F/F is positive edge triggered and slave flip-flop is negative edge triggered. The slave ftp-flop followed the master flip-flop. 30. Applications of D Flip Flop. 1. D Flip-flop can be used as a delay element 2. As a memory element. 3. In counters! timers. 4. in various types of registers, like in SIPO, SIPO etc.
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EC2302-DIGITAL ELECTRONICS 31. Draw the logic circuits and the excitation tables for the T, JK flip-flops.
32. Classify the sequential circuits.
33. Describe the difference between a gated S-R latch and an edge-triggered S-R flip flop. Gated S-R Flip-Flop : A gate S-A Flop/flop requires an enable (E) input. When enable is high, the output changes according to the inputs S and R. However when enable is ineffective, no change of state take place. Clock signal may also act as a enable.
Edge Triggered S-R Flip-flop: In edge-triggered S-R flip-flop, the change of state in flip-flop takes place only when edge (either +ve or -ve) of clock pulse takes place.
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EC2302-DIGITAL ELECTRONICS 34. What is the difference between level and edge triggering? Explain the working of master slave J-K flip flop.
Master slave JK flip-flop : The master slave flip-flop may be designed using R-S, D and JK flip-flops. Following figure shows the functional block diagram of master slave JK flip- flop: In figure m is used for Master and S is used for Slave
Working: Case 1: When positive clock pulse goes on leading edge is applied, the CLKm is 1 and CLKs is 0, then data transferred to Qm is held upto CLK = 1
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EC2302-DIGITAL ELECTRONICS Case 2: When the clock pulse goes negative, trailing edge is applied, the CLKm = 0 and CLKs = 1, then Qm and Qm will be transferred to Q = Q and at that duration the inputs at J and K should not change This is overcome by the use of data lockout. Internal structures of master slave J-K flip-flop, Truth table is as shown in fig
35. Draw a master-slave J-K flip-flop system. Explain its operation and show that the race-around condition is eliminated.
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EC2302-DIGITAL ELECTRONICS A master-slave J-K flip-flop is constructed from two flip-flops. One flip-flop acts as a master and the other as a slave and the overall circuit is thus, called as master-slave flip-flop. It make use of J-K master flip-flop and S-A slave flip-flop. The master is positive edge triggered and slave is negative edge triggered. Therefore, master responds to J-K inputs before the slave. If J = 1 and K = 0, the master sets on the positive clock edge. The high output of the master drives the J input of the slave, so when the negative clock edge arrives, the slave sets, copying the action of the master. If J = 0 and K = 1, the master resets on the positive clock edge. The high output of master i.e. goes to R input of the slave. Therefore, slave resets on arrival of negative clock edge.
If J = K = 1 for master, it toggles on positive clock edge and the slave them toggles on the negative clock edge. When J = K = 1 Let clock = 1 then master is active and slave is in active Therefore, output of master toggle. So S and R also will be inverted When clock 0 Master becomes in active and slave is active Therefore, output of the slave will toggle These changed outputs are again returned back to the master inputs as feedback is connected in fig But here clock is 0, the master is still in active So it does not respond to these changed outputs This avoids multiple toggling which is responsible for Race Around Condition Hence by using Master-Slave J K Flip-flop RACE AROUND CONDITION will be avoided or eliminated. 36. Explain what is universal shift register? Explain its working. A universal shift register is one which can function in any of the SISO SIPO PISO or PIPO modes of operation To operate the register universally it contains serial input serial output, parallel inputs, parallel outputs and must be able to serially shift data to the right or to the left, hold the data or to reset Thus, it has bidirectional property also It is a 74194 IC Its internal structure is as shown in figure.
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EC2302-DIGITAL ELECTRONICS 37. Draw the logic symbols for T and RS flip-flops. Explain the function of each type of flip-flop. RS Flip-flop: Its logic symbol is as shown in fig. Its internal structure is as shown:
Its functioning can be explained with the help of truth table as shown: Case I. When both the inputs i.e. S = R = 0 The data inside the flip-flop do not change i.e. if 0 was the previous data we get 0 as output data and if 1 was previously stored in flip-flop we get 1 as output data. Hence, no change state.
Case II. When the inputs are : S = 0 and R = 1. The flip-flop output is always 0 i.e. if the previously stored data was 0 or 1 we always get 0 output. Hence, Reset condition or state.
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EC2302-DIGITAL ELECTRONICS Case III When the inputs are S = 1 and R = 0 The flip flop output is always 1 i e if the previously stored data was 0 to 1 we always get 1 output Hence set state Case IV When the inputs are S = 1 and R = 1 The flip-flop outputs Q and intermediate state. T-flip-flop: comes same which is not possible i e Q = . Hence
T flip-flop is also known as Toggle flip-flop It is a modification of the JK flip-flop The T flip flop is obtained from a JK flip flop by connecting both inputs, J and K together When T = 0, both AND gates are disabled and hence these is no change in the output When T = 1 (i.e. J = 1 and K = 1) output toggles i.e. with the passage of each clock the output changes from 0 to 1 and 1 to 0 i.e. it toggles Its truth table is as shown in fig
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EC2302-DIGITAL ELECTRONICS 38. Draw the circuit of an S-R flip-flop using NAND gates. Modify it to include clock Derive J-K circuit from S-R flip-flop circuit and explain its truth table S-R Flip-flop using NAND gates:
Case l :When S = 0,R = 0 When any one input of NAND gate is zero, its output is forced to be 1. Now path Q and Q will be forced to become 1, which is not possible. Hence, Race condition or invalid state. Case2: When S = 0,R = 1 When S = 0, it will force Q to be 1 and hence both inputs R and Q become 1 and cause Q to be 0. It is called Reset condition. V Case3: When S = 1, R = 0 When R = 0, it will force Q to be 1. Hence both inputs S and Q will be 1 and cause Q to be 0. It is called set condition. V Case4: When S = 1, R =1 In this case, there will be no change in outputs. S-R Flip-flop including clock:
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EC2302-DIGITAL ELECTRONICS Derive J-K flip-flop from S-R flip-flop The truth table for S-R to J-K conversion is as shown:
K-maps
Logic diagram:
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EC2302-DIGITAL ELECTRONICS 39. Design a J-K counter that goes through states 2, 4, 5, 7, 2, 4 is the counter-self starting.
K-maps
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EC2302-DIGITAL ELECTRONICS Circuit
40. Perform the following conversions T flip-flop to D flip-flop. T flip-flop to D flip-flop: Truth table for conversion:
K-map for T:
Implementation of circuit diagram:
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EC2302-DIGITAL ELECTRONICS 41. Twisted ring counter is also known as Johnson counter. It is an application of shift register. Following figure shows the circuit diagram for its operation.
Operation : Initially a short negative pulse is provided to clear all the which resets the data to 000
42. Design a synchronous decade counter to count in the following sequence 1, 0, 2, 3, 4, 8, 7, 6, 5 The excitation truth table for synchronous decade counter to count the sequence 1, 0, 2, 3, 4, 8, 7, 6, 5 is as shown:
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Put all others as dont care conditions i.e. 10, 11, 12, 13, 14 and 15 to be dont care. K-map for TA:
K-map for TB:
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EC2302-DIGITAL ELECTRONICS K-map for TC:
K-map for TD:
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EC2302-DIGITAL ELECTRONICS 43. Write short note on the following: Counter design with state equation and state diagrams. Counter designing make use of static diagrams and state equations. State Diagram : The graphical representation of different states of a counter is known as state diagram. Let us consider an example of 3 bit Ripple counter (up and down)
The numbers written inside the circles are the state numbers and the arrows shows the direction of counter. In fig. (a) 0 is the initial state i.e. counter starts from 0 and count upto 7 then again 0 and so on. So it is up counter. Similarly, in fig. (b) initial state is 7so it starts from 7 and goes .to 0 then again 7and so on. So it is a down counter. State equation : A state equation is also known as application equation. It is an algebric expression that specifies the conditions for a flip-flop state transition. The left side of the equation represents the next state of the flip-flop and the right side gives a boolean function that specifies the present state conditions that make the next state equal to 1. The state equation can be derived from the state table or logic diagram. 44. What is race around condition in J-K flip flop? How it is eliminated? Race-Around Condition : When J and K both inputs are high i.e. J = K = I, the output will keep toggling indefinitely. This multiple toggling in J-K F/F is called Race-Around Condition. It can be eliminated by using master slave J-K flip-flop. 1. Master slave J-K Flip-flop
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EC2302-DIGITAL ELECTRONICS 2. By using RC triggering circuit:
45. Write note on 4 bit binary shift register. 4 bit binary shift Register: This type of Shift Register allows shifting either to left or right side.
Working Fig shows the bidirectional shift register When
signal IS High AND gates 1
3, 5, 7 are enabled and it enables the data shifting towards right Whereas when signal is Low AND gates 2, 4 6, 8 are enabled the data shifting is towards left Then the Q states of each flip-flop passes through the A and KA input of each proceeding flip flop When clock pulse arrives the data shift one place to right or left depending on 46. Design a BCD counter using JK flip-flops. The BCD decade counter counts from 0000 to 1001 as shown in diagram. The invalid states 1010 to 1111 should given next states as 0000 which is done by reset logic connected to clear input of all the flip-flops. .
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Truth table of BCD counter: Reset logic output for clear.
K-map:
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47. Design an up-down counter using JK Flip-flop to count 0, 2, 3, 6, 4, 0. Up-down counter counts (0, 2, 3, 6, 4, 0,......).
K-maps
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Circuit diagram
48. Design an up-down counter using D-flip-flops to count 0, 3, 2, 6, 4, 0,........
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EC2302-DIGITAL ELECTRONICS K-maps
Implementation of circuit:
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EC2302-DIGITAL ELECTRONICS 1. Explain the Bipolar RAM Cell. Bipolar transistor is used in bipolar ROM cell. It is as shown in figure.
When base of transistor is not connected with a row no current flows to the base and it represents a storage of logic 0. On the other hand, when base is connected the flowing to the base of transistor and it represents a storage of logic 1. 2. Design the OR Matrix or OR array. These gives the logical sum terms of output from AND arrays as shown in fig.
OR arrays gives sum terms in the logical form. Such as:
Here X are the fuse links used in diagrams. The interconnections without X are unplugged fuses or blown off fuse links.
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EC2302-DIGITAL ELECTRONICS 3. Draw the block diagram of PLA logic device. Ans.
4. Implement the boolean function using PAL.
Let the input variables are A, B and C. The K-map minimization is as shown:
Implementation using PAL:
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EC2302-DIGITAL ELECTRONICS 5. Design half adder circuit using PLA. Truth table of Half Adder circuit is:
Carry = C = AB.
6. What is a non-volatile memory? Non-volatile memory: The memory in which the data stored or information present once does not change even after the power is switched off is called as non-volatile memory. ROM i.e. Read only memory is the example of non-volatile memory. Because such memories hold the data or information even if power is switched off. 7. What are the advantages of static RAM over Dynamic RAM? . Advantages of static RAM over Dynamic RAM: 1. Access time of SRAM is less and thus these memories are faster memories. 2. As SRAM is consists of flip-flops thus, refreshing is not required. 3. Less number of memory cells are required in SRAM for unit area.
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EC2302-DIGITAL ELECTRONICS 8. What is EEPROM? EEPROM : Electrically Erasable PROM or Electrically Erasable Programmable Read Only Memory. This memory stores a bit by charging the floating gate of an FET. Thus, the memory is similar to EPROM except that the information can be altered by using electrical signals at the register level .rather than erasing all the information i.e. It can be erased information byte to byte. 9. What is PAL? PAL: PAL is known as programmable array logic. It is a programmed logic device with OR arrays fixed and AND arrays programmable. Because only AND gates are programmable, the PAL is easier to program, but it is not as flexible as the PLA (programmable logic array). For example : We have a boolean function given by Y (A, B, C,) = to implement it by using PAL. It is as shown: (1, 3, 4, 6) and we have
10. What is cache memory? Cache memory is a type of semiconductor memory. It forced its entry as fast memory device. It works as an interface between the CPU and the primary memory. Following block diagram shows the position of cache memory:
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EC2302-DIGITAL ELECTRONICS 11. Explain the role of PAL and PLA in digital design. Ans. PAL: It is called programmable array logic. It make use of AND array only as a programmable but OR array is fixed. PLA: It is called programmable logic array. Its AND or OR array both are programmable. Both PAL and PLA are used for memory purposes. 12. What is the difference between PAL and PLA?
13. What do you mean by PLDs? PLDs: Programmable logic devices are the special type of ICs used by the USE and are programmed before use Different type of logic functions can be implemented using a single programmed IC chip of PLDs. PLD s can be reprogrammed because these are based on re .writable memory technologies Fuse links are used to programmed the PLD b the user according to the type of PLD to be manufactured 14. Describe with diagram internal architecture of PLA Ans PLA is Programmable Logic Array It is used where the number of dont care conditions are excessive In PLAs both AND and OR arrays are programmable The ANI and OR gates are fixed for any PLA chip It depends on the number of inputs and outputs of PLA Let us take an example of Half Adder to illustrate the diagram internal architecture of PLA: Truth Table of Half Adder:
Thus, carry = A B and sum =
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EC2302-DIGITAL ELECTRONICS Implementation of Half Adder using PLA is as shown:
15. What is programmable logic array? How it differs from ROM? Programmable logic array are those in which AND and OR arrays are programmable. The AND and OR gates are fixed by any PLA chip. It depends on the number of inputs and outputs of PLA. Difference between PLA and ROM is as shown in table:
16. What is the difference between static and dynamic RAM?
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EC2302-DIGITAL ELECTRONICS 17. Where do we use PLAs? 1. Combinational circuits can be implemented using PLAs 2. Sequential circuits can be implemented using PLAs. 3. In sequential circuits implementation flip-flops and buffers are used at output stage with PLA devices while in combinational circuits only buffers are used. 4. Compact circuits can be built using PLAs, which covers less space. 18. On what basis do we characterize various type of memories. Memories can be characterize on various parameters. 1. Characterize based on Principal of operation. 2. Characterize based on Physical characteristics. 3. Characterize based on Mode of Access. 4. Characterize based on Fabrication Technology. 20. The difference between static and dynamic memories.
21. Give the classification of memories.
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EC2302-DIGITAL ELECTRONICS 22. What are the characteristics of memories? Characteristics of memory: 1. Memory organization and capacity 2. Physical dimensions 3. Packing of memory 4. Power consumption 5. Cost etc. 23. A certain memory stores 8 k x 16 bit words. How many data input lines, data output lines and address lines does it have ? What is its capacity in bytes? Ans. Memory is M x N form where M are memory locations and N are data input lines. Here M = 8K N = 16
24. What are the various types of ROMs? Discuss their relative advantages and disadvantages. ROM : In ROM, read and write operation cannot be periormed with equal ease always read operation is easier than write operation. It is used to store information which is (I) Permanent group includes ; masked ROM and PROM (ii) Semi permanent group include; EPROM and EE-PROM. Five types of ROM-masked ROM, PROM, EPROM, EE-PROM and flash memory are described in the following paragraphs. Masked ROM : Programming is done through masking and metallization. process. Manufactures provides programmed ROM, user cannot write into this memory. PROM : Programmable Read Only Memory user can program (write) the PROM through special PROM programmer. It can be written (programmed) once only, user cannot rewrite this memory.
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EC2302-DIGITAL ELECTRONICS EPROM : Erasable Programmable ROM. This memory stores a bit by charging the floating gate of an FET. The chip can be reused may times i.e., user can write this memory many time. Erasing is done using UV light through a window over the memory chip called quartz window. Erasing process cannot be done byte by byte or block by block, entire information will be erased at once,- after exposing the ROM in U.V. light. Therefore, erasing process is slower and time consuming it takes 15 to 20 minutes. EEPROM : Electrically Erasable PROM. This memory is functionally similar to EPROM, except that information can be altered by using electrical signals at the register level rather than erasing the information i.e., it can be erased information byte to byte. Advantages and Disadvantages: Advantages: 1. Low cost 2. High speed 3. Flexibility in system design 4. ROM is non-volatile memory Disadvantages: 1. In EPROM selective erasing is not possible. One time all the locations are erased. 2. IROM has to be removed from socket and put in eraser for erasing. 25. State and explain the difference among ROM, PROM, RAM, SRAM and DRAM. ROM : Read only memory (ROM) is the type of memory from which data can be repeatedly read out. We cant write data in this memory. It is a non-volatile memory i.e. it can hold data even if power is turned off. PROM: Programmable ROM is a ROM into which data is permanently stored by special programming device. A PROM can be programmed once after its fabrication. However another category of PROM is reprogrammable i.e. it can be programmed again and again and is referred erasable and programmable. If the erasing of PROM is using ultraviolet then it is EPROM i.e. Erasable programmable ROM.
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EC2302-DIGITAL ELECTRONICS If the erasing of ROM in using electrical voltage then it is known as electrically alterable ROM i.e. EAROM. RAM : Random Access Memory (RAM) is the memory that can be used for read as well as written operation. Here access time is same for each location. RAM is a volatile memory so it loses the stored data when power is turned off. RAM is of two types SRAM and DRAM. SRAM: Static RAM uses the flip-flop for its basic storage element. It is possible to store data as long as power is applied to the chip. It make use of cross coupled TTL multiemitter bipolar transistors or cross coupled MOSFETs for its construction. DRAM : Dynamic RAM make use of capacitive element for storing the data bit. Binary information is stored as charge. If charge is present at a capacitive element it represents a logic 1 and in the absence of the charge a logic 0 is stored. DRAMs consumes less power as compared to SRAMs. 26. Write short note on Classification and characteristics of memories. Ans. Classification and characteristics of memories Various memory devices can be classified on the basis of: 1. Principle of operation 2. Physical characteristics 3. Fabrication technology used 1. Principle of operation : The most commonly used memories are (a) Sequentially accessed memory. (b) Random access memory (RAM) (c) Read only memory (ROM) (d) Content addressable memory (CAM) (a) Sequentially accessed memories: In these type of memories the time required to access memory location is different for different locations. These are of basic two types: (i) Shift registers (ii) Charge coupled devices (CCDs). (b) RAM : Random access memory is the memory which is used for both read and write operation i.e. data can be read or placed into. Here access time is same for each location. It is of two types: (i) SRAM i.e. Static RAM (ii) DRAM i.e. Dynamic RAM
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EC2302-DIGITAL ELECTRONICS (c) ROM : Read only memory is the type from which data can be repeatedly read out but cannot be written into it. It is of two types (i) Mask programmable ROM (ii) Programmable ROM. In case of Mark Programmable ROM it is programmable at the time of manufacturing according to the information specified by the customer, and cannot be changed after packing. In case of programmable ROM, data is permanently stored but can be erased either by ultraviolet light or electrically using electric voltage. (d) CAM : Content address memory is a special purpose RAM which performs association operation in addition Read/Write operation. 2. Physical Characteristics : These are of two types :, (a) Erasable or non-erasable (b) Volatile or non-volatile (a) Erasable or non-erasable is a memory in. which the data stored can be erased or nonerased. For example : ROM is a non-erasable memory RAM is erasable memory. (b) Volatile or non-volatile: If the data stored in memory is lost where power is switched off then it is volatile memory. For example : RAM. But if the data stored is not lost when power is switched off when it is called non-volatile. For example : ROM. 3. Fabrication Technology : It is of two types (a) Bipolar (b) MOS Static RAM, ROM and PROM can be fabricated using either bipolar technology or MOS technology. But dynamic RAM, EPROM and EAROM can be fabricated using MOS devices only. 27. Draw the circuit of a static MOS RAM cell and explain its operation of Read and Write. Ans. Random .Access Memory (RAM) is a volatile memory. It can be read as well as written It has two types static RAM and Dynamic RAM The static RAM can be implemented using bipolar and MOS technology. The circuit diagram of static MOS RAM is as:
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In this circuit T1 and T3 are loads T2 and T4 are resistances. T9 is used for write operation and T10 for read operation. X and Y lines are used for addressing the cell. When X = 1 T5 and T6 will be ON when Y = 1, T7 and T6 will be ON. (i) Write operation: To make write operation, T9 is turned ON If the data is logic 1, then T3 is turned ON If data is logic 0 then T1 is ON (ii) Read operation: For read operation MOSFET (T10) is turned ON This will connect Data-line to Data-out Hence complement of stored data is read. 28. Explain the architecture and function of programmable logic arrays Ans. Programmable logic devices (PLD) are special type of ICs which can be programmed by the user and hence a combinational or sequential circuit can be implemented with these PLO s are of various types as programmable array logic (PAL) and programmable logic array (PLA) etc The block diagram of PLA device is as shown:
Input Buffers : These buffers amplify the input signal. These are also used to avoid the loading of sources connected at the input AND Matrix: It can be used to implement the product terms in the SOP form Each AND has two matrix has connections are shown by (X) mark on the line. OR Matrix: The OR matrix has OR gates of two inputs The connections are shown by cross (X) mark, on the line. lnvert/Non-lnvert: Matrix If the output in active low mode is required then it can be separated with this matrix otherwise it remain active high with non-invert matrix
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EC2302-DIGITAL ELECTRONICS 1. Draw the schematic of RTL NOR gate and explain its operation. RTL was the first to introduced. RTL NOR gate is as shown in fig.
Working: Case I: When A = B = 0. Both T1 and T2 transistors are in cut off state because the voltage is insufficient to drive the transistors i.e. VBE < 0.6 V: Thus, output Y will be high, approximately equal to supply voltage Vcc. As no current flows through Rc and drop across Rc is also zero. Thus, Y = 1, when A = B = 0. Case II : When A = 0 and B = 1 or A = 1 and B = 0. The transistor whose input is high goes into saturation where as other will goes to off cut state. This positive input to transistor increases the voltage drop across the collector resistor and decreasing the positive output voltage. Thus, Y = 0,when A= 0 and B = 1 or A = 1 and B = 0. Case III : When A = B = 1. Both the transistors T1 and T2 goes into saturation and output voltage is equal to saturation voltage. Thus, Y = 0,when A = B = 1 Truth Table
Which is the output of NOR gate.
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EC2302-DIGITAL ELECTRONICS 2. Explain DCTL NAND gate with the help of suitable circuit diagram. DCTL NAND gate circuit diagram is as shown:
Working Case I: When A = B = 0. Both transistors T1 and T2 goes to cut off state. As the voltage is not sufficient to drive the transistor into saturation. Thus, the output voltage equal to Vcc. When A = B = 0, output Y = 1 Case II: When A = 0 and B = 1 or A = 1 and, B = 0. The corresponding transistor goes to cut off state and the output voltage equals to Vcc. Thus, When A = 0 and B = 1 or A = 1 and B = 0, Output Y = 1. Case III: When A = B = 1. Both transistors T1 and T2 goes into saturation state and output voltage is insufficient to consider as 1 Thus when A B = 1, output Y = 0. Truth Table
Which is the output of NAND gate.
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EC2302-DIGITAL ELECTRONICS 3. Compare standard TTL, Low power TTL and high speed TTL logic families.
4. Give characteristics and specification of CMOS. Ans. 1 Power supply (VDD) = 3 15 Volts 2. Power dissipation (Pd) = 10 nW 3. Propagation delay (td) = 25 ns 4. Noise margine (NM) = 45% of VDD 5, Fan out (FO) = >50 5. Which TTL series is most suitable for battery powered circuits? The most suitable TTL series for battery powered circuits is the low power TTL 74L series. Its power dissipitation is about 1mW, which is very less as compared to other TTL series, It consumes less power by increasing the value of all internal resistances. 6. What are the advantages of CMOS memory chips over bipolar memory chips? Advantages of CMOS memory chip over bipolar memory chips. 1. Power dissipation per gate is very low i.e. about 0.05 the power dissipation is in milliwatts. 2. CMOS memory chips has high noise immunity than bipolar memory chips. 7. What is the minimum voltage value that is considered as highstage input in case of TTL logic family? The maximum value of voltage that is considered as high state input in case of TTL logic family is: . In case of bipolar memory chip
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8. Why TTL logic family is faster then DTL? TTL logic family is faster than DTL because in Transistor logic family the propagation delay per gate is less than or equal to 10 ns except for low power low speed L, TTL. Where, as in Diode transistor logic the propagation delay per gate in 30 ns. Hence, the speed of TTL logic family is fast as compared to DTL logic family. 9. What do you mean by interfacing? Explain its need. How will you interface TTL to CMOS? Interfacing in digital ICs are very essential so that one device or circuit can be connected with another circuit or device to met the requirement of compatibility of the load. Interfacing means to connect the output of one device or circuit to another which may have rent electrical characteristics. Following points should be noted while interfacing TTL gates and CMOS gates 1. The requirements of load circuit must be satisfied by the driver output. 2. Different power supplies are required for load and driver circuits. Thus, the output must swings between its specified voltage ranges for both circuits. Interfacing TTL to CMOS : When interfacing a TTL to CMOS IC having same +5V app1y, a pull up resistor is required. This resistor will ensure that logic 1 is sufficient voltage operate CMOS. It is as shown in fig.
When two different power supplies are used, a transistor circuit is used to isolate the TTL IC from CMOS IC as shown in fig.
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10. With the help of circuit diagram explain working of a two input ECL NOR gate? Ans. The circuit diagram of two input ECL NOR gate is as shown:
Working Case I : When A = B = 0, the reference voltage of T3 is more forward biased then T1 and T2. Thus, T3 is ON and T1, T2 remains OFF. The value of R1 is such-that the output of NOR gate is high .i.e. 1. Case II: When A = 1 or B = 1 or A = B = 1, the corresponding transistors are ON, as they are more forward biased that T3 and thus T3 is OFF. Which makes the NOR output to be low i.e. 0. This shows that the circuit works as a NOR gate. 11. Draw and explain the operation of TTL inverter. Ans.
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Tristate TTL inverter utilizer the high-speed operation of totem-pole arrangement while permitting outputs to be wired ANDed (connected together). It is called tristate TTL because it allows three possible output stages. HIGH, LOW and High-Impedance. We know that transistor T3 is ON when output is HIGH and T4 is ON when output is LOW. In the high impedance state both transistors, transistor T3 and T4 in the totem pole arrangement are med OFF. As a result the output is open or floating, it is neither LOW nor HIGH. The above fig. shows the simplified tristate inverter. It has two inputs A and E. A is the normal logic input whereas E is an ENABLE input. When ENABLE input is HIGH, the circuit works as a normal inverter. Because when E is HIGH, the state-of the transistor T1 (either ON or OFF) depends on the logic input A and the additional component diode is open circuited as cathode is at logic HIGH. When ENABLE input is LOW, regardless of the state of logic input the base-emitter junction of T is forward biased and as a result it turns ON. This shunts the current through R1 away from T2 making it OFF. As T2 is OFF, there is no sufficient drive for T4 conduct and hence T4 turns OFF. The LOW at ENABLE input also forward biases diode D2, which shunt the current away from the base of T3, making it OFF. In this way, when ENABLE output is LOW, both transistors are OFF and output is at high impedance state.
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EC2302-DIGITAL ELECTRONICS Q. 12. Why totem pole outputs cannot be connected together? It is because when one output is high the other goes low and wired ANDed connection are used, then a large current from supply +V will flows to ground through high state gate transistor and low state gate transistor. Thus, large current will flow which damages the output transistors of totem pole TTL arrangement. 13. Define noise margin. What is its importance? Noise margin is also known as noise immunity. It is defined as the ability of a logic circuit to tolerate noise without causing any unwanted changes in the output. Also, the quantative measure of noise immunity is known as noise margin. It is important because it cause the voltage to drop into the invalid range so as to avoid the effects of noise voltage. 14. Compare performance of ECL with TTL. Comparison in performance of ECL and TTL is as under.
15. Compare performance of DTL and TTL.
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EC2302-DIGITAL ELECTRONICS 16. When does a TTL circuit act as a current source and as a current sink? TTL as current source: The current is extremely small, typically of order diagram is below: Current source fake place when output of driving gate (Y) becomes high. Q3 will be ON and Q4 will be OFF. So the base emitter junction of Q1 of load gate will be reversed biased. Therefore the reverse leakage current of Q1 will be supplied by the, driving gate. . The
TTL as current sinking : It take place when output (Y) is low. The current flows from the input stage of load gate into the output stage of driving gate. Q3 is OFF and Q4 remains ON. 1 7. How do open collector outputs differ from totem pole 0/Ps? Following is the table of comparison between open collector outputs
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EC2302-DIGITAL ELECTRONICS 18. What limits the speed of TTL gate? How can the speed of TTL gate be enhanced? In case of open collector TTL output the operating speed is low. In open collector the value of pull up resistor is high i.e. of the order of few Kc2. Thus, if the load capacitor is also large then the time constant RC becomes large. Due to this the switching speed of output transistor will slow down and therefore, the speed of TTL gate also reduces. The speed of TTL gate can be enhanced if totem-pole TTL gate is used. In case of. totem-pole arrangement, when output is high the impedance at the output is very low i.e. of the order of iO.2. Therefore, the time constant RC will be very short to charge the capacitive load. Thus, increases its speed. 19. Draw the schematic of ECL OR gate and explain its operation. ECL or gate : Emitter-coupled logic (ECL) is the fastest of all logic families and thus it is used in applications where very high speed is essential. High speeds have become possible in ECL because the transistors are used in difference amplifier configuration, in which they are never driven into saturation and thereby the storage time is eliminated. Here, rather than switching the transistors from ON to OFF and vice-versa, they are switched between cut-off and active regions. Propagation delays of less than 1 ns per gate have become possible in ECL. Basically, ECL is realized using difference amplifier in which the emitters of the two transistors are connected and hence it referred to as emitter-coupled logic. A 3-input ECL gate is shown in Fig. (A) which has three parts. The middle part is the difference amplifier which performs the logic operation.
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Emitter followers are used for d.c. level shifting of the outputs, so that V (0) and V (1) are same for the inputs and the outputs. Note that two output Y1 and Y2 are available in this circuit which are complementary. Y1. corresponds to OR logic and Y2 to NOR logic and hence it is named as an OR/NOR gate. Additional transistors are used in parallel to T1 to get the required fan-in. There is a fundamental difference between all other logic families (including MOS logic) and ECL as far as the supply voltage is concerned. In ECL, the positive end of the supply is connected to ground in contrast to other logic families in which negative end of the supply is grounded. This is done to minimize the effect of noise induced in the power supply and protection of the gate from an accidental short circuit developing between the output of a gate and ground. The voltage corresponding to V (0) and V (1) are both negative due to positive end of the supply being connected to ground. The symbol of an ECL OR/NOR gate is shown in Fig. (B)
20. Give an order of magnitude which is applicable to various logic families for (a) fan-out ; (b) power dissipation per gate ; (c) propagation delay per gate; (d) clock rate. An order of magnitude which is applicable to various-logic families for different parameters are as shown in the form of table
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EC2302-DIGITAL ELECTRONICS 21. Draw the circuit of an open collector TTL NAND gate and explain its operation Ans. The circuit diagram of 2-input NAND gate open-collector TTL gate is as shown:
Working: Case.1 : When A = 0,B = 0 When both inputs A and B are low, both functions of Q1 are forward biased and Q2 remains off. So no current flows through R4 and Q3 is also off and its collector voltage is equal to Vcc i.e. Y = 1 Case2 : When A = 0, B = 1 and Case 3: When A = 1, B = 0 When one input is high and. other is low, then one junction is forward biased so Q2 is off and Q3 is also off. So collector voltage is equal to Vcc i.e. Y = 1 Case 4: When A = 1, B = 1 When both inputs are high, Q1 is turned off and Q2 turned ON Q3 goes into saturation and hence Y = 0. The open-collector output has main advantage that wired ANDing is possible in it. 22. Compare TTL, ECL, RTL, DCTL, and DTL w.r.t. fan-in, fan-out and noise margin.
Fan-in : It is the maximum number of inputs which the logic circuit can handle. Fan-out : The max-number of load gates which the driver gate can feed is called tan-out. Noise-margin : The circuits ability to tolerate noise signals is referred as noise immunity, a quantitative measure of which is called Noise Margin.
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EC2302-DIGITAL ELECTRONICS 23. Draw the circuit of TTL NAND gate and explain its operation. Compare the TTL and ECL logic families. Two input TTL NAND gate-is given in fig. (1). In this transistor T3 and T4 form a totem pole. Such type of configuration is called-as totem-pole output or active pull up output.
So, when A = 0 and B = 1 or (+5V). T1 conducts and T2 switch off. Since T2 is like an open switch, no current flows through it. But the current flows through the resistor R2 and into the base of transistor T3 to turn it ON. T4 remains OFF because there is no path through which it can receive base current. The output current flows through resistor R4 and diode D1. Thus, we get high output. When both inputs are high i.e. A = B = 1 or (+ 5V), T2 is ON and it drives T4 turning it ON. It is noted that the voltage at the base of T3 equals the sum of the base to emitter drop of T4 and of T2..
The diode D1 does not allow base-emitter junction of T3 to be forward-biased and hence, T3 remains OFF when T4 is ON. Thus, we get low output. It works as TTL NAND gate. Comparison of TTL and ECL :
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EC2302-DIGITAL ELECTRONICS 24. Draw the circuit of Totem pole NAND gate and explain its operation. Explain why these cannot be wire ANDed ? In TTL Totem pole NAND gate, multiple emitter transistor as input is used. The no. of inputs may be from 2 to 8 emitters. The circuit diagram is as shown
Case 1: When A = 0, B = 0 Now D1 and D2 both conduct, hence D3 will be off and make Q2 off. So its collector voltage rises and make Q3 ON and Q4 off; Hence output at Y = 1 (High) Case 2 and Case 3: If A = 0, B = 1 and A = 1, B=0 In both cases, the diode corresponding to low input will conduct and hence diode P3 will be OFF making Q2 OFF. In a similar way its collector voltage rises Q3 ON and Q4 OFF. Hence output voltage Y = 1 (High). Case 4: A = 1, B = 1 Both diodes D1 and D2 will be off. D3 will be ON and Q2 will ON making Q4 also ON. But Q3 will be OFF. So output voltage Y = 0. All the four cases shows that circuit operates as a NAND gate. Totem pole cant be Wired ANDed due to current spike problem. The transistors used in circuits may get damaged over a period of time though not immediately. Sometimes voltage level rises high than the allowable.
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EC2302-DIGITAL ELECTRONICS 25. Discuss the comparison of the important characteristics of various IC logic families.
Q 26. Discuss (i) CMOS inverter (ii) Tristate logic (i) CMOS Inverter: It is complementary MOSFET obtained by using P-channel MOSPET and n-channel MOSFET simultaneously. The P and N channel are connected in series, their drains are connected together, output is taken from common drain point. Input is applied at common gate terminal. CMOS is very fast and consumes less power.
Case 1. When input Vi = 0. The
(Gate source) voltage of Q1 will be 0 volt, it will be off.
But Q2 will be ON; Hence output will be equal to +VDD or logic 1.
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EC2302-DIGITAL ELECTRONICS Case 2. When input Vi = 1, The ground or logic 0. In this way, CMOS function as an inverter. (ii) Tri-state logic: When there are three states i.e. state 0, state 1 and high impendence i.e. called Tri-state logic. High impedence is considered as state when no current pass through circuit. Although in state 0 and state 1 circuit functions and current flows through it. (Gate source) voltage of Q2 will be 0 volt, it will be OFF,
But Q1 will be ON. Hence output will be connected to
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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EDAPALAYAM, REDHILLS, CHENNAI-52.

T flip-flop is known as Toggle flip-flop

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EC2302-DIGITAL ELECTRONICS K maps for S & R are: For S: For R:

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

Ans. State table is as shown:

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EC2302-DIGITAL ELECTRONICS For modified reduced state diagram:

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EC2302-DIGITAL ELECTRONICS 18. Differentiate between synchronous and asynchronous counters.

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

Q output follows D input with each other. 3. T Flip-flop:

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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

Max. frequency of operation for asynchorous counter

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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EC2302-DIGITAL ELECTRONICS 27. Compare binary counters with non-binary counters.

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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

32. Classify the sequential circuits.

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EC2302-DIGITAL ELECTRONICS Circuit

Implementation of circuit diagram:

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

R.RAMADHURAI B.E.,M.TECH AP/ECE

GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

K-map for TB:

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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY

EC2302-DIGITAL ELECTRONICS K-map for TC:

K-map for TD:

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GOJAN SCHOOL OF BUSINESS & TECHNOLOGY