James Morizio

1
Dynamic Combinational
Circuits
Dynamic circuits
Charge sharing, charge redistribution
Domino logic
np-CMOS (zipper CMOS)
James Morizio
2
Dynamic Logic
Dynamic gates use a clocked pMOS pullup
Two modes: precharge and evaluate
1
2
A Y
4/3
2/3
A
Y
1
1
A
Y

Static Pseudo-nMOS Dynamic

Precharge Evaluate
Y
Precharge
James Morizio
3
The Foot
What if pulldown network is ON during
precharge?
Use series evaluation transistor to prevent fight.
A
Y

foot
precharge transistor

Y
inputs

Y
inputs
footed unfooted
f f
James Morizio
4
Dynamic Logic
M
p
M
e
V
DD
PDN
In
1
In
2
In
3
Out
M
e
M
p
V
DD
PUN
In
1
In
2
In
3
Out
C
L
C
L
2 phase operation:
Evaluation
Precharge

n network

p network

James Morizio
5
Logical Effort
Inverter NAND2 NOR2
1
1
A
Y
2
2
1
B
A
Y
A B
1 1
1
g
d
= 1/3
p
d
= 2/3
g
d
= 2/3
p
d
= 3/3
g
d
= 1/3
p
d
= 3/3
Y

2
1
A
Y
3
3
1
B
A
Y
A B
2 2
1
g
d
= 2/3
p
d
= 3/3
g
d
= 3/3
p
d
= 4/3
g
d
= 2/3
p
d
= 5/3
Y

footed
unfooted
3
2
2
James Morizio
6
Dynamic Logic
N+2 transistors for N-input function
Better than 2N transistors for complementary static CMOS
Comparable to N+1 for ratio-ed logic
No static power dissipation
Better than ratio-ed logic
Careful design, clock signal needed
James Morizio
7
Dynamic Logic: Principles
M
p
M
e
V
DD
PDN
In
1
In
2
In
3
Out
C
L

Precharge
= 0, Out is precharged to V
DD
by M
p
.
M
e
is turned off, no dc current flows
(regardless of input values)
Evaluation
= 1, M
e
is turned on, M
p
is turned off.
Output is pulled down to zero depending
on the values on the inputs. If not,
precharged value remains on C
L
.
Important: Once Out is discharged, it cannot be charged again!
Gate input can make only one transition during evaluation
Minimum clock frequency must be maintained
Can M
e
be eliminated?
James Morizio
8
Example
M
p
M
e
V
DD
Out
A
B
C
Ratioles s
No Static Power Cons umption
Nois e Margins s mall (NM
L
)
Requires Clock

James Morizio
9
Dynamic 4 Input NAND Gate
In
1
In
2
In
3
In
4
Out
V
DD
GND

James Morizio
10
Cascading Dynamic Gates
M
p
M
e
V
DD
M
p
M
e
V
DD
In
Out1 Out2

Internal nodes can only make 0-1 transitions during evaluation period
Out2
Out1
In
V
t
V
Tn

James Morizio
11
Monotonicity
Dynamic gates require monotonically rising inputs
during evaluation
0 -> 0
0 -> 1
1 -> 1
But not 1 -> 0
Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicity
during evaluation
A

James Morizio
12
Monotonicity Woes
But dynamic gates produce monotonically falling
outputs during evaluation
Illegal for one dynamic gate to drive another!
A
X

Y
Precharge Evaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
James Morizio
13
Reliability Problems Charge Leakage
M
p
M
e
V
DD
Out
A
C
L
(1)
(2)
t
t
V
out
(b) Effect on waveforms (a) Leakage sources
precharge
evaluate
Minimum Clock Frequency: > 1 MHz
A = 0

(1) Leakage through reverse-biased diode of the diffusion area

(2) Subthreshold current from drain to source
James Morizio
14
Leakage
Dynamic node floats high during evaluation
Transistors are leaky (I
OFF
0)
Dynamic value will leak away over time
Formerly miliseconds, now nanoseconds!
Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
A

H
2
2
1 k
X
Y
weak keeper
James Morizio
15
Charge Sharing (redistribution)
M
p
M
e
V
DD
Out
A
B = 0
C
L
C
a
C
b
M
a
M
b
X
Assume: during precharge, A and B are 0, C
a
is discharged
During evaluation, B remains 0 and A rises to 1
Charge stored on C
L
is now redistributed over C
L
and C
a
C
L
V
DD
= C
L
V
out
(t) + C
a
V
X
V
X
= V
DD
- V
t
, therefore
V
out
(t) = V
out
(t) - V
DD
= (V
DD
-V
t
)
C
L
C
a
Desirable to keep the voltage drop below threshold
of pMOS transistor (why?) C
a
/C
L
< 0.2
James Morizio
16
Charge Sharing
Dynamic gates suffer from charge sharing
B = 0
A
Y

x
C
x
C
Y
A

x
Y
Charge sharing noise
Y
x Y DD
x Y
C
V V V
C C
= =
+
James Morizio
17
Charge Redistribution - Solutions
M
p
M
e
V
DD
Out
A
B
M
a
M
b
M
bl
M
p
M
e
V
DD
Out
A
B
M
a
M
b
M
bl
(b) Precharge of internal nodes
(a) Static bleeder

James Morizio
18
Secondary Precharge
Solution: add secondary precharge transistors
Typically need to precharge every other node
Big load capacitance C
Y
helps as well
B
A
Y

x
secondary
precharge
transistor
James Morizio
19
Domino Logic
M
p
M
e
V
DD
PDN
In
1
In
2
In
3
Out1
M
p
M
e
V
DD
PDN
In
4
Out2
M
r
V
DD
Static Inverter
with Level Restorer

Static inverters
between dynamic stages
James Morizio
20
Domino Gates
Follow dynamic stage with inverting static gate
Dynamic / static pair is called domino gate
Produces monotonic outputs
Precharge Evaluate
W
Precharge
X
Y
Z
A

B
C

C
A
B
W X
Y
Z
=
X
Z
H
H
A
W

B C
X Y Z
domino AND
dynamic
NAND
static
inverter
James Morizio
21
Domino Logic - Characteristics
Only non-inverting logic
Very fast - Only 1->0 transitions at input of inverter
Adding level restorer reduces leakage and
charge redistribution problems
Optimize inverter for fan-out
Precharging makes pull-up very fast
James Morizio
22
Domino Optimizations
Each domino gate triggers next one, like a string of
dominos toppling over
Gates evaluate sequentially but precharge in parallel
Thus evaluation is more critical than precharge
HI-skewed static stages can perform logic
S0
D0
S1
D1
S2
D2
S3
D3

S4
D4
S5
D5
S6
D6
S7
D7

Y
H
James Morizio
23
Dual-Rail Domino
Domino only performs noninverting functions:
AND, OR but not NAND, NOR, or XOR
Dual-rail domino solves this problem
Takes true and complementary inputs
Produces true and complementary outputs
invalid 1 1
1 0 1
0 1 0
Precharged 0 0
Meaning sig_l sig_h
Y_h
f

inputs
Y_l
f
James Morizio
24
Example: AND/NAND
Given A_h, A_l, B_h, B_l
Compute Y_h = A * B, Y_l = ~(A * B)
Pulldown networks are conduction complements
Y_h

Y_l
A_h
B_h B_l A_l
= A*B
= A*B
James Morizio
25
Example: XOR/XNOR
Sometimes possible to share transistors
Y_h

Y_l
A_l
B_h
= A xor B
B_l
A_h A_l A_h
= A xnor B
James Morizio
26
Domino Summary
Domino logic is attractive for high-speed circuits
1.5 2x faster than static CMOS
But many challenges:
Monotonicity
Leakage
Charge sharing
Noise
Widely used in high-performance microprocessors
James Morizio
27
np-CMOS (Zipper CMOS)
M
p
M
e
V
DD
PDN
In
1
In
2
In
3
M
e
M
p
V
DD
PUN
In
4
Out1
Out2

Only 1-0 transitions allowed at inputs of PUN

Used a lot in the Alpha design
James Morizio
28
np CMOS Adder
V
DD

C
i0
A
0
B
0
B
0

A
0
V
DD

B
1

A
1
V
DD

A
1
B
1
C
i1
C
i2
C
i0
C
i0
B
0
A
0
B
0
S
0
A
0
V
DD

V
DD

V
DD

B
1
C
i1
B
1

A
1
A
1
V
DD

S
1
C
i1
Carry Path
James Morizio
29
CMOS Circuit Styles - Summary