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Architecture of; 80286 Processor 80386 Processor 80486 Processor Intel Pentium Processor
80286 Features
Introduced in Feb. 1982 Originally 6.0MHz, went up to 20 MHz MIPS = 0.90 No. of Transistors = 134,000 Design Resolution (Pixel Size) = 1.5 micron Address Bus = 24 bit (16 MB) Data Bus = 16 bit Register Size = 16 bit No. of Registers = 14 No. of Instructions in Instruction Set = 225 +
Introduced Memory Management Unit to support multi tasking at the processor level. Little-Endian Architecture
80286 Processor
Flag Registers
The 8086 has 9 flags, the 80286 has 11 flags, and the 80386 has 13 flags. All of these flag registers include 6 flags related to data conditions (sign, zero, carry, auxiliary carry, overflow, and parity) and three flags related to machine operations (Interrupt, Single-step and Strings). The 80286 has two additional flags: I/O Privilege and Nested Task. The I/O Privilege uses two bits in protected mode to determine which I/O instructions can be used, and the nested task is used to show a link between two tasks. The processor also includes control registers and system address registers, debug and test registers for system and debugging operations.
80386 Features
Introduced in Oct. 1985 Originally 16MHz, went up to 33 MHz MIPS = 5.0 No. of Transistors = 275,000 Design Resolution (Pixel Size) = 1.5 micron Address Bus = 32 bit (4 GB RAM) Data Bus = 32 bit Register Size = 32 bit No. of Registers = 14 No. of Instructions in Instruction Set = eq. 80286+
Pipelined architecture. The 80386 was the first processor in the Intel family to include parallel stages in its execution cycle.
80386 Processor
Prefetch Queue
Decoding Unit
Bus Interface
Microcode ROM
Control Unit
In a microprogrammed CISC the processor fetches the instructions via the bus interface into a prefetch queue, which transfers them to a decoding unit. The decoding unit breaks the machine instruction into many elementary micro-instructions and apples them to a microcode queue. The micro-instructions are transferred from the microcode queue to the control and execution unit which drives the ALU and the registers
80486 Features
Introduced in Apr. 1989 Originally 25MHz, went up to 33 MHz MIPS = 20.0 No. of Transistors = 1.2 million Design Resolution (Pixel Size) = 1.0 micron Address Bus = 32 bit Data Bus = 32 bit Register Size = 32 bit No. of Registers = 14 No. of Instructions in Instruction Set = i386 + i387
Paging Unit
Decoding Unit
Control Unit
i486 CPU
80486 Processor
80486 Pipeline
Instruction Fetch (memory access Write-back
Write result into eax
Cycle n
Cycle n+1
Cycle n+2
Cycle n+3
Cycle n+4
Execution
Decode 1
Decode 2
Pentium Registers(1)
Instruction Pointer 31 EIP 16 15 IP 0 EFLAG EFLAG Register 16 15 31 FLAG E0
General-Purpose Registers 16 15 31 EAX EBX ECX EDX ESI EDI EBP ESP AH BH CH DH
8 7 AL BL CL DL SI DI BP SP
0 CS SS DS ES FS GS
Segment Registers 15 0
Pentium Registers(2)
15 TR LDTR TSS Selector LDTSS Selector IDTR GDTR 0 31 0 19 TSS Base Address LDT Base Address IDT Base Address GDT Base Address TSS Limit LDT Limit IDT Limit GDT Limit 0
Control Registers 31 CR4 CR3 CR2 CR1 CR0 16 15 0 DR7 DR6 DR5 DR4 DR3 DR2 16 15 0 DR1 DR0 TR7 TR6
Debug Registers 31 16 15 0
Bus Interface
TLB
TLB
BTB
Control Unit
v pipeline
u pipeline
Register
Intel Pentium
Summary