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Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators

Denis Navarro, Oscar Luc a, Member, IEEE, Luis Angel Barrag an, Jos e Ignacio Artigas, Isidro Urriza, and Oscar Jim enez, Student Member, IEEE

AbstractAdvantages of digital control in power electronics have led to an increasing use of digital pulse-width modulators (DPWM). However, the clock frequency requirements may exceed the operational limits when the power converter switching frequency is increased, while using classical DPWM architectures. In this paper, we present two synchronous designs to increase the resolution of the DPWM implemented on eld programmable gate arrays (FPGA). The proposed circuits are based on the on-chip digital clock manager block present in the low-cost Spartan-3 FPGA series and on the I/O delay element (IODELAYE1) available in the high-end Virtex-6 FPGA series. These solutions have been implemented, tested, and compared to verify the performance of these architectures. Index TermsField programmable gate arrays (FPGA), power conversion, pulse-width modulated power converters.

I. INTRODUCTION

IGITAL pulse-width modulators (DPWMs) have become a basic building block in digital control architectures of any power converter [1][7]. The DPWM frequency is mainly determined by the power converter operating conditions, whereas the DPWM resolution determines the accuracy in the output voltage/current control. As a consequence, the DPWM resolution has a direct impact in the power converter performance. Traditional DPWM implementations are based on counters and comparators, which generate the power converter gating signals according to several predened thresholds [8][14]. For these designs, the minimum on-time step is equal to the counterclock period. Its equivalent number of bits nDPW M is nDPW M = log2 fCLK fSW (1)

where fSW is the DPWM frequency and fCLK is the counterclock frequency. Nowadays, power converters are evolving toward designs with higher switching frequencies in order to reduce the

Manuscript received February 8, 2011; revised July 13, 2011 and August 29, 2011; accepted October 20, 2011. Date of current version February 27, 2012. This research was supported in part by the Spanish MICINN under Project TEC2010-19207, Project CSD2009-00046, Project IPT-2011-1158920000, and the FPU grant AP2010-5267, and by the Bosch and Siemens Home Appliances Group. Recommended for publication by Associate Editor L. M. Tolbert. The authors are with the Department of Electronic Engineering and Communications, University of Zaragoza, Zaragoza 50018, Spain (e-mail: denis@unizar.es; olucia@unizar.es; barragan@unizar.es; jiartigas@unizar.es; urriza@unizar.es; ojimenez@unizar.es). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2011.2173702

size of inductors and capacitors. Besides, for the digital implementation, the number of bits nDPW M has to be higher than the A/D converter resolution to avoid limit cycling [15][17]. As a consequence, an unfeasibly high clock frequency can result, increasing the complexity and the cost of the nal implementation [18]. Moreover, recent developments in semiconductor technology enable the use of higher switching frequencies through SiC [19] and GaN [20] power devices. This allows the design of power converters with reduced size and cost, and improved dynamic behavior and power density, as shown in [21] and [22]. However, these designs require high-frequency high-resolution PWMs (HRPWMs) in order to take the most of the power converter. Another eld of application for HRPWMs is the dcdc converters, where either the output voltage [voltage regulator modules (VRMs)], the duty cycle for output-power control [23], or the switching delay mismatch between power devices [24], [25] need to be accurately tuned. As a conclusion, the evolution of both power electronics and digital control techniques makes the development of higher resolution DPWMs [26] necessary. To overcome this problem, different solutions have been proposed depending on whether the digital controller is implemented on a digital signal processor (DSP), an applicationspecic integrated circuit (ASIC), or a eld programmable gate array (FPGA). In the case of DSPs, some of them include HRPWM peripherals [27]. The HRPWM module extends the time resolution capabilities of the conventional PWM allowing a minimum time step that is a fraction of the system clock. Besides, several architectures have been proposed for IC implementation [28][30]. They are usually based on a tapped delay line in combination with a multiplexer [28] or a hybrid counter/delay line [30]. Several FPGA-based solutions have also been proposed in the literature [31][38]. One common solution is to use a coarse resolution counter-based stage plus one or several on-chip digital clock manager (DCM) blocks. The PWM signal is set at the beginning of the counter period, and it is reset after a given number of clock cycles plus a certain fraction of the clock period established by the DCM. Apart from [35] and [38], the circuits previously published for delaying the reset signal are not fully synchronous. Asynchronous circuits make harder to perform static timing analysis and can result in glitching since controlling the logic and routing delays in an FPGA is more difcult than in ASIC implementations. A synchronous design, therefore, improves the reliability

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TABLE I HRPWM ARCHITECTURE COMPARISON

of the circuit and eases the design process. Besides, it makes the design more independent of the technology, easing the design portability. In Table I, a brief comparison of the FPGA-based architectures classied according to the coarse counter frequency, the achieved resolution, and the number of paths to manually equilibrate is given. The higher the number of paths to equilibrate is, the harder the design of a monotonic DPWM is. Besides, it is pointed out if they are fully synchronous and glitch-free designs, due to the combinational circuit usage. The aim of this paper is to propose two fully synchronous high-resolution DPWM architectures in order to avoid the need of using unfeasible high clock frequencies, providing a more convenient nal implementation. Both of them are based on the resources available in modern FPGAs. The rst proposed architecture, presented in [39], is a generalization of the DCMbased circuit in [35], and it allows operating the circuit at higher clock frequencies [39]. The second proposal is based on the I/O delay element (IODELAYE1) available in the Virtex-6 FPGAs, and it provides higher resolution with a straightforward implementation. This paper is organized as follows. The proposed highresolution DPWM architectures using DCM blocks and IODELAYE1 blocks are explained in Sections II and III, respectively. The experimental results for the proposed architectures are shown in Section IV. Section V includes further discussion and some guidelines for the architecture selection. Finally, the conclusions of this study are drawn in Section VI. II. HIGH-RESOLUTION DPWM ARCHITECTURE USING DCM BLOCKS The key of this architecture is the on-chip DCM block provided in almost every state of the art FPGA (see Fig. 1). The following DCM clock management features [40] will be used. 1) Phase shifting: The DCM provides four phase-shifted clock signals derived from the source clock CLKIN. In addition to CLK0 for zero-phase alignment to the CLKIN signal, the DCM also provides the CLK90, CLK180, and CLK270 outputs for 90 , 180 , and 270 phase-shifted signals, respectively. Besides, all the outputs of the DCM can be phase shifted with ner resolution. 2) Frequency synthesis: The DCM can generate a wide range of output clock frequencies (CLKFX output port), performing clock frequency division and multiplication. Besides phase shifting, the DCM is able to condition the clock input CLKIN in order to obtain clock outputs with 50% duty

Fig. 1

Simplied pinout description of the DCM block.

Fig. 2.

Fixed ne phase shifting effect.

cycle. The clock feedback signal CLKFB is used to compare and lock the output signals with the input CLKIN signal. The ne phase shifting can be xed (specied at design time and set during the FPGA conguration process) or variable. It is set by means of the DCM attribute PHASE_SHIFT, an integer in the range [255, +255]. Fig. 2 shows the ne phase shift effects in the xed mode of operation. A phase-shifted output with a resolution of (1/256)th of the input clock period can be obtained. The variable phase-shifting feature has been used in [33]. However, this operating mode requires several clock cycles to change the duty cycle, degrading the dynamic performance. Besides, an asynchronous circuit is used to divide the clock cycle into four quadrants. In this paper, a fully synchronous design with xed phase shifting is proposed. A. First Approach In order to introduce the proposed DCM-based highresolution DPWM architecture, let us consider a rst version to obtain a 2-bit resolution increase (see Fig. 3). This architecture is basically the one presented in [35].

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Fig. 3.

DCM-based HRPWM rst approach.

In this rst version, the quadrant phase-shifted outputs of a single DCM are used. The duty cycle command dc(m:0) has m+1 bits, ranging from m to 0, and the counter CNT has m1 bits. CLRD signal is set when the m1 most-signicant bits (MSBs), dc(m:2), are equal to CNT; and SETD signal is set when CNT is equal to zero and dc(m:2) is different from zero. Fig. 4 shows how the circuit works with m = 4, and dc = 10010. Basically, when the counter CNT is equal to the m1 MSBs of the duty command dc, signal CLRD activates. The resulting pulse is captured in the next clock cycle by FF0, and phase shifted 90 , 180 , and 270 by ip-ops FF1, FF2, and FF3, respectively. These four FFs implement a multiphase synchronous circuit [41]. The two least-signicant bits (LSBs) of the duty command are used by the multiplexer to select the phase-shifted signal that clears the SR latch. The advantage of this proposal in relation to others is that the digital circuit that generates the reset of the SR latch is synchronous. The use of asynchronous circuits to reset the latch makes harder to calculate timing using static timing analysis and can result in glitching since controlling the logic and routing delays in an FPGA is more difcult than in ASIC implementations. The next section presents an improved and scalable architecture in order to improve the HRPWM resolution.

B. Generalization of the DCM-Based Architecture The previous architecture can be scaled to enhance the HRPWM resolution. Let n = m + k be the bits of the duty cycle command dc, with k 2. Basically, the proposed circuit is made up of a synchronous m-bit counter, r DCMs, p = 4r edge-triggered ip-ops, a p-to-1 multiplexer, and an SR latch whose output is the PWM signal. The modulus of the counter is congurable. The CLRD signal is set when the counter is equal to the m MSBs of dc. The SETD signal is set when the counter is zero and dc is different from zero. These signals are used to generate the SET and RESET signals that control the SR latch. The counter and all DCMs are clocked by the same input clock signal CK. Quadrant phase-shifted outputs CLK0, CLK90, CLK180, and CLK270 of DCMs are used to generate a set of p phase-shifted clocks {CKi } with 0 i < p. All clock signals CKi have the same period TCK with 50% duty cycle. CKi is phase-shifted TCK /p time with respect to CKi 1 [see Fig. 5(a)]. The ne phase shifting in the xed mode shifts the phase of all DCM output signals by a xed fraction of the input clock period. Being the minimum phase shift 1/256 of TCK (k 8),

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Fig. 4.

DCM-based HRPWM operation with dc = 10010.

the circuit is designed, such as the minimum allowable delay for paths, in which the source and destination clocks are different, is TCK /2, regardless the phase number. By doing so, the maximum clock frequency is not limited by the multiphase circuit but for the DCM, and it can be easily scaled to the required p number. In the circuit shown in Fig. 5(b), the period constraint is less restrictive than in the previous design, and a higher clock frequency can be achieved: tp m ax (FFi ) + tp m ax (net) + tSU FFp/ 2+ i < TCK i m ax CKi , CKp/ 2+ i 2 (2)

where tp m ax (FFi ) and tSU FFp /2+ i are the maximum clockto-output propagation time and the setup time of a ip-op, respectively; tp m ax (net) is the routing delay, TCK0 /2 is the nominal time difference between rising edges of CK0 and CK2, and m ax (CK0, CK2) is the maximum difference in the arrival time of the rising edges of CK0 and CK2 in relation to its nominal value. For a particular FPGA series, the value of p is constrained by the number of DCM blocks available, the number of global clock lines that each DCM block can drive up, and the need to ensure that the routing delay of the multiplexer inputs is less than TCK /p for a monotonic behavior.
Fig. 5. (a) Phased clock signals. (b) Multiphase synchronous circuit.

C. Implementation This section describes an implementation example carried out to show the feasibility of the DCM-based HRPWM architecture proposed in this study. As the implementation depends on the FPGA, let assume that the high-resolution DPWM is implemented in the Xilinx XC3S500E Spartan-3E FPGA of the S-3E Starter Kit board by Digilent. This board includes a 50-MHz clock oscillator that is used as the input clock. As the FPGA has four DCMs, the parameter k can be up to 4. As an example, Fig. 6 shows an implementation with m = 8,

the phase-shift value for DCMj must be set to j64/r with 0 j < r. The p ip-ops [see Fig. 5(b)] implement a multiphase synchronous circuit. FFi is triggered by the rising edge of CKi . A p-to-1 multiplexer uses the k LSBs of dc to select the CLRi signal that clears the SR latch. CLRi is delayed by a fraction 1/p of TCK with respect to CLRi 1 . In order to improve speed,

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Fig. 6.

Implemented high-resolution DPWM with m = 8 and k = 3.

and k = 3. It has been described in VHDL. DCMx4 multiplies its input clock frequency by 4. The CLKFX output of DCMx4 is connected to the input clock of the counter, DCM0 and DCM1 . The binary counter has 8 bits, and SETD and CLRD signals are generated from the counter output and the eight MSBs of dc as explained earlier. FFa and FFb store these signals. Negativeedge-triggered ip-ops FFc and FFd avoid malfunctions due to the phase offset between CK and CK0 (200 ps max. according to the data sheet). DCM0 and DCM1 generate eight phased clocks {CK0 ,. . ., CK7 }. PHASE-SHIFT attribute of DCM0 is set to 0. DCM0 generates clocks CK0 , CK2 , CK4 , and CK6 . PHASE-SHIFT attribute of DCM1 is set to 32, and its outputs are shifted 32/256 of TCK . DCM1 generates clocks CK1 , CK3 , CK5 , and CK7 . In the implementation step of the design ow, DCM0 and DCM1 are manually placed at DCM_X0Y0 and DCM_X1Y0, respectively, in order to be close to each other and reduce routing delays. These two DCMs can drive up to four global clock lines. Then, the circuit must work with the rising and falling edges of only four phased clocks {CK0 , CK1 , CK2 , CK3 }, and FF4, FF5, FF6, and FF7 must be negative-edge triggered. This introduces nonlinearity in the on-time step due to duty-cycle variation but

this effect cannot be solved due to the routing architecture of this FPGA. For this implementation, the maximum clock frequency is limited to 200 MHz, which is the maximum operating frequency for the CLK90 and CLK270 DCM outputs according to the FPGA datasheet. However, it is important to note that if there were paths in the implementation in which the difference between active clock edges of source and destination ip-ops were lower than the one present in this design (TCK /2), the timing constraint would be more restrictive than the one expressed in (2) and the maximum clock frequency would be reduced. For instance, a clock difference of TCK /4, as it occurs in Fig. 3, would lead to the 168-MHz maximum operating frequency. In this case, the multiphase circuit would limit the operation instead of making the most of the FPGA DCM resources. The proposed architecture can also be implemented using the high-end Virtex-6 FPGA series. In these FPGAs, the DCM block has been replaced by the mixed-mode clock manager (MMCM), which provides improved functionalities and jitter performance. The MMCM provides output signals with a 45 phase shift. The DCM0 and DCM1 can therefore be replaced by a single MMCM, and a higher resolution can be achieved

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When in this mode, the IODELAYE1 reset signal resets the delay value to a value set by the CNTVALUEIN, as shown in Fig. 8. The delay time is, therefore, calculated as td = ttap CNTVALUEIN, and the current delay value can be read in the CNTVALUEOUT signal. A. Proposed Architecture Fig. 9 shows the proposed implementation for an m+1-bit HRPWM. Basically, the proposed circuit is made up of a synchronous m4 bit counter, an IODELAYE1 block, two edgetriggered ip-ops, an MMCM, and an SR latch whose output is the PWM signal. The main difference with the previous proposal is that the multiphase synchronous circuit used to generate the signal RESET is replaced by the IODELAYE1 block, making the implementation easier. Signals SETD and CLRD are generated as previously explained by comparing the counter output CNT with the most m5 signicant bits of the duty command dc(m:5). FFa and FFb are placed in order to avoid the glitches that may be present in the output of the comparator. For this implementation, the loadable variable mode for the IODELAYE1 block is used. The IODELAYE1 block allows, therefore, delaying the input signal through a 5-bit value CNTVALUEIN updated when the NVALUE signal is activated, which has to be synchronized with the C clock. Considering that the maximum 32-tap delay covers half a period of CK_REF, a clock that doubles the CK_REF frequency is required to clock the counter. These clock signals are generated through the MMCM using as a reference the board base clock CK. The output frequency for the MMCM output i is set through its attributes M, D, and Oi as fCK O i = M/(D Oi ). In addition to this, the IDELAYCTRL is instantiated in order to autocalibrate the delay tap as previously explained. Fig. 10 shows the basic operation of the proposed IODELAYE1-based HRPWM architecture with dc = 10010011. The CLRD signal is activated when dc(7:5) = CNT(7:5) = 100 = 4. The resulting pulse is captured in the next clock cycle by FFb, which generates the input signal for the IODELAYE1 block DATAIN. The IODELAYE1 block generates the RESET signal by delaying the CLR signal a number of tap cycles given by dc(4:0) = 10011 = 19. This signal clears the SR latch to generate the desired PWM signal. B. Implementation The proposed IODELAYE1-based HRPWM architecture has been implemented in a Xilinx Virtex-6 XC6VLX240T1FFG1156 in the ML605 Evaluation Kit featuring a 200-MHz oscillator that is used as the input clock. The REF_CK clock frequency for the IODELAYE1 block has been set to 200 MHz, achieving a resolution ttap = ton = (1/ (32 2 fCK REF )) = 78 ps. Therefore, the CK2 clock frequency for the counter and the ip-ops is 400 MHz. These clock signals are generated through the MMCM congured with M = 8, D = 2, O1 = 2, and O2 = 4. The proposed design can operate correctly with 32-bit counters, allowing generating up to 10-s-width pulses with 78-ps resolution. If required by the

Fig. 7. Simplied pinout description of (a) I/O delay element IODELAYE1 and (b) IDELAYCTRL block.

using this architecture, as it is shown in the experimental results. In spite of this, Virtex-6 FPGAs provides additional resources, which allow obtaining better HRPWM resolution. In the next section, we present the proposed architecture to implement the HRPWM based on the IODELAYE1 block. III. HIGH-RESOLUTION DPWM ARCHITECTURE USING IODELAYE1 BLOCKS The second approach uses the I/O delay element (IODELAYE1) [42] present in Virtex-6 series FPGAs. The IODELAYE1 block allows generating a signal (DATAOUT) delayed by a certain number of tap delays with respect to the input (DATAIN). The IODELAYE1 tap resolution is given by ttap = 1/(32 2 fCK REF ), providing a ne delay-time td adjustment. The reference frequency fCK REF is set through the block attribute REFCLK, and it can be either 200 10 or 300 10 MHz. Besides, it provides additional ports to congure the increment/decrement mode (CE), increment/decrement delay (INC), and reset (RST), which allows controlling the desired delay. These signals are synchronized with the clock signal C. When using the IODELAYE1 block, the IDELAYCTRL block must be also instantiated. This block continuously calibrates the delay elements in order to reduce the inuence of process, voltage, and temperature variations by using the supplied REFCLK. Fig. 7 shows the pinout description of the IODELAYE1 and IDELAYCTRL blocks. The IODELAYE1 block offers three different operational modes when operating in the unidirectional input delay conguration, depending on the mechanism used to select the number of delay taps. 1) Fixed: The number of delay taps is predened through the block attributes and it cannot be changed during operation. 2) Variable: The number of delay taps can be dynamically changed after conguration through the control signals CE and INC. When the enable increment/decrement signal (CE) is activated, the number of delay taps increases or decreases depending on whether the INC signal is activated or not. If the reset signal RST is activated, the delay value is reset to a predened value. 3) Loadable variable: This mode has the same functionality as the variable mode. In addition to this, it allows loading the delay value through the 5-bit input CNTVALUEIN.

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Fig. 8.

IODELAYE1 operation in the loadable variable mode.

Fig. 9.

Implemented high-resolution DPWM with the IODELAYE1 block.

Fig. 10.

IODELAYE1-based HRPWM operation with dc = 10010011.

application, the tap resolution could be improved up to 56 ps by selecting a 300-MHz clock for the IODELAYE1 block. IV. EXPERIMENTAL RESULTS This section presents the main experimental results for the proposed DCM-based and IODELAYE1-based HRPWM architectures. The DPWM output has been assigned to the SMA connector of the development boards, and connected through a coaxial cable to a Tektronix DPO7354 oscilloscope (3.5-GHz bandwidth) as can be seen in Fig. 11. The DPWM signal frequency and duty cycle have been selected for test purposes; so, the complete pulse and minimum ton can be captured and measured in a single oscilloscope screen. Fig. 12 shows the pulse width and pulse-width increment for the DCM-based HRPWM architecture. The values have been

measured with the oscilloscope for nine consecutive duty commands differing in one LSB from each other. This way, the different values of the three LSBs of the duty cycle are tested. The monotonic behavior can be noticed. The expected on-time step ton was 625 ps. There is an offset due to the fact that the RESET signal goes through a multiplexer and the SET signal does not (as seen in Fig. 6). It could have been reduced as in [35] or by triggering FFe with the rising edge of CK2, but normally the offset will be compensated by the digital controller. Fig. 13 shows the traces of the DCM-based DPWM pulses corresponding to the duty commands shown in Fig. 12 from the maximum duty (top) to the minimum (bottom). As has been explained in Section II, the DCM-based architecture can also be implemented by using the MMCM blocks present in Virtex-6 FPGAs. This approach has been tested using a 400-MHz clock for the MMCMs, which leads to a 312-ps

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Fig. 11. Experimental setup for measurements: S-3E Starter Kit board with (a) Xilinx XC3S500E and (b) ML605 Evaluation Kit with Xilinx XC6VLX240T.

Fig. 13. Measured DPWM pulses with horizontal scale 2.5 ns/div, from (a) duty command 11000 to 10100, and (b) 10100 to 10000 for the DCMbased architecture.

in the previous implementation. The nonmonotonic behavior of the last point 100000 is due to the jitter in the delay chain inside the IODELAYE1 block. The datasheet for the Virtex-6 FPGAS species a 5-ps-per-tap jitter; so, the obtained results are within the device specications. This may be solved by using only 30 taps, instead of the 31, and using the appropriate scale factor as explained in [27]. Fig. 16 shows the traces of the IODELAYE1-based DPWM pulses for a four-tap increment.
Fig. 12. DCM-based HRPWM architecture performance for duty commands from 10000 to 11000. (a) Pulse width. (b) Pulse-width increment.

V. DISCUSSION This paper details two HRPWM implementations based on the DCM and the IODELAYE1 blocks available in modern FPGAs. The designer should select the most suitable one according the specications of resolution, cost, and number of PWM outputs. Some guidelines are given in the following. In Table II, we summarize the characteristics of the proposed HRPWM architectures. Compared to the previous implementations (see Table I), the proposed architectures achieves higher resolution, while keeping a fully synchronous design. Besides, these are glitch-free designs, which improve the circuit reliability, and the number of paths to equilibrate in order to achieve a monotonic behavior is minimized. The DCM-based architecture uses the DCM blocks present in almost every modern FPGA. Unlike other high-resolution architectures proposed in the literature, the maximum clock

resolution. The experimental results including the pulse width and pulse-width increment for the MMCM-based architecture are shown in Fig. 14. These results show a lower deviation than the DCM-based architecture, mainly due to the improvement of clocking jitter in Virtex-6 FPGAs. The experimental results for the IODELAYE1-based HRPWM architecture are shown in Fig. 15(a) and (b), where the pulse width and pulse-width increment are shown, respectively. These measurements have been also performed for 32 consecutive values of the duty command. Each duty command differs in one LSB from each other, which correspond to one tap delay of the IODELAYE1 block. The expected on-time step ton for this architecture is 78 ps. The results show a monotonic behavior and a more stable value of the on-time step than

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Fig. 15. IODELAYE1-based HRPWM architecture performance for duty commands from 000000 to 100000. (a) Pulse width. (b) Pulse-width increment.

Fig. 14. MMCM-based HRPWM architecture performance for duty commands from 10000 to 11000. (a) Pulse width. (b) Pulse-width increment.

frequency is determined by the DCMs instead of the multiphase circuit. This allows an efcient HRPWM implementation for low-cost systems. As the number of DCM blocks is limited, this architecture is recommended for systems requiring a few PWM outputs. In contrast, the IODELAYE1-based architecture achieves a higher resolution by using the resources present in the high-end Virtex-6 FPGA series. This architecture features a straightforward implementation as it uses a single block instead of the multiphase circuit. The architecture is simplied and there is no need to equilibrate the propagation paths. One of the main advantages of this proposal compared to the previous one is that it allows generating as many PWMs as needed, as each I/O tile in Virtex-6 FPGAs contains two IODELAYE1 blocks. This architecture is, therefore, recommended for systems requiring higher resolution or a high number of PWM outputs. The DCM-based architecture can also be implemented in the Virtex-6 FPGA series using the MMCM blocks available. However, the increased cost compared to the Spartan-based solution does not justify it, as the IODELAYE1 block achieves better performance. If we consider the ratio = 1/f clk, max ton , m in as a measure of the architecture efciency, the DCM and IODELAYE1-based proposals can be compared. The DCMbased architecture obtains DCM = 1/(200 MHz 625 ps) = 8, whereas the IODELAYE1-based architecture obtains DCM =

Fig. 16. Measured DPWM pulses for a four-tap increment with horizontal scale 2.5 ns/div, from (a) duty command dc (5:0) 100000 to 010000, and (b) 001100 to 000000 for the IODELAYE1-based architecture.

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TABLE II PROPOSED HRPWM ARCHITECTURES COMPARISON

1/(400 MHz 78 ps) = 32. The IODELAYE1-based architecture presents a four times better efciency that leads to a more power-efcient architecture. VI. CONCLUSION Advances in power electronics and digital control have made necessary the development of high-resolution DPWMs to take the most of either high-frequency or high-precision power converters. In this paper, we have proposed two novel fullysynchronous HRPWM implementations using different FPGA resources: the DCM and the I/O delay element (IODELAYE1). The DCM-based architecture can be implemented using the resources present in low-cost FPGAs, and the maximum clock frequency is determined by the DCMs instead of the multiphase circuit. On the contrary, the IODELAYE1-based architecture offers a higher resolution and number of PWM outputs with a straightforward implementation using the high-end Virtex-6 FPGAs. Both solutions are complementary and cover a wide spectrum of cost/performance applications. The proposed DCM-based and IODELAYE1-based synchronous architectures have been implemented on a Xilinx Spartan-3E and Virtex-6 FPGA, respectively. The experimental results show a resolution of 625 ps for the DCM-based architecture, and 78 ps for the IODELAYE1-based architecture, showing the feasibility of the proposals. REFERENCES
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Oscar Luc a (S04M11) received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Zaragoza, Zaragoza, Spain, in 2006 and 2010, respectively. He is currently an Assistant Professor with the Department of Electronic Engineering and Communications, University of Zaragoza. His main research interests include induction-heating applications, multiple-output power converters, resonant inverters, and digital control and modulation strategies applied to power converters. Dr. Luc a is a member of the Aragon Institute for Engineering Research.

Luis Angel Barrag an received the M.Sc. and the Ph.D. degrees in physics from the University of Zaragoza, Zaragoza, Spain, in 1988 and 1993, respectively. He is currently an Associate Professor with the Department of Electronic Engineering and Communications, University of Zaragoza. He has been involved in different research and development projects on induction heating systems for home appliances. His research interests include digital circuits design and digital control of inverters for induction heating applications. Dr. Barrag an is a member of the Aragon Institute for Engineering Research.

Jos e Ignacio Artigas received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Zaragoza, Zaragoza, Spain, in 1989 and 1996, respectively. He is currently an Associate Professor with the Department of Electronic Engineering and Communications, University of Zaragoza. He has been involved in different research and development projects. His main research interests include digital control of switching converters for induction heating and the use of information and communications technologies to improve the quality of life.

Denis Navarro received the M.Sc. degree in microelectronics from the University of Montpellier, France, and the Ph.D. degree from the University of Zaragoza, Zaragoza, Spain, in 1987 and 1992, respectively. Since September 1988, he has been an Associate Professor with the Department of Electronic Engineering and Communications, University of Zaragoza. He is involved in the implementation of new applications of ICs. In 1993, he designed the rst SPARC microprocessor in Europe. His current research interests include computer-aided designs for very large scale integration, low power application-specied IC design, and modulation techniques for power converters. Dr. Navarro is a member of the Aragon Institute for Engineering Research.

Isidro Urriza received the M.Sc. and Ph.D. degrees in electrical engineering from the University of Zaragoza, Zaragoza, Spain in 1991 and 1998, respectively. He is currently an Associate Professor with the Department of Electronic Engineering and Communications, University of Zaragoza. He has been involved in different research and development projects. His main research interests include digital implementation of modulation techniques for power converters. Dr. Urriza is a member of the Aragon Institute for Engineering Research.

Oscar Jim enez (S10) received the M.Sc. degree in telecommunications engineering from the University of Zaragoza, Zaragoza, Spain, in 2009. He is currently working toward the Ph.D. degree at Department of Electronic Engineering and Communications, University of Zaragoza. His research interests include the eld of domestic induction-heating, resonant inverters, and digital control applied to power converters. Mr. Jim enez is a member of the Aragon Institute for Engineering Research.