Future Directions in Silicon ICs for RF Personal Communications

RF Transceivers in PCS Systems Typical Current Implementations New Approaches for Low-Power RF Transceivers Examples and Current Status

Slide 1

Evolution of PCS in the Communications Infrastructure

Fiber Optic Backbone > 1Gbit/sec

COMPUTE SERVERS

WIRELESS BASE STATIONS

VIDEO DATABASE

SPEECH RECOGNITION

Compressed Video

LARGE COMMERCIAL DATABASE Airline schedule, Newspaper, ...

LOCAL PORTABLE TERMINAL - Video - Speech - X-terminal

MID-RANGE PERSONAL COMMUNICATORS -Cordless PBXs -PCS Systems

WIDE-AREA PERSONAL COMMUNICATORS - Enhanced Cellphones -Personal numbers - World wide coverage

Slide 2

Low-Power PCS Terminal Design

BATTERY (40+ lbs)

Architecture Optimization Low-Power Digital, DSP Power-Optimized Display

Key Element: Low-Power RF Transceiver

Slide 3

Summary of Cellular Phone, Cordless Phone, LAN PCS Standards

Parameter
Origin Access Modulation Baseband lter Data rate per RF channel FM Deviation RF Channel frequencies
NA

AMPS
EIA/TIA FDD FM

IS54
EIA/TIA FDM/FDD/TD M pi/4QPSK Root raised cosine 48kb/sec (2bits/symbol) NA 824.04848.97(X) 869.04893.97(R) 833 30kHz slow

GSM
ETSI FDM/ FDD/ TDM GMSK, diff Root raised cos. beta=0.3 270.8kb/sec

JCP

DECT
ETSI FDM/TDM/ TDD UK

CT2

PHP
Japan TDM/TDD pi/4-DQPSK Root Nyquist alpha=0.5 384kb/sec

802.11FH
IEEE FH/FDM (G)FSK 500kHz LP 1Mb/sec/2Mb/ sec ~150kHz 2.4-2.5GHz

FDM/TDD GFSK Gaussian BT=0.5 72kb/sec

pi/4DQPSK Root raised cosine 42kb/sec (2bits/symbol) NA

GFSK Gaussian BT=0.5 1.152Mb/sec

3khz 824.04848.97(X) 869.04893.97(R) 833 30kHz slow

NA 890-915(X) 935-960(R)

288kHz 0:1897.344MH z, 9:1881.792MH z

14.4-25.2kHz 1:864.15MHz 40:868.05MHz

NA 18951911MHz

No of RF Channels Channel Spacing Synthesizer switching speed Frequency Accuracy Speech channels per RF Channel (full/half rt) Speech coding Frame Length Peak Power: Power Control rqmt

124 200kHz

1600

10 1.728MHz 30us(BS) 450us(HS) 50kHz

40 10kHz 1ms(ch-ch) 2ms 10kHz

52 300kHz 30us(BS) 1.5ms(HS) 3ppm

75 1MHz several us

2.5ppm

200Hz

8/16

3/6

12/24

1/1

4/8

NA

Analog companded NA 3W(6max) 7 steps

VCELP 8kb/s 40ms 3W(6max) 7 steps

RELP-LTP 13kb/sec

VCELP 8kb/sec

32kb/s ADPCM 10ms(12Tx+1 2Rx)

32kb/s ADPCM 2ms (1Tx+1Rx) 10mW no

32kb/s ADPCM 5ms (4Tx+4Rx) 100mW

NA

3W(20max

250mW no

1 watt? no

Slide 4

Adaptive, Multistandard RF Modems

BATTERY (40+ lbs)

Slide 5

Key Goals for ICs for RF Transceiver Implementations

Minimum Power Dissipation Minimum Cost, Form Factor Extendable to Higher Data Rates Adaptable to Multiple RF Transmission Standards

Slide 6

Typical Current RF Transceiver Implementation

Slide 7

Block Diagram, Typical MultiTechnology RF Transceiver

RF LNA/Mixer/VCO

Receiver
IF Mixer ADC 90 I

VCO Tank Channel Select PLL

IF, AGC ADC IF PLL Tank DAC

Discrete GaAS Bipolar Si CMOS Si

Slide 8

90 Power Amplifier VCO Modulator Transmit PLL DAC Q

Transmitter

Tank

Ultimate Objective:
Single-Chip, Scaled CMOS or BiCMOS Minimum External Components

Slide 9

Future Directions in Silicon ICs for RF Personal Communications

RF Transceivers in PCS Systems Typical Current Implementations New Approaches for Low-Power RF Transceivers Examples and Current Status

Slide 10

Keys to Progress in Low-Power Adaptive RF Transceiver Design

New Receiver Architectures Low-Power CMOS/BiCMOS RF Circuit Design New Approaches for Low-Noise On-chip Synthesis RF-Compatible CMOS/BiCMOS Technologies Low-Power A/D and Digital for Baseband Processing Control of Chip, Package Parasitic RF Paths

Slide 11

Direct Conversion RF Transceivers

Superheterodyne example
RF Filter 1.8GHz 1.6GHz L.O. IF Filter 200MHz ADC Baseband Processing ADC 200MHz L.O. Data out

Direct Conversion example

RF Filter 1.8GHz 1.8GHz L.O. ADC Baseband Processing ADC Data out

Slide 12

Low-Frequency Errors in Direct Conversion Receivers

Circuit-related noise and offsets, 5-10mV RF Filter 1.8GHz 10 microvolts 1.8GHz 100 microvolts Parasitic Path 1.8GHz L.O. + + LPF Gain ADC Baseband Processing ADC Data out

10mV 100uV
Freq

Desired signal often has L. F. information Time-varying offsets 100X bigger than signal

Slide 13

Approaches for Practical Direct Conversion Recievers

Optimize coding for short-term DC balance Low-IF architectures Decision-Directed DC offset removal Quasi-direct conversion

Slide 14

Decision-Directed Offset Removal

Utilize DC Balanced Preamble to Data Packet
Preamble, ~16 bits 0101010 Data, ~500 bits (1Mb/sec) Etc. Channel 2 Channel 1

Receive Frame (10ms)

Slide 15

Transmit Frame (10ms)

Decision-Directed Offset Removal

Circuit-related noise and offsets, 5-10mV

RF Filter 1.8GHz 10 microvolts 1.8GHz 100 microvolts Parasitic Path

+ +

LPF Gain

ADC Baseband Processing ADC

Data out

100uV
1.8GHz L.O.

Time-varying DC Offsets tracked and removed in analog path Key is coupling DSP to analog path

Slide 16

Quasi-Direct Receiver Architectures

Conventional Super-Heterodyne
LNA IF A/D

LO1 Synth.

I Synth

Q LO2

Variable Freq. LO1

Fixed Freq. LO2

Quasi-Direct Conversion
LNA I Q I Q A/D

LO1 Synth Ring Osc.

LO2 Synth Ring Osc.

Fixed Freq. LO1

Slide 17

Variable Freq. LO2

Keys to Progress in Low-Power Adaptive RF Transceiver Design

New Receiver Architectures Low-Power CMOS/BiCMOS RF Circuit Design New Approaches for Low-Noise On-chip Synthesis RF-Compatible CMOS/BiCMOS Technologies Low-Power A/D and Digital for Baseband Processing Control of Chip, Package Parasitic RF Paths

Slide 18

Noise Figure in LC-Tuned RF Ampliers

Broadband Case Narrowband Case

C Vin Rs Vin Rs

fsignal<<ft
2 3 NF = 1 + + others gm Rs

fsignal<<fmax
2 3

NF = 1 +

Kg m R s

+ others

Slide 19

Example Tuned RF Amplier

Ll

Rs

Ls Lm

Key Points: L-C Narrowband Design is essential for RF LNA, Power amplier. Inductor Q, capacitor Q, and device fmax are the critical technology parameters
Slide 20

Keys to Progress in Low-Power Adaptive RF Transceiver Design

New Receiver Architectures Low-Power CMOS/BiCMOS RF Circuit Design New Approaches for Low-Noise On-chip Synthesis RF-Compatible CMOS/BiCMOS Technologies Low-Power A/D and Digital for Baseband Processing Control of Chip, Package Parasitic RF Paths

Slide 21

Why is Synthesizer Phase Noise Important?

RF input Pwr,
Undesired Channel -30dBm Desired Channel -115dBm Desired Signal Noise

freq
30kHz (IS54)

Syn. Outp. Pwr

LNA

freq
Center Frequency
~900MHz

Synthesizer

Slide 22

Sources of Oscillator Phase Noise

C N

stored kT

Active Device
C N 1 Q PWR fkT

Pierce 56, Everhard 86)

Options for on-chip VCO: Compatible on-chip high-Q inductors Find a way to use ring oscillators (Q=1)

Slide 23

Typical Synthesizer Implementation

Crystal Reference fout = N x fcrystal M

Phase Detector

Loop Filter N

VCO

S ( f)

Narrow PLL BW Increasing PLL Bandwidth

f f0 f0 + fm
Slide 24

Phase-Noise-Optimized Synthesizer Design

Problem: Conict between narrow channel spacing and high comparison frequency Some Possible Solutions: Quasi-direct Conversion, xed rst LO Two-step synthesis using DDS or other means for 2nd step Noise-shaped fractional-N synthesis Ring oscillator VCO with noise-shaped multi-tap phase interpolation
Slide 25

Keys to Progress in Low-Power Adaptive RF Transceiver Design

New Receiver Architectures Low-Power CMOS/BiCMOS RF Circuit Design New Approaches for Low-Noise On-chip Synthesis RF-Compatible CMOS/BiCMOS Technologies Low-Power A/D and Digital for Baseband Processing Control of Chip, Package Parasitic RF Paths

Slide 26

Technology Speed Figure of Merit vs Time

ft
100GHz 30GHz
0.35u 0.5u 0.25u

Hemts,HBTs

10GHz
0.8u

0.6u

3GHz 1GHz

GaAs
1.5u 2u

1u

Bipolar

3u

MOS
75 77 79 81 83 85 87 89 91 93 95 97 99

Year
Slide 27

RF IC Technology and Design Considerations

CMOS, BiCMOS are the only alternatives for high integration Scaled NMOS devices are fast
Technology 0.35 micron 0.25 micron 0.18 micron ft 25GHz 40GHz 60 GHz(e) fmax 40GHz(e) 60-70GHz(e) 90-100GHz(e)

Inductors and Capacitors of reasonable Q are essential

Slide 28

Inductors in Silicon ICs

Aluminum Spirals Bond Wires

L=1-10nH Q=4-8@2Ghz fself~3-10Ghz

Slide 29

L=1-5nH Q=20-40@2Ghz

Alternatives for High-Q Resonators in Si ICs

Standard aluminum spirals of bond wires for inductance Etched cavities for improved self-resonance Plated-up thick metal for higher Q inductors Micromachined structures for variable capacitors Compatible on-chip accoustic resonators, etc.

Slide 30

Keys to Progress in Low-Power Adaptive RF Transceiver Design

New Receiver Architectures Low-Power CMOS/BiCMOS RF Circuit Design New Approaches for Low-Noise On-chip Synthesis RF-Compatible CMOS/BiCMOS Technologies Low-Power A/D and Digital for Baseband Processing Control of Chip, Package Parasitic RF Paths

Slide 31

Example Low-Power Baseband ADC

10-bit 20MS/s 35mW Pipeline Tech: 1.2m CMOS Vdd: 3.3V

Active Area: 3.2 x 3.3 mm2 Power: 35mW @ 20MS/s 15mW @ 10MS/s 2.8mW @ 1MS/s
*:T. Cho @CICC 94, San Diego
Slide 32

Keys to Progress in Low-Power Adaptive RF Transceiver Design

New Receiver Architectures Low-Power CMOS/BiCMOS RF Circuit Design New Approaches for Low-Noise On-chip Synthesis RF-Compatible CMOS/BiCMOS Technologies Low-Power A/D and Digital for Baseband Processing Control of Chip, Package Parasitic RF Paths

Slide 33

Future Directions in Silicon ICs for RF Personal Communications

RF Transceivers in PCS Systems Typical Current Implementations New Approaches for Low-Power RF Transceivers Examples and Current Status

Slide 34

1.6GHz Integrated GPS Reciever IC

Triple-Conversion Superheterodyne Receiver 1.4GHz on-chip L-C VCO, Synthesizer Off-Chip RF, IF Filters Off-Chip LNA High-Speed Bipolar Technology

Plessey GP1010/2010

Slide 35

Slide 36

900MHz CMOS Wireless LAN Transceiver

A. Abidi, et al, UCLA

Frequency-Hopped 900Mhz Spread-Spectrum LAN 2-160kbps Data Rate Direct Conversion Receiver w/subsampling mixer Fixed VCO+DDS offset frequency Tuned LNA, Pwr Amp using Etched-cavity Inductors 30mW Variable Transmit Power Amplier

Slide 37

CMOS 900Mhz CMOS Transmitter IC

A. Abidi, et al UCLA

Dual Up-conversion Mixers Tuned Preamplier 30mW Balanced Variable-power Amplier 1 Micron CMOS, Etched-Cavity Inductors
Slide 38

Infopad CDMA Downlink Receiver

S. Sheng, Bob Broderson, et al- UCB

Wireless LAN, 50 users, 2 Mbps each Direct-Sequence CDMA, 64 spread 900Mhz Carrier Frequency Direct conversion, sampling mixers Scaled from IS-95B CDMA standard 1 Micron CMOS Implementation

Slide 39

CDMA Downlink Receiver

Analog Front End
XCORR SCANCORR

Correlator Block

MPCORR MPCORR MPCORR

1 GHz front end LNA Dual I/Q receive paths Sampling mixers 4 bit, 128 MHz dual ADCs 47dB linear+step AGC 130 mW Power Diss.

Timing recovery Adjacent channel scan Multipath estimation RAKE reception Data Recovery 27 mW Power Diss.

Slide 40

DECT/Multistandard CMOS Adaptive Transceiver Project

T. Cho, et al, UCB

1.8Ghz RF Receive Path Integration of RF, Synthesizer, and Baseband ADC Shaped-Phase-Noise Ring-oscillator-based Synthesizer Approach Quasi-Direct Conversion Architecture 0.6 Micron Implementation

Slide 41

Plot of DECT Reciever die goes here

Slide 42

Key Problems for Silicon RF ICs

Development of CAD tools for package modeling, inductor design, substrate modeling, etc. Exploitation of scaled CMOS and BiCMOS technologies for low-power, high-integration transceiver functions Continued Development of Process Enhancements for on-board high-Q Inductors/resonators/ lters Exploitation of bands above 2.5Ghz using SiGe or hybrid Si-III-IV approaches
Slide 43

Ultimate Objective:

Slide 44

Technology Speed Figure of Merit vs Time

ft
100GHz 30GHz
0.35u 0.5u 0.25u

Hemts,HBTs

10GHz
0.8u

0.6u

3GHz 1GHz

GaAs
1.5u 2u

1u

Bipolar

3u

MOS
75 77 79 81 83 85 87 89 91 93 95 97 99

Year
Slide 45

Local Oscillators in Radio Receivers

RF Filter

RF Amp

Analog Baseband Circuitry

DSP

Divider VCO Xtal Osc L-C

Typical Requirements:

Synthesizer block

1.8Ghz +/- 10Mhz Frequency-Agile <50mW Average Power Dissipation 30kHz-1Mhz channel spacing Phase Noise: -95 to -120 dBc/Hz at adjacent channel
Slide 46

Block Diagram, High-Integration RF Transceiver

Mixer LNA RF Filt I Mixer Q I Mixer Q 10b,10MS/s Baseband ADC ltering Baseband 10b,10MS/s ltering ADC AGC DCoffset control Carrier tracking Symbol timing recovery Frame recovery Symbol decode Sequence correl. Equalization AGC control DC Offset control Transmit pulse shaping Transmitter burst control Channel select Hopping control Power adaptation

Dout Clkout Sync out

Power Amplier

Modulator

Filters Filters

DAC DAC Adaptive Baseband Processor

Din Clkin

Control

VCO1 RF PLL Xtal Osc.

VCO2 IF Channel Select PLL Synthesizer

Slide 47