Inductor On Chips

ON-CHIP SPIRAL INDUCTORS FOR SILICON-BASED RADIO-FREQUENCY INTEGRATED CIRCUITS
A DISSERTATION SUBMITTED TO THE DEPARTMENT OF ELECTRICAL ENGINEERING AND THE COMMITTEE ON GRADUATE STUDIES OF STANFORD UNIVERSITY IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF DOCTOR OF PHILOSOPHY
Chik Patrick Yue July 1998
Copyright by Chik Patrick Yue 1998 All Rights Reserved
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Abstract
Recently, there has been tremendous interest in silicon-based integrated circuits for radio-frequency (RF) applications. This trend can be attributed to the enormous potential of the wireless communication market, the low-level integration of current transceiver implementations, and the rapid advancements in silicon processing technologies. RF designs require a large number of passive components realized today mostly in discrete form. To attain a high level of integration, circuit blocks and passive elements need to be fabricated on the same substrate using a single technology. Silicon technology has progressed to offer device performance suitable for analog operations at GHz frequencies and consequently has become the cost-effective choice for RF front-end circuits. Nevertheless, silicon-based RF designs face some unique challenges that must be resolved before the monolithic transceiver can be realized. In particular, the quality factor (Q) of on-chip inductors and noise coupling through the substrate are among the most pressing issues to overcome. Since typical spiral inductors span a few hundred microns on each side, substrate noise coupling associated with these elements can be signicant. Although numerous results of on-chip inductors have been reported, the basic understanding of performance limitations and the procedures for optimizing the quality factor are lacking. Most published inductor models rely on numerical techniques which are not
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intuitive enough to provide the insight needed in a design process. This dissertation presents a physical model that addresses the phenomena and parasitics important to the behavior of on-chip inductors. This scalable model has been conrmed with measured and published data of inductors having different geometric and process parameters. Based on this compact model, an efcient design methodology for inductors on silicon is discussed. With the insight gained from the physical model, this dissertation presents a patterned ground shield inserted between an on-chip spiral inductor and the substrate to suppress silicon parasitic effects. The patterned ground shield can be realized in standard silicon technologies without additional processing steps. The impacts of shield resistance and pattern on inductance, parasitic resistances and capacitances, and quality factor are studied extensively. Experimental results show that a polysilicon patterned ground shield achieves the most improvement. The addition of the shield can increase the inductor quality factor and reduce the substrate coupling between two adjacent inductors. We also show that the quality factor of a LC tank can be nearly doubled with a shielded inductor. The amount of improvement can be further increased by the optimization techniques based on the physical inductor model.
Table of Contents
Abstract .............................................................................................................................. iv List of Tables .......................................................................................................................x List of Figures ................................................................................................................... xii Chapter 1 Introduction 1 1.1 Worldwide Wireless Communication Market.......................................................1 1.2 System on a Chip ..................................................................................................3 1.3 The Role of Inductors in RF Designs ...................................................................4 1.4 The Advantages of Integration..............................................................................6 1.5 Dissertation Organization .....................................................................................9 Chapter 2 On-Chip Inductors 11 2.1 Active Inductors..................................................................................................11 2.2 Bond Wire Inductors...........................................................................................14 2.3 Spiral Inductors...................................................................................................17 Chapter 3 Modeling and Characterization 25 3.1 Inductance and Parasitics of a Spiral Inductor....................................................26 3.1.1 Series Inductance ....................................................................................27 3.1.1.1 Self Inductance.........................................................................28 3.1.1.2 Mutual Inductance ...................................................................30
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3.2 3.3 3.4
3.5 3.6 3.7
3.1.1.3 Spiral Inductance .....................................................................31 3.1.2 Series Resistance.....................................................................................36 3.1.2.1 Proximity Effect on Resistance................................................38 3.1.2.2 Skin Effect on Resistance ........................................................40 3.1.3 Feed-through Capacitance ......................................................................44 3.1.4 Substrate Parasitics .................................................................................46 A Physical Model................................................................................................48 Testing and Parameter Extraction .......................................................................48 Measured and Modeled Results ..........................................................................54 3.4.1 Individual Elements in the Physical Model ............................................54 3.4.2 Two-Port S Parameters............................................................................56 Impact of Technology on Inductor Performance ................................................57 Design Methodology...........................................................................................66 Summary .............................................................................................................68
Chapter 4 Patterned Ground Shields 69 4.1 Design Considerations ........................................................................................70 4.1.1 Denitions of Quality Factor ..................................................................70 4.1.2 Understanding of Substrate Effects.........................................................72 4.1.3 Drawback of Solid Ground Shields ........................................................75 4.1.4 Design of Patterned Ground Shields.......................................................78 4.2 Experimental .......................................................................................................80 4.2.1 Experiment Design..................................................................................80 4.2.2 Effects on Inductance and Parasitics.......................................................82 4.2.3 Improvement in Inductor Q.....................................................................89 4.2.4 Improvement in Q of a LC-Tank.............................................................91 4.2.5 Suppression of Substrate Noise Coupling...............................................92 4.3 Summary .............................................................................................................93 Chapter 5 Effects of Epitaxial and Lightly Doped Substrates 95 5.1 Theory and Simulation........................................................................................96 5.2 Experimental Results ........................................................................................101 5.2.1 Bond Pads .............................................................................................101 5.2.2 Spiral Inductors.....................................................................................104 5.3 Summary ...........................................................................................................111
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Chapter 6 Conclusions 113 6.1 Summary ...........................................................................................................113 6.2 Future Work ......................................................................................................114 6.2.1 Improvement in Q .................................................................................114 6.2.2 On-Chip Transformers and Baluns .......................................................115 6.2.3 On-Chip Tunable Bandpass Filters .......................................................115 Bibliography 117
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List of Tables
Table 1.1: Table 3.1:
Table 4.1: Table 5.1: Table 5.2:
RF front-end component count..................................................................7 Properties of spiral inductance. For all cases, the inner dimension is xed at 100 m, line width at 12 m, line spacing at 2 m, and metal thickness at 1 m.....................................................................................................34 Comparison of measured inductor parameters for the NGS (11 -cm) and polysilicon PGS cases at 2 GHz..............................................................88 Summary of 100 100 m2 bond pads...................................................99 Summary of spiral inductors..................................................................103
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List of Figures
Figure 1.1:
Figure 1.2: Figure 1.3: Figure 1.4:
Figure 2.1: Figure 2.2: Figure 2.3: Figure 2.4:
Worldwide cellular population (a) in 1996, and (b) the forecast for 2000. (Data source: the Cellular Telecommunications Industry Association.) ..........................................................................................2 Typical impedance matching networks. (a) L-match. (b) -match........4 Comparison of frequency response of a simple amplier with and without tuned load..................................................................................5 The printed circuit board inside a digital cellular phone for the European DCS-1800 and the component count for the RF front-end circuit. (Bosch 1997.).............................................................................7 Gyrator-based active inductors in (a) single-ended and (b) oating congurations.......................................................................................12 A gyrator-based inductor for illustrating the noise properties of active inductors. The resistor and MOSFET constitute the gyrator. ..............14 Die photo of the VCO presented by J. Craninckx et al., which used four bond wires to implement two inductors...............................................15 Limitation of IC interconnects for implementation of 3D coils: (a) vertical coils are limited by the number of available metal layers (b) horizontal coils achieve little mutual coupling due to short via length in the vertical direction. ...........................................................................18 Cross section of multi-level interconnects in a typical IC. ..................19 Layout of a 3-turn square spiral inductor.............................................20 Cross-sectional view of the spiral and the center-tap underpass. ........21
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Figure 2.8: Figure 3.1: Figure 3.2: Figure 3.3: Figure 3.4: Figure 3.5: Figure 3.6: Figure 3.7: Figure 3.8: Figure 3.9: Figure 3.10: Figure 3.11: Figure 3.12: Figure 3.13:
Figure 3.14:
Scanning electron micrographs of a 7-turn square spiral inductor. .....22 Cut-away view of a conventional spiral inductor on silicon substrate with the inductance and RC parasitics highlighted. .............................24 The dependency of self inductance on the wire cross-section dimension for different wire lengths......................................................................26 The dependency of self inductance on the wire length for different cross-section dimensions. ....................................................................27 Two parallel wires with the same dimensions for studying mutual coupling................................................................................................29 The mutual inductance and coupling coefcient between two wires as a function of line-to-line spacing............................................................30 The mutual inductance and coupling coefcient between two wires as a function of line pitch............................................................................31 Positive and negative mutual couplings in a 4-turn spiral inductor. ....32 Proximity effect on series resistance for (a) side-by-side and (b) stacked wires.....................................................................................................36 Eddy current effect in the conductors of a (a) coaxial and (b) microstrip transmission line. .................................................................................39 Effective thickness (teff) of a conductor with nite thickness (t) under skin effect.............................................................................................40 Effective thickness of (a) aluminum and (b) copper as a function of frequency..............................................................................................41 A three-turn inductor: (a) layout and relevant elements (b) distributed model and (c) lumped model. ..............................................................43 (a) Real and (b) imaginary parts of the input impedance of the inductor model circuits in Figure 3.12 for studying the importance of crosstalk and overlap capacitance to the overall feed-through capacitance........45 (a) Lumped physical model of a spiral inductor on silicon. (b) Equivalent model with combined impedance of Cox, CSi, and CSi substituted by Rp and Cp. .....................................................................47 S parameters measurement set-up and a sample test structure consisted of an open and a device under test (DUT). ..........................................48 Equivalent circuit of the measurement set-up......................................49 Parameter extraction procedure for the lumped elements in the inductor model shown in Figure 3.14(b). ...........................................................51 Measured and modeled values of (a) Ls and Rs, (b) Cp and Rp for two inductors with different spiral metal materials: one with copper and the other with aluminum. ...........................................................................53
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Figure 3.19: Figure 3.20: Figure 3.21: Figure 3.22: Figure 3.23: Figure 3.24: Figure 3.25: Figure 3.26: Figure 3.27: Figure 3.28:
Measured and modeled values of S11 and S21 plotted on a Smith chart. . 55 Measured and modeled values of (a) real and (b) imaginary parts of S11 and S22..................................................................................................56 Measured and modeled values of (a) real and (b) imaginary parts of S12 and S21..................................................................................................57 Measured and modeled values of (a) Q and (b) degradation factors for two inductors with 1-m spirals in copper and aluminum. .................59 Effect of metal scheme on Q................................................................60 Effect of oxide thickness on Q.............................................................61 Effect of substrate resistivity on Q.......................................................62 Effect of layout area on Q. ...................................................................62 Verication of the physical model using published data. ....................63 Contour plots of Q as a function of inductance and outer dimension of square spiral inductors at (a) 0.6 GHz, (b) 1.0 GHz, (c) 1.6 GHz, and (d) 3.0 GHz. .........................................................................................65 Lumped physical model of a spiral inductor on silicon.......................71 Equivalent model with the combined impedance of Cox, CSi, and RSi in Figure 4.1 substituted by Rp and Cp.....................................................72 (a) Perspective view of a spiral inductor on solid ground shield and the resulting electromagnetic eld lines. The elds are substantially attenuated by the shield. (b) Perspective view of a solid ground shield showing the induced loop current and its associated magnetic eld lines. .....................................................................................................75 Circuit model for illustrating the effects of negative mutual coupling between a spiral inductor and a solid ground shield. ...........................76 Close-up photo of the patterned ground shield. ...................................77 Die photos of ground-signal-ground (GSG) test structure and the inductors: (a) spiral inductor with no ground shield (NGS), (b) solid ground shield (SGS) shown without and with spiral, (c) patterned ground shield shown without and with spiral. .....................................79 Two-port test structure for measuring crosstalk via substrate between two adjacent inductors (shown with un-shielded inductors)................80 Effect of aluminum ground shields on: (a) spiral inductance (Ls), (b) series resistance (Rs). ...........................................................................82 Effect of aluminum ground shields on: (a) parasitic capacitance (Cp), and (b) parasitic resistance (Rp). ..........................................................83 Effect of polysilicon ground shields on: (a) spiral inductance (Ls), (b)
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Figure 4.11: Figure 4.12: Figure 4.13: Figure 4.14: Figure 5.1: Figure 5.2: Figure 5.3: Figure 5.4: Figure 5.5: Figure 5.6: Figure 5.7: Figure 5.8: Figure 5.9: Figure 5.10: Figure 5.11: Figure 5.12:
series resistance (Rs). ...........................................................................85 Effect of polysilicon ground shields on: (a) parasitic capacitance (Cp), and (b) parasitic resistance (Rp). ..........................................................86 Effect of (a) aluminum and (b) polysilicon ground shields on Q. .......87 Effect of polysilicon patterned ground shield on Q of a 2-GHz LC tank. 89 Effect of polysilicon patterned ground shield on substrate coupling between two adjacent inductors. ..........................................................90 (a) A parallel-plate capacitor with SiO2 and Si as dielectric slabs. (b) A equivalent circuit model for the SiO2-Si system..................................95 Simulation results of (a) Cp and (b) Rp for a MOS structure with 16-m wide metal on 1 m thick oxide and 500 m thick silicon..................98 Frequency response of (a) Cpad and (b) Rpad for metal pads on various substrates (see Table 5.1). ..................................................................101 Frequency response of Q for the metal pads......................................102 Measured results of (a) series inductance and (b) series resistance for the inductors listed in Table 5.2. ........................................................104 Frequency response of Q for the inductors. .......................................105 Comparison of substrate parasitic capacitance for inductors on epi and lightly doped substrate. ......................................................................106 Ls/Rs for Epi5nH and Ld8nH. .........................................................106 Substrate loss and self-resonance factors for Epi5nH and Ld8nH. ...107 Frequency response of Q for Epi5nH with and without PGS. Diffusion and polysilicon PGS are considered. .................................................108 Resonator Q of Epi5nH with and without PGS. Diffusion and polysilicon PGS are considered. ........................................................109 Substrate parasitic capacitance of Epi5nH with and without PGS. Diffusion and polysilicon PGS are considered. .................................110
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Chapter
Introduction
The interest in on-chip inductors has surged with recent growing demand for silicon-based radio-frequency (RF) integrated circuits. This chapter presents the impetus behind the integration of inductors from both economic and technological viewpoints. First of all, a survey of the current status and future trends of the worldwide wireless communication market is reported. The impacts on the IC industry are addressed. The critical role of inductors in RF circuits and systems is illustrated by examples. The advantages of on-chip inductors towards system on a chip for RF designs is elucidated. The last section outlines the organization of this dissertation.
1.1 Worldwide Wireless Communication Market

The cellular telephone industry has enjoyed phenomenal growth since its inception in 1983. According to the Cellular Telecommunications Industry Association (CTIA), in 1996 there were 87 million cellular subscribers worldwide: 38 million in North America, 25 million in Europe, 19 million in Asia Pacic, and 5 million in the rest of the world (See Figure 1.1). In 1997, the cellular populations in North America and Europe have already grown to 48 and 50 million, respectively. In Asia Pacific, Japan alone has now more than 31 million subscribers, reported recently by Japans Ministry of Posts and Telecommunications (MPT). Among the most well established markets, Japan has the highest population penetration at 24% followed by North America and Europe at 18% and 13%, respectively. Nevertheless, the percentage of population using wireless communication is still less than 5% worldwide. CTIA forecasts that by year 2000 the global cellular subscribers will increase to 300 million: 125 million in North America, 75 million in Europe,
Chapter 1: Introduction
80 million in Asia Pacific, and 20 million in the rest of the world. This translates to an astonishing annual growth rate of nearly 40% in the next several years. One of the driving forces behind this aggressive growth is the allocation of new radio spectra for wireless communication. The Broadband Personal Communications Services (PCS) which operates from 1850 to 1910 MHz (downlink) and from 1930 to 1990 MHz (uplink) is currently the fastest growing cellular service in North America. In April 1997, the Federal Communications Commission (FCC) licensed the band between 2305 to 2320 MHz and 2345 to 2360 MHz for Wireless Communication Services (WCS) which are expected to be in service in three years. The FCC auctioned another 25-MHz band from 4660 to 4685 MHz in May 1998 for General Wireless Communication Services (GWCS). In Europe, the Global System for Mobile Communications (GSM) is the entrenched standard with the original version working at 890 to 915 MHz (downlink) and at 935 to 960 MHz (uplink). The newer version known as the Digital Communication SysOther 5 Million 6% Other 20 Million 7%
Asia Pacic 19 Million 22% Europe 25 Million 29%
North America 38 Million 43%
Asia Pacic 80 Million 27%
North America 125 Million 41%
Europe 75 Million 25%
Year 1996 87 Million Subscribers (a)
Year 2000 300 Million Subscribers (b)
Figure 1.1: Worldwide cellular population (a) in 1996, and (b) the forecast for 2000. (Data source: the Cellular Telecommunications Industry Association.)
1.2. System on a Chip
tem (DCS-1800) uses the spectrum between 1710 to 1785 MHz (downlink) and 1805 to 1880 MHz (uplink). The Universal Mobile Telecommunication System (UMTS), the successor to the second-generation GSM, will be in service as early as 2001 at frequencies between 1885 to 2025 MHz and 2110 to 2200 MHz. Another reason for the surge of wireless communication is the constant reduction in service fees due to market competition. To enhance network capacity, new cellular standards emphasize the utilization of digital radio access technologies, such as code-division multiple access (CDMA) and time-division multiple access (TDMA). Using digital transmission, more users can be accommodated into the available bandwidth without degrading the voice quality. Consequently, cellular services become more affordable. This is especially important for developing countries such as China and India where populations are large and wired telephony infrastructure is lacking. Since wireless communication is the only option which avoids constructing more costly copper-based networks, low-cost service will expedite the adoption and spread of cellular telephony.
1.2 System on a Chip

The wireless trend continues to have a large impact on the IC industry. The U.S. sales of analog and mixed-signal ICs into the cellular-handset market soared from $654 million in 1993 to over $3.2 billion in 1996 according to Dataquest Inc., San Jose, CA. In addition to cellular and cordless phones, novel portable electronics continue to emerge ranging from handsets for wireless e-mail and Internet access to navigation systems based on the Global Positioning System. The success of these consumer products depends heavily on the cost, battery lifetime, functionality and weight. To meet these requirements, the chip manufacturers are pursuing the system-on-a-chip approach aiming to integrate a RF transceiver and baseband digital signal processing on a single piece of silicon. Among the various technical challenges, the integration of passive components, especially inductors, has received a great deal of attention due to their vital roles in RF front-end systems [1][2].
1.3 The Role of Inductors in RF Designs

The operating frequency of most cellular services ranges from 0.8 to 2.5 GHz. At such high frequencies, impedance matching networks are required between the circuit blocks in a RF system to ensure maximum power transfer. The primary function of these matching networks is to match the output impedance of a circuit block to the input impedance of the following block. Maximum power transfer is attained when the reactive parts of the impedances are a conjugate pair and the resistive parts are equal. Inductors are an integral part of impedance transformation circuits, such as the L-match and -match networks shown in Figure 1.2 . Design guidelines for such networks are described extensively in [3]. Inductors are often employed in the design of tuned ampliers, mixers, and oscillators. Low-noise ampliers and power ampliers with tuned loads are widely adopted to amplify the desired signals and to filter the out-of-band signals simultaneously. The main advantages of using tuned ampliers over broadband designs include relative ease of obtaining a specied gain at radio frequencies, high immunity to low-frequency noise, and low power consumption. In general, the difficulty of obtaining a certain gain-bandwidth product is approximately independent of the center frequency [3]. For instance, a constant gain of 10 up to 1 GHz implies a gain-bandwidth product of 10 GHz a task difficult to accomplish. On the other hand, if the desired signal has a bandwidth of 25 MHz (typical in L L
C1
C2
(a)
(b)
Figure 1.2: Typical impedance matching networks. (a) L-match. (b) -match.
1.3. The Role of Inductors in RF Designs
cellular standards), then a 1-GHz tuned amplifier with a gain-bandwidth product of only 250 MHz will be sufcient. To illustrate this idea, consider the effect of the inductor (L) on the frequency response of the amplier gain as shown in Figure . 1.3 Without L, the circuit reduces to a simple common source amplifier having a gain of gmR and a 3-dB bandwidth of 1/RC. The corresponding gain-bandwidth product is gm/C. With L, the circuit can be modeled as an ideal transconductor driving a parallel RLC tank. At low frequencies, the inductor acts as a short and the amplifier gain is small; whereas at high frequencies, the
Vout C Vin gm
Gain Without L BW = (RC) -1 With L BW = (RC) -1
fcenter= (LC) -1/2
Frequency
Figure 1.3: Comparison of frequency response of a simple amplier with and without tuned load.
capacitor behaves as a short and causes the gain to roll off. At the tank resonance frequency, namely (LC)0.5, the load is simply R and the gain is gmR for the effects of the inductor and the capacitor cancel each other. Since the bandwidth of the tank is 1/RC, the gain-bandwidth product remains as gm/C. This example demonstrates the essential function of inductors at radio frequencies for tuning capacitances. More detailed treatment of tuned ampliers can be found in [3]. In addition to tuned amplier loads [4][5], inductors are also used as emitter or source degeneration for improving linearity and matching [5][10] and as series and parallel LC resonators for RF lters [11][14] and oscillators [15][16].
1.4 The Advantages of Integration

Current transceivers typically consist of parts manufactured in several technologies: bipolar or BiCMOS for the low-noise amplier, mixer, and voltage-controlled oscillator; GaAs or bipolar for the power amplifier; and CMOS for the baseband signal processing [1][2]. The large number of required passive components are realized today mostly on the PCB using thick-film techniques or in discrete form (See Figure 1.4). To increase the level of integration, circuit blocks and passive elements need to be fabricated on the same substrate using a single technology. Silicon technology has progressed to offer device performance suitable for analog operations at a few gigahertz [17][21] and consequently emerges as the cost-effective choice for RF front-end circuits. Cost. In the front-end radio of a cellular phone, the majority of the components on the PCB are discrete passive elements. Although the component cost of discrete RLC elements constitutes a small fraction (about 10%) of the board cost, the associated assembly cost is substantial. In fact, the overall cost due to passive components often exceeds one third of the board cost. Consequently, integrating the passives on chip can reduce both component and assembly costs. More importantly, with the intermediate LC matching networks integrated, individual circuit blocks are more readily manufactured on the same
1.4. The Advantages of Integration
Table 1.1:
RF front-end component count. 11 >100 >50 5 12 1 2
Inductor Capacitor Resistor IC Transistor Crystal Filter
Figure 1.4: The printed circuit board inside a digital cellular phone for the European DCS-1800 and the component count for the RF front-end circuit. (Bosch 1997.)
silicon substrate. As a result, the cost of IC packaging and testing will drop drastically because fewer ICs are needed to implement a system. Power. Power savings is another important benet. When signals travel between components on the PCB, additional power is dissipated in driving large parasitic inductances and capacitances due to bond pads, bond wires, IC packages, PCB traces, and discrete packages. Size. Discrete passives occupy for most of the PCB area in todays systems. Increasing demand for miniature portable system has resulted in large reductions in the footprints of surface mount RLC elements. The state-of-the-art discrete resistors and capacitors are available in a 0402 package. The smallest surface mount inductors are limited to a 0603 package due to the volume required for wire winding [22]. However, because of the overhead area required for solder attachments and vias, the PCB area savings offered by these advanced packages is not significantly. Further miniaturization of component size will result in diminishing improvements in form factor. Integrating RLC elements on chip is a more effective solution. Reliability. Monolithic implementation will also improve system reliability by reducing transitions and interfaces arising from component soldering. Matching. Most wireless communication circuits operate between 0.8 to 2.5 GHz. At such high frequencies, typical inductances required range from 1 to 25 nH. The small inductance values are difficult to match with discrete implementation. For surface mount inductors, tolerance for component values is usually between 2% to 25% and is worse for smaller inductances (below 10 nH) due to package parasitics [22][24]. Monolithic implementation of the required inductance values is quite feasible. On-chip inductors offer superior matching and repeatability because of the tight control in IC processing. Design Flexibility. The integration of passive components allows more flexibility in impedance matching designs by keeping signals on chip and thus avoiding the need for matching to the off-chip 50- environment.
1.5. Dissertation Organization
Testing. Integration of more components will simplify and reduce IC testing and as a result lower cost. The advantages of integrating passive elements on chip are clear. In silicon technologies, resistors and capacitors are readily available since they have been used extensively in analog ICs which typically operate up to a few hundred megahertz. In contrast, on-chip inductors are rarely employed in those ICs. This is mainly because the required inductances are too large to be realized on chip in a reasonable area and with adequate performance. The advent of RF ICs demands inductors to be included in the IC family.
1.5 Dissertation Organization

This dissertation is devoted to the fabrication, modeling, characterization, and design of on-chip spiral inductors using conventional silicon IC technologies. Chapter 2 presents the reasons for the limited usefulness of gyrator-based and bond-wire on-chip inductors. The fabrication of spiral inductors using standard IC interconnect technologies is reviewed. The impacts of micro-machining techniques and advanced metallization materials are presented. The focus of Chapter 3 is on modeling, testing, and characterization of inductors with various process and layout parameters. A design methodology for optimal inductor layout is also described. Based on the physical insights gained, Chapter 4 presents the design of a patterned ground shield inserted between an inductor and the substrate to improve the overall performance. Chapter 5 discusses the effect of lightly doped and epitaxial substrates on inductors and demonstrates the effectiveness of a patterned ground shield for both substrates. Lastly, conclusions and future work are summarized in Chapter 6.
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Chapter
On-Chip Inductors
This chapter evaluates several common approaches for integrating inductors on chip. Integrated inductors can be categorized into active and passive implementations. Regardless of the circuit scheme, active inductors virtually all share the same drawbacks of excess noise, extra power dissipation, and limited dynamic range owing to the required active circuitries. Passive inductors can be realized using the available conductors on a chip which include regular interconnects and bond wires. The predictability and reproducibility of bond wire inductors are fairly poor and thus have limited their widespread adoption. Spiral inductors are the most feasible and widely used choice because of their compatibility with IC processing.
2.1 Active Inductors

Inductances can be emulated through the reciprocation of capacitances. A gyrator is a circuit that performs impedance reciprocation by creating an phase inversion to the original impedance. Since IC technologies offer good quality capacitors, inductances can be obtained by utilizing on-chip gyrators and capacitors [25][27]. Figure 2.1 shows the general form of gyrator-based inductors in single-ended and oating congurations. It can be shown that the emulated inductance in both congurations is C L eff = -------------------gm 1 gm 2 (2.1)
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Chapter 2: On-Chip Inductors
i1 -gm1 iin C L eff = -------------------gm 1 gm 2
+
vin
+
C vc gm2 i2 (a) i1 -gm1 iin
+
gm2 C L eff = -------------------gm 1 gm 2 vin i3 gm1 iin i2
+
C vc
-gm2 i4 (b) Figure 2.1: Gyrator-based active inductors in (a) single-ended and (b) oating congurations.
2.1. Active Inductors
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where the gm terms represent the transconductance of the gain blocks and C is the capacitance of a passive capacitor. The major drawback of active inductors is their excess noise. To understand the noise properties of active inductors, consider the simple gyrator-capacitor circuit shown in Figure 2.2 [3]. In this example, the idealized gyrator is comprised of a parasitic-free MOSFET and a resistor. Under the assumptions that 1/RC is much lower than the inductors operating frequency and that the quality factor, Q, of the inductor is much greater than unity at all frequencies of interest, one can derive the effective inductance and Q as RC L eff = ------gm and gm Q eff = -----------2 fC (2.3) (2.2)
where f is the frequency in Hz. (Q is a measure of the inductors efficiency for storing magnetic energy. A detailed treatment for the definition of Q is given in Chapter 4.) The effective current noise density due to the thermal noise of R is
2 2 4 kT - ( Q eff + 1 ) I R = --------R
(2.4)
which indicates that the thermal noise of the resistor (4kT/R) is amplified by a factor of (Qeff2+1). This effect is due to a voltage drop across the capacitor caused by the resistor noise current. This noise voltage is then amplified by the MOSFET transconductance. While a high Qeff is desirable for most circuit applications, it also leads to an unacceptably high noise level. This trade-off fundamentally limits the application of active inductors in RF designs. Besides the thermal noise of the resistor, additional noise sources due to the MOSFET also contribute to the overall noise of the active inductor. The usefulness of active induc-
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R gm C
2 4 kT - f i nR = --------R
Figure 2.2: A gyrator-based inductor for illustrating the noise properties of active inductors. The resistor and MOSFET constitute the gyrator.
tors is further hampered by the power dissipation and the dynamic range limitations of the active . circuitries
2.2 Bond Wire Inductors

Bond wires are used to make electrical connections between a chip and the IC package. Conventional bond wires are made of gold with a diameter of about 1 mil (25 m) and a typical length of 25 mm. It is known that in high-speed digital circuits when large transient current is drawn from the supply in a short time, the inductance of bond wires may cause detrimental power supply uctuations as described by d V supply = L I transcient . dt (2.5)
Using bond wires as inductors in RF circuits was rst proposed by J. Craninckx et al. in the design of a voltage-controlled oscillator [28][29] whose die photo is shown in Figure 2.3 .F our wires were bonded across the chip to implement two inductors.
The dc inductance of a wire with circular cross section can be estimated using
2.2. Bond Wire Inductors
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Figure 2.3: Die photo of the VCO presented by J. Craninckx et al., which used four bond wires to implement two inductors.
2l L self = 2 l ln ---- 0.75 r
(2.6)
where Lself is the inductance in nH, l is the wire length in cm, and r is the radius in cm [30]. According to (2.6), the inductance of a typical bond wire is about 1 nH/mm. It should be pointed out (2.6) assumes that the wire is straight and hence does not account for any curvature of the bond wire. At high frequencies, the skin effect causes attenuation of the magnetic field in the wire. However, this has little effect on the overall inductance since most of the magnetic eld is external to the wire. On the other hand, the non-uniform current density in the wire due to the skin effect must be accounted for when computing the high-frequency resistance. The skin depth of a conductor is = -------- f (2.7)
where , , and f represent the resistivity in -m, permeability in H/m, and frequency in Hz, respectively [31]. For gold ( = 2.4 -cm), the skin depth at 1 GHz is 2.5 m which
16
is only one tenth of the bond wire diameter. Since the ac current ows near the bond wire surface, the effective cross-section area is roughly equal to the circumference of the bond wire times the depth of penetration (). Thus, the ac resistance of a bond wire can be approximated by l f l R ac = ----------- = ----- ---------. 2r 2r 172 m/mm at 2 GHz. The Q of bond wire inductors can be estimated by substituting (2.6) and (2.8) into 2 f L self Q = ---------------------- . R ac (2.9) (2.8)
For gold bond wires, the ac resistance is 122 m /mm at 1 GHz and increases to
Assuming an inductance of 1 nH/mm, (2.9) yields a Q of approximately 50 at 1 GHz which increases to 70 at 2 GHz. Although bond wire inductors offer high Q, they have many disadvantages. As can be seen in Figure 2.3, the achievable inductance is limited by the chip dimensions. For example, to obtain 10 nH on a 4-mm-by-4-mm chip, several bond wires connected in series are required. The routing of bond wire inductors is cumbersome. Since the bond wire has to stretch over a long distance, the two ports of the inductor are remotely spaced across the chip. To overcome the routing difficulty, each inductor requires a pair of bond wires connected at one end of the chip. However, the mutual coupling between the two wires must be considered in the designs. The mutual inductance, M, in nH between two bond wires with the same length, l, and separation, d, both in cm can be computed using [30]
2 2 l l d d M = 2 l ln -- + 1 + ----- 1 + ----- + -- . 2 2 l d d l
(2.10)
For instance, two 5-mm bond wires with 1-mm separation have a mutual inductance of 1.5 nH, which is about 30% mutual coupling. The mutual inductance is positive if the cur-
2.3. Spiral Inductors
17
rents in the wires flow in the same direction and negative otherwise. The mutual inductance decreases slowly as d increases as can be inferred from the logarithmic dependency. Since multiple inductors are needed on the same chip, the large mutual coupling can cause unwanted interactions and lead to deleterious effects on the circuits. Another issue is related to the pads where the wires are bonded. The bond pads are typically 100-m-by-100-m, and therefore introduce considerable parasitic capacitance and resistance due to the underlying oxide layer and silicon substrate. This is especially problematic when several bond wires are connected in series to implement a single inductor. The controllability and consistency of bond wire inductance also pose problems. Due to the positioning uncertainties of the bonding process, a conservative estimation of the inductance tolerance is about 6% [29]. Variation in wire size, length, spacing, and curvature are responsible for the high tolerance.
2.3 Spiral Inductors

Discrete inductors are usually solenoid coils because of the large mutual coupling between turns and the ease of inserting high-permeability () material inside the coil to increase the inductance and Q. In conventional silicon IC technologies, however, three-dimensional coils are hard to realize. The difculty stems from the limited number of metal layers and the short via lengths in the vertical direction as shown in Figure 2.4 . For vertical coils, the close proximity of the turns in different layers induces significant eddy currents in each other and increases the overall ohmic loss (see Section 3.1.2). Furthermore, the inter-layer metal-to-metal overlap capacitance is large and lowers the maximum usable frequency substantially. The importance of the overlap capacitance is explained in Section 3.1.3. Due to the short via length, the net positive mutual inductance for horizontal coils is almost zero. Also, the resistance of via stacks is typically quite large and thus raises the resistive
18
Via Via
Metal Metal Metal
(a)
Metal
Via
Via
Via
Via Metal
(b) Figure 2.4: Limitation of IC interconnects for implementation of 3D coils: (a) vertical coils are limited by the number of available metal layers (b) horizontal coils achieve little mutual coupling due to short via length in the vertical direction. loss to intolerable level. For both vertical and horizontal coils, the substrate loss becomes more severe as the separation to the lossy silicon substrate is reduced. Planar inductors are more compatible with the IC interconnect scheme. Today, ICs typically have 35 levels of interconnects (see Figure 2.5). The top layer metal is usually
19
Figure 2.5: Cross section of multi-level interconnects in a typical IC. the thickest at 12.5 m while the lower layers are typically 0.71.0 m thick. The separation between the top layer metal and the silicon substrate is determined by the overall dielectric thickness which is typically 47 m. Several planar inductor structures are possible including loop, meander, and spiral [32]. Spirals are preferred because of their large positive mutual inductance. One can picture a planar spiral as a special form of solenoid with turns of descending diameter on the same plane. The layout of a 3-turn square inductor is shown in Figure 2.6. The current flow directions are indicated on the layout. Note that the interconnect segments with the same current direction are close to each other while those with opposite currents are separated far apart. This arrangement ensures the net mutual inductance is positive and therefore enhances the overall inductance.
20
N=3
AA
id od id
od Figure 2.6: Layout of a 3-turn square spiral inductor.
It has been reported that the series resistance of circular and octagonal spirals is approximately 10% less than that of a square spiral with the same inductance [33]. Nevertheless, square spiral remains the common choice in IC designs because non-Manhantton geometries are not supported by many layout tools. If necessary, the diagonal segments of an octagonal line can be drawn as Manhattan stair-step jogs. However, it may require a ne step size to assure smooth edges.
21
For square spirals, the layout parameters are the number of turns (N), line width (w), line spacing (s), and outer dimension (od). One can also specify the layout using the inner dimension (id) instead of the outer dimension. For an inductance of 120 nH, the typical N is 210 turns. Higher inductance values require more turns to achieve more mutual coupling. The line width usually ranges from 530 m. In general, large inductance values are realized with narrower line widths to avoid excessive parasitic capacitance. Smaller inductance values can tolerate more parasitic capacitance and therefore usually employ wider lines. The line spacing is generally kept to the minimum allowed by the technology, usually 15 m, to reduce the spiral series resistance. The outer dimension varies from 100500 m depending on the inductance and the available chip area. The cross section of the 3-turn inductor along AA is shown in Figure 2.7. The spiral is patterned in the top layer to take advantage of the low series resistance and to stay away from the lossy silicon substrate. The contact to the center of the spiral is realized with an underpass in a lower level interconnect. The entire inductor structure is separated from the silicon substrate by oxide. Figure 2.8 shows the scanning electron micrographs of a square spiral inductor with N = 7, w = 13 m, s = 7 m, and od = 300 m.
22
AA t toxM1-M2 tox Oxide
Silicon
Figure 2.7: Cross-sectional view of the spiral and the center-tap underpass.
23
Figure 2.8: Scanning electron micrographs of a 7-turn square spiral inductor.
24
Chapter
Modeling and Characterization
The lack of an accurate equivalent circuit model for on-chip inductors presents one of the most difficult problems for RF designers. In conventional IC technologies, inductors are not considered standard components like transistors, resistors, or capacitors whose models are included in the technology library. However, this situation is changing as the demand for RF ICs continues to grow [34][40]. Various approaches for inductor modeling have been reported [41][47]. Most of these models, however, are not scalable with layout dimensions and process parameters. The modeling difficulties stem from the complexity of the physical phenomena such as the skin effect and substrate loss. This chapter presents an analytical model which accounts for these physical effects. Each element of the model must be consistent with the physical phenomena occurring in the part of the inductor structure it represents. The behavior of spiral inductors with different structural parameters can therefore be predicted over a broad range of frequencies. Furthermore, the model is sufciently compact for circuit simulation and layout optimization. In this chapter, an analysis of a spiral inductor is carried out by treating separately the spiral inductance and other parasitics [48]. To conrm the validity of the analytical model, test structures for various inductors are fabricated and measured. Test structure design and the techniques for extracting the parasitics are described. The impact of layout and process parameters on the inductor quality factor, Q, are studied and compared to the model prediction. Lastly, Q contour plots are presented as a design tool for optimization of inductor layout.
25
26
Chapter 3: Modeling and Characterization
3.1 Inductance and Parasitics of a Spiral Inductor

The key to accurate physical modeling is the ability to identify the relevant parasitics and their effects. Since an inductor is intended for storing magnetic energy only, the inevitable resistance (R) and capacitance (C) in a real inductor are counter-productive and thus are considered parasitics. The parasitic resistances dissipate energy through ohmic loss while the parasitic capacitances store electric energy. In general, the RC parasitics hamper the quality of the inductor. A cut-away view of a spiral inductor on silicon is depicted in Figure 3.1. to highlight the parasitics existing in the structure. The inductance and resistance of the spiral and the underpass is represented by the series inductance, Ls, and the series resistance, Rs, respectively. The overlap between the spiral and the underpass allows direct capacitive coupling
Cs C Si C ox R Si Ls Rs
Figure 3.1: Cut-away view of a conventional spiral inductor on silicon substrate with the inductance and RC parasitics highlighted.
3.1. Inductance and Parasitics of a Spiral Inductor
27
between the two terminals of the inductor. This feed-through path is modeled by the series capacitance, Cs. The oxide capacitance between the spiral and the silicon substrate is modeled by Cox. The capacitance and resistance of the silicon substrate are modeled by CSi and RSi. The characteristics of each element are investigated extensively in the following sections.
3.1.1 Series Inductance

Inductance is the ratio of magnetic ux to current whereas capacitance is the ratio of electric charge to voltage. These relationships can be expressed as L = --I Q C = --V = H dS Q = E dS (3.1) (3.2) (3.3) (3.4)
where L, , I, C, Q, V, , , H, E, and dS are the inductance in henries (H), magnetic ux in webers (Wb), current in amperes (A), capacitance in farads (F), electric charge in coulombs (C), permeability in henries per meter (H/m), permittivity in farads per meter (F/m), magnetic eld density in amperes per meter (A/m), electric eld density in volts per meter (V/m), and area in meters squared (m2), respectively. Inductors store energy from the applied voltage in their magnetic field through flux just like capacitors store energy from the applied current in the electric eld through charge. The foundation for computing inductance of practical inductors is built on the concepts of the self inductance of a wire and the mutual inductance between a pair of wires. A comprehensive collection of formulas and tables for inductance calculation was summarized by F.W. Grover in [30]. Using Grovers formulas, the self and mutual inductance for IC interconnect lines are characterized in the following sections.
28
3.1.1.1 Self Inductance The dc self inductance of a wire with a rectangular cross-section area is expressed as follows: 2l w + t L self = 2 l ln ----------- + 0.5 + ---------- w+t 3l (3.5)
where Lself is the inductance in nH, l is the wire length in cm, w is the width in cm, and t is the thickness in cm. Using (3.5), the dependency of the self inductance on the cross-section dimension and length are plotted in Figure 3.2. and Figure 3.3. The cross-section dimension refers to the sum of width and thickness. As shown in Figure 3.1, the inductance decreases slowly with larger cross-section dimensions. For instance, the inductance of a 1-cm wire decreases by only a factor of two when the cross-section dimensions increases by two orders of magnitude from 1 m to 100 m. Since the inductance is pri-
100.00 l = 1 cm 10.00 l = 1 mm Lself (nH) 1.00 l = 100 m
0.10
0.01
l = 10 m
0.00
10 w + t (m)
100
1000
Figure 3.2: The dependency of self inductance on the wire cross-section dimension for different wire lengths.
29
100.00 w + t = 1 m w + t = 10 m w + t = 100 m w + t = 1 mm
10.00
Lself (nH)
1.00
0.10
0.01
0.00 10 100 l (m) Figure 3.3: The dependency of self inductance on the wire length for different cross-section dimensions. 1000 10000
marily determined by the magnetic flux external to the wire, the variation in the wire cross-section dimensions has little effect on the inductance. In general, the wires with smaller cross-section area have a slightly larger inductance because they generate more magnetic flux external to the wire. It should also be pointed out that (3.5) is not valid for wires having cross-section dimension approximately twice their length. For example, as indicated in Figure 3.2, with a cross-section dimension of 700 m, the inductance of a 10-m wire is larger than the 100-m case. It is physically impossible for a shorter wire to have larger inductance. Although wires with such geometries are hardly used in practice, they point out the limitation of (3.5). Figure 3.3 shows that the increase in inductance with length is slightly more than linear, which is due to the positive mutual coupling between parts of the wire. However, this transformer effect is insignicant as suggested by the logarithmic dependency on (w+t) in (3.5). For (w+t) equal to 10 m, a 250-m and 1000-m wire yield inductance per milli-
30
meter at 0.88 nH and 1.16 nH, respectively. Typical wire segments of an on-chip spiral inductor have widths of 530 m and lengths of 100400 m which result in self inductances of 0.71.1 nH/mm. 3.1.1.2 Mutual Inductance The mutual inductance between two parallel wires can be calculated using the following equations. In general, M = 2 lQ (3.6)
where M is the inductance in nH, l is the wire length in cm, and Q is the mutual inductance parameter, which can be calculated using GMD 2 GMD l 2 l - + ------------ 1 + -------------. Q = ln ------------- + 1 + ------------ l GMD l GMD
(3.7)
In (3.7), GMD is the geometric mean distance between the wires, which is approximately equal to the pitch of the wires. A more accurate expression for the GMD is given as w w w w w ln GMD = ln d ----------- ----------- -------------- -------------- ---------------- .... 2 4 6 8 10 12 d 60 d 168 d 360 d 660 d where w and d are the wire width and pitch in cm, respectively. Two parallel wires with the same dimensions are shown in Figure 3.4. The self and mutual inductance can be obtained using (3.5) through (3.8) and they are related as M = k L 1 L 2 = kL (3.9)
2 4 6 8 10
(3.8)
where L1 and L2 are the self inductance of the two wires and are both equal to L. k is the mutual coupling coefficient. Figure 3.5 shows the mutual inductance (M) and the corresponding coupling coefficient (k) as a function of the line-to-line spacing, s. The self inductance of the 1-m, 10-m, and 50-m (w+t) wires are 1.48 nH, 1.14 nH, and 0.84 nH respectively. All three wires are 1 m thick and 1 mm long. In general, the mutual inductance is larger for narrower wires. For small s, the difference in M is more pronounced
31
because the narrower wires have larger k and L. As s increases, k of the narrower wires decreases more rapidly and eventually drops below those of the wider cases. Nevertheless, the narrower wires have larger mutual inductances even with a larger spacing due to their higher self inductances. Figure 3.6 plots M and k with respect to the line pitch, d. Note that M does not vary with the width when the pitch is fixed. This indicates that for on-chip inductors with the same turn-to-turn pitch, variations in spiral width have little effect on the overall inductance. This also implies that the variation of inductance due to process fluctuation is extremely small. 3.1.1.3 Spiral Inductance Based on Grovers formulas, Greenhouse developed an algorithm for computing the inductance of planar rectangular spirals [49]. The Greenhouses method states that the overall inductance of a spiral can be computed by summing the self inductance of each wire segment and the positive and negative mutual inductance between all possible wire segment pairs. For instance, a four-turn rectangular spiral has sixteen segments and hence sixteen self inductance terms (see Figure 3.4 .). The mutual inductance between two wires s l
w t
Figure 3.4: Two parallel wires with the same dimensions for studying mutual coupling.
32
1.50 w = 1 m w = 10 m w = 50 m
1.20 M (nH)
0.90 s 0.60
0.30 0.0 10.0 20.0 s (m) (a) 1.00 0.90 0.80 0.70 k 0.60 0.50 0.40 0.30 0.0 10.0 20.0 s (m) (b) Figure 3.5: The mutual inductance and coupling coefcient between two wires as a function of line-to-line spacing. 30.0 40.0 50.0 w = 1 m w = 10 m w = 50 m 30.0 40.0 50.0
33
2.0 w = 1 m w = 10 m w = 50 m
1.0
M (nH)
d 0.1 1 10 d (m) (a) 1.0 100 1000
w = 1 m w = 10 m w = 50 m 0.1
10 d (m) (b)
100
1000
Figure 3.6: The mutual inductance and coupling coefcient between two wires as a function of line pitch.
34
depends on their angle of intersection, length, and separation. Two wires orthogonal to each other have no mutual coupling since their magnetic flux are not linked together. The current flow directions in the wires determine the sign of coupling. The coupling is positive if the currents in the two wires are in same direction and negative for opposite currents. A rectangular spiral has four groups of positive mutual inductance, one for each side of the spiral, and two groups of negative mutual inductance for two opposite sides. For instance, in a four-turn inductor, each positive mutual group consists of four segments and results in six mutual inductance terms whereas each negative mutual group consists of eight segments and results in sixteen mutual terms. Therefore, the overall inductance of a four-turn inductor is the sum of sixteen self inductance terms, twenty-four positive mutual
Positive Mutual Coupling
Negative Mutual Coupling
Current
Figure 3.7: Positive and negative mutual couplings in a 4-turn spiral inductor.
35
inductance terms, and thirty-two negative mutual inductance terms. In general, each rectangular spiral has number of self inductnace terms = 4 N , number of positive mutual inductnace terms = 2 N ( N 1 ) , and number of negative mutual inductnace terms = 2 N 2 , where N is the number of turns. To understand the characteristics of spiral inductance, L as a function of N is listed in Table 3.1. N is varied from 110. For all cases, the inner dimension is fixed at 100 m, line width at 12 m, line spacing at 2 m, and metal thickness at 1 m, which are typical values in RF designs. The spiral L is computed with the Greenhouse algorithm which calculates all the self and mutual inductances using (3.5)(3.8) and then sums them together. L is proportional to Nm where m is approximately 2 because of the positive mutual inductance. It should be pointed out that the power m is a function of N, line pitch and the ratio of outer to inner dimension. In general, m increases with N but decreases with larger line pitch. Spirals with a small outer-to-inner-dimension ratio have a higher power m. In a typical spiral layout, the value of m lies between 1.7 and 2.5. The third column of Table 3.1 contains the spiral length which is simply the sum of all individual segments lengths. For comparison, the self inductance of a straight wire with length equal to the spiral length is calculated using (3.5) and is listed in the last column. The width and thickness of the straight wire are 12 m and 1 m, respectively, the same as the spiral. Notice that for N less than 3, the wire L is actually higher than the spiral L. This is mainly because the negative mutual inductance outweighs the positive one. To reduce the negative mutual coupling, the inner dimension can be increased. Another reason is that the self inductance increases with length more than linearly as indicated in (3.5). Although the total length of the spiral segments is the same as the length of the straight wire, the spiral actually has less self inductance than the straight wire. To illustrate this point, consider a 1-mm long wire and four 0.25-mm long wires. According to (3.5), the 1-mm wire has an (3.12) (3.10) (3.11)
36
inductance of 0.97 nH whereas the 0.25 mm wires each has 0.17 nH. It follows that the Table 3.1: Properties of spiral inductance. For all cases, the inner dimension is xed at 100 m, line width at 12 m, line spacing at 2 m, and metal thickness at 1 m. Spiral L (nH) 0.27 0.94 2.03 3.60 5.71 8.41 11.77 15.84 20.68 26.36 Spiral Length (m) 448 1034 1720 2518 3428 4450 5584 6830 8188 9658 Wire L (nH) 0.42 1.15 2.09 3.25 4.64 6.26 8.10 10.19 12.51 15.07
N 1 2 3 4 5 6 7 8 9 10
total inductance of the four shorter wires is 0.69 nH which is less than 0.97 nH. For larger Ns, the positive mutual inductance dominates and spirals achieve much larger inductances per unit length compared to straight wires. Although many empirical formulas exist in the literature for estimation of spiral inductance [3][50][51], they are not able to accurately account for different geometries. However, the Greenhouse method has been verified with various experimental results [11][12][43]. For high accuracy, the series inductance in the physical inductor model is obtained using the Greenhouse method. Even though the Greenhouse method appears to be a tedious algorithm, it is actually fairly compact to implement in software.
3.1.2 Series Resistance

Resistance is a measure of the opposition offered by a conductor to the current ow under an applied voltage. Since the total current is equal to the current density times the area (for materials with uniform resistivity), the resistance can be expressed as
37
V V R ( f ) = ---------- = ----------------------------. I( f ) J ( f ) Area
(3.13)
The frequency dependence of R is due to the change in current density as frequency varies. The current density in a wire is uniform at dc; however, as frequency increases, the current density becomes non-uniform due to the formation of eddy currents. The eddy current effect occurs when a conductor is subjected to time-varying magnetic fields and is governed by Faradays law [52][53]. Eddy currents manifest themselves as skin and proximity effects. In accordance with Lenzs law, eddy currents produce their own magnetic elds to oppose the original eld. In the case of the skin effect, the time-varying magnetic eld due to the current ow in a conductor induces eddy currents in the conductor itself. The proximity effect takes place when a conductor is under the influence of a time-varying field produced by a nearby conductor carrying a time-varying current. In this case, eddy currents are induced whether or not the first conductor carries current. This is essentially a transformer action. If the first conductor does carry a time-varying current, then the skin-effect eddy current and the proximity-effect eddy current superimpose to form the total eddy current distribution. Regardless of the induction mechanism, eddy currents reduce the net current ow in the conductor and hence increase the ac resistance. The distribution of eddy currents depends on the geometry of the conductor and its orientation with respect to the impinging time-varying magnetic field. The most critical parameter pertaining to eddy current effects is the skin depth which is dened as = -------- f (3.14)
where , , and f represent the resistivity in -m, permeability in H/m, and frequency in Hz, respectively. The skin depth is also known as the depth of penetration since it describes the degree of penetration by the electric current and magnetic flux into the surface of a conductor at high frequencies. The severity of the eddy current effect is determined by the ratio of skin depth to the conductor thickness. The eddy current effect is negligible only if the depth of penetration is much greater than the conductor thickness. In general, eddy currents increase with frequency and thus further reduce the skin depth.
38
Since a spiral inductor is a multi-conductor structure, eddy currents can potentially be caused by both proximity and skin effects. The following sections will investigate the relative importance of each effect. 3.1.2.1 Proximity Effect on Resistance Due to the close proximity between the conductor segments in a spiral inductor, the current in each segment can induce eddy currents in other segments and cause the resistance to increase. It is difcult to analytically determine the signicance of the mutual eddy current and resistance caused by the proximity effect [52]. To investigate this problem, an electromagnetic eld solver based on the nite element method [54] is employed to study the effect of magnetic mutual coupling on resistance. Three side-by-side wires, as shown in Figure 3.8(a), are simulated. Each wire has a width and thickness of 20 m and 1 m, respectively. The spacing between lines is 2 m. During the simulation, an ideal ground plane with infinite conductivity is placed 500 m below the wires for carrying the return current. At 1 GHz, the inductance and resistance matrix are
Wire
(a)
Wire 3 2 1 (b) Figure 3.8: Proximity effect on series resistance for (a) side-by-side and (b) stacked wires.
39
L 11 L 12 L 13 1.24 0.95 0.81 L 21 L 22 L 23 = 0.95 1.23 0.95 H/m 0.81 0.95 1.24 L L L
31 32 33
(3.15)
and R 11 R 12 R 13 1961 15 0 R 21 R 22 R 23 = 15 2012 15 /m 0 15 1961 R R R

31 32 33
(3.16)
respectively. L11, L22, and L33 are the self inductance of each wire and the off-diagonal terms represent the mutual inductances. The mutual coupling, k, between adjacent wires is 0.76 while k between wire 1 and wire 3 is 0.65. R11, R22, and R33 are the self resistances of each wire and the off-diagonal terms represent the mutual resistances which signify induced eddy currents. The overall resistance of each wire can be obtained by summing the self and mutual resistances along a row or column of the resistance matrix. For instance, the resistance of wire 2 is 2042 /m whereas for wire 1 and wire 3, it is 1976 /m. The mutual resistance is less than 1% for side-by-side wires because the mutual coupling is relatively weak. To investigate further the proximity effect on wire resistance, three stacked wires, as shown in Figure 3.8(b), are simulated. The separation between wires is 1 m. At 1 GHz, the inductance and resistance matrix are L 11 L 12 L 13 1.24 1.23 1.21 L 21 L 22 L 23 = 1.21 1.24 1.23 H/m 1.21 1.23 1.24 L L L
31 32 33
(3.17)
and
40
R 11 R 12 R 13 2008 498 489 R 21 R 22 R 23 = 498 2012 498 /m 489 498 2004 R R R

31 32 33
(3.18)
respectively. In this case, the magnetic coupling is nearly prefect (k > 0.97) and as a result, the mutually induced eddy current is more signicant compared to the side-by-side conguration. In particular, the resistance of all three wires is approximately the same and is equal to 3000 /m which is 50% greater than the self resistance of each wire. 3.1.2.2 Skin Effect on Resistance To learn about the skin effect in practical systems, consider the coaxial transmission line shown in Figure 3.9(a) . At high frequencies, the current ow is limited to the outer surface of the inner conductor whereas the return current in the ring-shape conductor is confined to the inner surface. This is attributed to the fact that eddy currents are more severe at the center for the inner conductor and at the outer surface of the ring-shape outer conductor. In these regions, as a result, the current density is significantly lower than the dc level. For on-chip spiral inductors, the line segments can be treated as microstrip transmission lines such as the one shown in Figure 3.9(b). In this case, the high frequency current recedes to the bottom surface of the wire, which is above the ground plane [55][56]. The attenuation of the current density (J in A/m2) as a function of distance away from the bottom surface is shown in Figure 3.10 [57] and can be represented by J = J0 e
-x/
(3.19)
The current (I in A) is obtained by integrating J over the wire cross-sectional area. Since J only varies in the x direction, I can be calculated as
41
I = =
J dA 0 J 0 e
t -x/
w dx
(3.20)
= J 0 w t eff = J0 w (1 e
-t/
where t is the thickness of the wire. An effective thickness can be expressed as
H E
E H
Current
Conductor
(a) H (see Figure 3.10)
x t 0 E
(b) Figure 3.9: Eddy current effect in the conductors of a (a) coaxial and (b) microstrip transmission line.
42
J (A/m2) teff J0
Same Area
x (m) 0 t Figure 3.10: Effective thickness (teff) of a conductor with nite thickness (t) under skin effect.
t eff = ( 1 e
-t/
).
(3.21)
The effective thickness for aluminum and copper as a function of frequency is plotted in Figure 3.11. The dotted lines in each graph denotes the skin depth. At 1 GHz, the skin depth of Al and Cu are 2.8 m and 2.5 m respectively. With t = 3 m, teff for Al and Cu are 1.8 m and 1.7 m respectively. Note that at dc teff equals to t as approaches innity. On the other hand, at high frequencies, is much smaller than t and teff approaches as the exponential term in (3.21) vanishes. Substituting (3.20) and (3.21) into (3.13), R can be expressed as V R = ----------------------------------------------------- . -t/ J0 w (1 e ) Since V = El , = J0 l (3.22) can be rewritten as (3.23) (3.22)
43
100.0 Aluminum t = 10 m t = 3 m t = 2 m t = 1 m
10.0 teff (m) 1.0 0.1 0.01
0.10 1 Frequency (GHz) (a) t = 10 m t = 3 m t = 2 m t = 1 m
10
100.0 Copper
10.0 teff (m) 1.0 0.1 0.01
0.10 1 Frequency (GHz) (b)
10
Figure 3.11: Effective thickness of (a) aluminum and (b) copper as a function of frequency.
44
l R = ------------------------------------------t/ ) w (1 e
(3.24)
where and l represent the resistivity and length of the wire. As decreases with frequency, R increases. To compute the series resistance of a spiral inductor, (3.24) is used with l equal to the total length of all segments.
3.1.3 Feed-through Capacitance

The feed-through capacitance (Cs) models the parasitic capacitive coupling between input and output ports of the inductor. This capacitance allows the signal to flow directly from the input to output port without passing through the spiral inductor. Based on the inductors physical structure, both the crosstalk between adjacent turns and the overlap between the spiral and underpass contribute to Cs. However, since the adjacent turns are almost equipotential, the effect of the crosstalk capacitance is negligible. Furthermore, the crosstalk capacitance can be reduced by increasing the spacing between the turns. The overlap capacitance is more significant because of a larger potential difference between the spiral and the underpass [58][59]. Therefore, in the inductor model, it is sufficient to model Cs as the sum of all overlap capacitances, which is equal to ox 2 C s = n w --------------------t oxM1-M2 (3.25)
where n is the number of overlap, w is the spiral line width, and toxM1-M2 is the oxide thickness between the spiral and the underpass. To verify that the crosstalk capacitance is indeed unimportant to an inductors characteristics, consider the three-turn inductor and its equivalent models as shown in Figure 3.12. In the distributed model, the 3-turn inductor is divided into six half-turn sections. Each section is represented by an inductance and resistance. Furthermore, there are four crosstalk capacitances (Cct1Cct4) and three overlap capacitances (Cov1Cov3). The inductor layout is chosen such that the sum of crosstalk capacitance is equal to the sum of overlap capacitance. In the lumped model, the total inductance and resistance of the induc-
45
Port 1 Cov3 Cov2 Cov1 Port 2 Cct1 Cct3
Cct4 Cct2
(a) Cov1 Cov2 Cov3 Port 2 Cct4 Cct3 Cct2 Cct1 Port 1
(b) Cs = Cov1 + Cov2 + Cov3
Rs
Ls
(c) Figure 3.12: A three-turn inductor: (a) layout and relevant elements (b) distributed model and (c) lumped model.
46
tor are used. However, the lumped feed-through capacitance includes only the overlap part. Using a circuit simulation program such as SPICE, the real and imaginary parts of the inductor impedance are obtained. Three different cases are simulated with the distributed model. In the first case, both the overlap and crosstalk capacitances are included. In the second case, the crosstalk capacitances are omitted from the model. For the third case, only the overlap capacitances are included. As shown in Figure 3.13, the distinction between the inductor impedance using overlap and crosstalk and overlap only is barely noticeable. On the other hand, gross difference is observed when comparing overlap and crosstalk to crosstalk only. This can be explained by the fact that the overlap capacitances are effectively in parallel with one another and therefore they add together to account for most of the feed-through capacitance. In contrast, the crosstalk capacitances appear in series with each other and consequently have little inuence on the feed-through capacitance. Figure 3.13 also shows that by using the lumped model with overlap capacitance only, both the real and imaginary parts of the inductor impedance can be modeled with insignicant discrepancies up to 5 GHz.
3.1.4 Substrate Parasitics

The characteristics of microstrip structures on semiconductor substrate, especially metal on oxide on silicon, have been investigated extensively [60][63]. In general, a MOS microstrip structure can be modeled by a three-element network comprised of Cox, RSi and CSi (see Figure 3.1). Cox represents the oxide capacitance whereas RSi and CSi represent the silicon substrate resistance and capacitance, respectively. The physical origin of RSi is the silicon conductivity which is predominately determined by the majority carrier concentration. C Si models the high-frequency capacitive effects occurring in the semiconductor. For spiral inductors on silicon, the lateral dimensions are typically a few hundred micro-meters which is much larger than the oxide thickness and is comparable to the silicon thickness. As a result, the substrate capacitance and resistance are approximately proportional to the area occupied by the inductor and can be estimated by
47
10.0 Distributed model: Overlap and Crosstalk Overlap only Crosstalk only Lumped model: Overlap only
8.0 Re [Zin] ()
6.0
4.0
2.0
0.0 0.1 1.0 10.0 Frequency (GHz) (a) 100.0
10 Distributed model: Overlap and Crosstalk Overlap only Crosstalk only Lumped model: Overlap only
1 Im [Zin] (k)
0.1
0.01
0.001
0.1
1.0 10.0 Frequency (GHz) (b)
100.0
Figure 3.13: (a) Real and (b) imaginary parts of the input impedance of the inductor model circuits in Figure 3.12 for studying the importance of crosstalk and overlap capacitance to the overall feed-through capacitance.
48
ox 1 - l w ------- , C ox = -2 t ox 1 - l w C sub C Si = -2 and 2 R Si = ------------------------l w G sub
(3.26)
(3.27)
(3.28)
where Csub and Gsub are capacitance and conductance per unit area for the silicon substrates. ox and tox are the dielectric constant and thickness of the oxide layer between the inductor and the substrate. The area of the spiral is equal to the product of the spiral length, l , and width, w. C sub and G sub are functions of the substrate doping and are extracted from measurement results. The effects of lightly doped and epitaxial substrates on inductors will be studied extensively in Chapter 5.
3.2 A Physical Model

Combining the inductance and parasitics described in the previous sections, a physical model for spiral inductors on silicon is formed in Figure 3.14(a) . In Figure 3.14(b), Ls, Rs, and Cs remain unchanged as in Figure 3.14(a). The combined impedance of Cox, CSi, and RSi is substituted by Rp and Cp. Therefore, Rp and Cp are frequency dependent. The reason for this substitution is twofold: it facilitates the extraction of Rp and Cp from measured S parameters and the analysis of their effects on Q.
3.3 Testing and Parameter Extraction

To examine the validity of the proposed inductor model, square spiral inductors with different structural and process parameters were fabricated with standard silicon processing technology. This section describes the techniques for testing and parameter extraction.
3.3. Testing and Parameter Extraction
49
Cs
Ls
Rs
Cox
Cox
RSi
CSi
CSi
RSi
(a) Cs
Ls
Rs
Rp
Cp
Cp
Rp
(b) Figure 3.14: (a) Lumped physical model of a spiral inductor on silicon. (b) Equivalent model with combined impedance of Cox, CSi, and CSi substituted by Rp and Cp.
50
Probe Station
OPEN
G S G
Device Under Test
G S G
Figure 3.15: S parameters measurement set-up and a sample test structure consisted of an open and a device under test (DUT).
On-wafer testing was performed with a HP8720B Network Analyzer and Cascade Microtech coplanar ground-signal-ground (GSG) probes [64]. The measurement set-up is shown in Figure 3.15. The set-up is calibrated using the Cascade Impedance Standard
51
G On-chip Ground for Return Current 50
Device Under Test
50
Power Source On-chip Ground for Return Current G G
Figure 3.16: Equivalent circuit of the measurement set-up.
Substrate (ISS) [65]. The full two-port calibration procedure involves steps known as the short-load-open-through (SLOT). To ensure that the parasitics up to the GSG probe tips are indeed calibrated out and accounted for by the Network Analyzers built-in error models, several structures on the ISS with known values are measured and compared to the specification. These standard test structures include a 0.5-nH inductor, a 0.25-pF capacitor, various resistors, and a few attenuators. If the measured results are consistent with the standard specication, then the set-up is qualied for testing. It should be emphasized that the post-calibration measurements with standard structures are crucial for validating the calibration. The shunt parasitics of the test structure were de-embedded using open calibration structures fabricated next to the device under test (DUT) [66][68]. An equivalent circuit for the two-port measurement set-up is shown in Figure 3.16. Since the on-chip ground paths for the return currents appear in series with the DUT, the parasitic inductance and resistance of these ground paths should be made insignificant compared to the DUT impedance.
52
During the inductor measurements, the substrate was grounded from the wafer back-side through the testing chuck. Two-port S parameters were measured, instead of one-port parameter, to allow extraction of the inductance and other parasitics without any curve-tting. The extraction procedure is summarized in Figure 3.17 . From the de-embedded S parameters, the complex propagation constant and characteristic impedance are computed. Then, the lumped elements in the series and shunt branches of the inductor model in Figure 3.14(b) are solved using the relationships shown in the bottom block of Figure 3.17. To extract Ls, Rs, and Cs from the real and imaginary parts of the measured series impedance, some assumptions about Ls and Cs need to be made. Ls and Rs are subject to skin effect, which governs the magnetic field intensity and current density in the conductor at high frequencies [52]. As frequency increases, the penetration of magnetic eld into the conductor is attenuated, which causes reduction in the magnetic ux internal to the conductor. However, Ls does not decrease significantly with increasing frequency because it is predominantly determined by the magnetic flux external to the conductor. Thus, Ls can be approximated as constant with frequency. The skin effect on Rs is much more pronounced because Rs is directly affected by the non-uniform current distribution in the conductor. C s is considered independent of frequency since it represents the metal-to-metal overlap capacitance between the spiral and the center-tap. At low frequencies, the reactance is dominated by Ls because Ls is much greater than 1/Cs. Cs is extracted using the low-frequency L s value and the resonant frequency of the series branch. Then, with Cs held constant, Ls and Rs are solved using the real and imaginary parts of the series impedance at each measurement frequency. In the shunt branch, Rp and Cp can be extracted readily from the real and imaginary parts of the shunt admittance, respectively.
53
De-embedded S parameters
S to Transmission Matrix Conversion S 11 S 12 S 21 S 22 A B C D
Solve for Propagation Constant ( ) and Characteristic Impedance (Z0) cosh l Z 0 sinh l A B = 1 C D Z 0 sinh l cosh l
Ls Cs
Rs = l Z0
Rp Cp
2Z 0 = --------- = l
Rp Cp
Figure 3.17: Parameter extraction procedure for the lumped elements in the inductor model shown in Figure 3.14(b).
54
3.4 Measured and Modeled Results

3.4.1 Individual Elements in the Physical Model
The modeled and measured results for two spiral inductors fabricated on 10 -cm silicon substrate are shown in Figure 3.18. The inductors have the same layout and process parameters: 7 turns, 13-m width, 7-m spacing, 300-m outer dimension, and 4.5-m oxide. However, the spiral metal material is different for the two cases, one with copper and the other with aluminum. Both metal films are 1 m thick. The measured dc sheet resistance of the copper and aluminum lms is 20 m/sq. and 30 m/sq., respectively. For Ls, the Greenhouse method predicts an inductance value of 8.1 nH which is consistent with the measured data. Since the inductance is not a function of the metal material, both the copper and aluminum inductors are expected to achieve the same inductance. This is indeed observed in the experimental results shown in Figure 3.18(a). The slight decrease in Ls with frequency indicates that the skin effect on inductance is small and the assumption of constant Ls is in fact valid. The copper inductor has lower Rs than the aluminum sample, which is in agreement with the dc measurements. The skin effect on R s is more pronounced because R s is inversely proportional to the effective cross-sectional area. An increase in Rs with frequency is observed for both inductors. The modeled and measured values are in excellent agreement for both cases. This proves that the effective thickness ( t eff ) described in Section 3.1.2.2 is adequate to account for the frequency and material dependence of Rs. Using (3.25) with n = 6, w = 13 m, and toxM1-M2 = 1.3 m, the modeled value of Cs is 28 fF. From the measurements, the resonance frequency of the series branch in the inductor model is found to be approximately 11 GHz. With a low frequency Ls of about 8.2 nH, the extracted value of Cs is 26 fF, which is very close to the modeled value. The frequency behaviors of Rp and Cp are governed by Cox, CSi, and RSi. As shown in Figure 3.18(b), the measured shunt parasitics of the inductors are independent of the spiral
3.4. Measured and Modeled Results
55
10
25
20
Ls (nH)
4 Copper 2 Aluminum Model 0 0.1 1 Frequency (GHz) (a) 25 20 Rp (k) 15 10 5 0 0.1 10
10
Copper Aluminum Model
250 200 150 100 50 0 Cp (fF)
1 Frequency (GHz) (b)
10
Figure 3.18: Measured and modeled values of (a) Ls and Rs, (b) Cp and Rp for two inductors with different spiral metal materials: one with copper and the other with aluminum.
Rs ()
15
56
metal material. This further confirms that the proposed parameter extraction procedure and the inductor model are consistent with the physical effects. Using (3.26)(3.28), the modeled values of Cox, CSi, and RSi are 230 fF, 45 fF, and 850 , respectively. At low frequencies, the electric eld terminates at the oxide-silicon interface and Cp is primarily determined by Cox. Since almost all the electric energy is stored within the oxide layer along the spiral, little conduction current ows in the silicon substrate and thus Rp is large [61]. As frequency increases, the electric eld starts to penetrate into the silicon substrate which reduces Cp because of the series connection of oxide and silicon substrate capacitances. The roll-off in Rp signies increasing electric energy storage and hence more dissipation in the silicon substrate. At high frequencies, electric energy is stored mainly in the silicon substrate causing Cp and Rp to approach CSi and RSi respectively; Cox is effectively short-circuited. Based on this effect, Csub and Gsub in (3.27)(3.28) can be obtained by dividing the measured values of Cp and Rp at high frequencies by the spiral area.
3.4.2 Two-Port S Parameters

In the previous section, it is shown that the individual elements in the physical model is consistent with the values extracted from measured S parameters. To confirm that the physical model can indeed predict the overall inductor behavior, a comparison between the measured and modeled two-port S parameters is carried out. Using SPICE, two-port S parameters of the physical inductor model are generated. The model components are computed using the algorithm and equations described. Then, the modeled results are compared directly with the as-measured S parameters from the Network Analyzer. On the Smith Chart shown in Figure 3.19 , the modeled and measured S11 and S21 are graphed and show excellent agreement. In Figure 3.20 and Figure 3.21, the measured real and imaginary parts of the two-port S parameters are compared with the modeled values.
3.5. Impact of Technology on Inductor Performance
57
S11 S21 Model
Figure 3.19: Measured and modeled values of S11 and S21 plotted on a Smith chart.
3.5 Impact of Technology on Inductor Performance

To demonstrate the scalability of our model, spiral inductors with various structural parameters including different metal material, metal thickness, oxide thickness, substrate material, and layout geometry are fabricated and tested. The efficiency of an inductor is measured by its quality factor, Q, which is limited by the parasitic resistance and capacitance. In terms of the elements shown in Figure 3.14(b), the Q of a spiral inductor on silicon substrate can be derived as (See Chapter 4 for the detailed derivation.)
58
1.0 Re [S11] Re [S22] Model
0.8 Re [S11], Re [S22]
0.6
0.4
0.2
0.0 0.1 1 Frequency (GHz) (a) 1.0 Im [S11] Im [S22] Model 10
0.8 Im [S11], Im [S22]
0.6
0.4
0.2
0.0
0.1
10
Figure 3.20: Measured and modeled values of (a) real and (b) imaginary parts of S11 and S22.
59
1.0
0.8 Re [S12], Re [S21]
0.6
0.4 Im [S12] Im [S21] Model 0.1 1 Frequency (GHz) (a) 0.0 10
0.2
0.0
-0.2 Im [S12], Im [S21]
-0.4
-0.6 Im [S12] Im [S21] Model 0.1 1 Frequency (GHz) (b) 10
-0.8
-1.0
Figure 3.21: Measured and modeled values of (a) real and (b) imaginary parts of S12 and S21.
60
2(C + C ) Ls Rp Rs s p - ------------------------------------------------------------- 1 ------------------------------Q = -------- 2 Ls ( C s + C p ) 2 Rs R + [ ( L R ) + 1 ] R Ls p s s s
Ls - Substrate Loss Factor Self-resonance Factor = --------Rs
(3.29)
where L s / Rs accounts for the magnetic energy stored and the ohmic loss in the series resistance. The second term in (3.29) is the substrate loss factor representing the energy dissipated in the semiconducting silicon substrate. The last term is the self-resonance factor describing the reduction in Q due to the increase in the peak electric energy with frequency and the vanishing of Q at the self-resonant frequency. Hence, the self-resonant frequency can be solved by equating the last term in (3.29) to zero. Figure 3.22(a) shows the measured and modeled Q of the copper and aluminum inductors studied in the previous section. At low frequencies, Q is well described by Ls/Rs for both inductors. The copper inductor has higher Q because it has lower series resistance. As frequency increases, the quality factors start to deviate from Ls/Rs due to the substrate effects. The rapid degradation of Q at high frequencies is a combined effect of the substrate loss and the self-resonance. At high frequencies, the quality factors merge together and reduce to zero at the self-resonant frequency. This indicates that the substrate effects are independent of the metal layer as expected. The close agreement between the measured and modeled results indicates the physical model is capable of accounting for variation in the metal material. Figure 3.22(b) shows the relative importance of the substrate loss and the self-resonance to the overall quality factor for the two inductors. At low frequencies, both the substrate loss factor and the self-resonance factor are at unity. As frequency increases, the substrate loss factor starts to drop from unity earlier than the self-resonance factor. In particular, the substrate loss alone causes 10 30% reduction from L s /R s at 1 2 GHz. Physically, the substrate loss stems from the penetration of electric field into the silicon. As the potential drop in the semiconductor increases with frequency, the energy dissipation in the substrate through RSi becomes more severe.
61
10 Copper Aluminum Model Ls / Rs
6 Q 4 2 0 0.1
1 Frequency (GHz) (a)
10
1.0 Substrate Loss Factor 0.8 0.6 0.4 Copper 0.2 0.0 0.1 Aluminum Model
1.0 0.8 0.6 0.4 0.2 0.0 1 Frequency (GHz) (b) 10 Self-Resonance Factor
Figure 3.22: Measured and modeled values of (a) Q and (b) degradation factors for two inductors with 1-m spirals in copper and aluminum.
62
Besides replacing aluminum by copper, another approach to reduce the series resistance is to use thicker metal for the spiral. Figure 3.23 illustrates the effect of different metal thicknesses and schemes on Q. Four inductors with different metal thicknesses are fabricated and measured. A significant improvement in Q is obtained by increasing the aluminum thickness from 1 m to 2 m. However, the 3 m data reveals that further thickening the metal has diminishing improvements in Q. This is due to the more severe skin effect suffered by the thicker spiral. Since the current ow is concentrated at the bottom side of the spiral, metal thicker than the skin depth is ineffective for lowering the series resistance. For instance, at 1 GHz, the effective thicknesses of 1-m, 2-m, and 3-m aluminum are 0.84 m, 1.43 m, and 1.83 m respectively. After including the substrate factors, the improvement in Q at 1 GHz is 57% and 81% as the metal thickness is increased from 1 m to 2 m and 3 m. This effect is well predicted by the physical inductor model. Since the thinner metal suffers less severe skin effect, one may attempt to obtain more effective thickness by building an inductor with three levels of 1 m alumi-
8 3 levels of 1 m Al in parallel 3 m Al 2 m Al 1 m Al Model
0 0.1
1 Frequency (GHz)
10
Figure 3.23: Effect of metal scheme on Q.
63
num connecting in parallel. That is the three spirals are connected to each other only at the ends and are isolated by oxide along the path. The measurement, however, shows that Q obtained in this case is the same as the one level 3 m inductor. At rst, this observation is counter-intuitive. As discussed in Section 3.1.2.1, because the three layers are close to each other, there are strong mutual coupling between them. The proximity effect induces additional eddy currents comparing to an isolated 1 m layer. This explains that breaking up the 3 m into three levels of 1 m results in essentially the same effective thickness. Q can be improved by fabricating the inductor farther away the silicon substrate with thicker oxide. Three inductors with the same layout but different oxide thicknesses are fabricated and measured. Figure 3.24 shows that increasing oxide thickness improves Q because the substrate effects are suppressed. But as frequency increases, Cox is effectively short-circuited, substrate effects become dominant, and the Qs merge together. Figure 3.25 shows that lowering silicon substrate resistivity decreases R Si and increases CSi, causing the Q roll-off to occur at a lower frequency and a reduction of the
8 6.0 m oxide 6 4.5 m oxide 2.5 m oxide Model
0 0.1
1 Frequency (GHz)
10
Figure 3.24: Effect of oxide thickness on Q.
64
8 10 -cm Si: Csub = 1.610-3 fF/m2 Gsub = 4.010-8 S/m2 6 -cm Si: Csub = 6.010-3 fF/m2 Gsub = 1.610-7 S/m2 Model
0 0.1
1 Frequency (GHz)
10
Figure 3.25: Effect of substrate resistivity on Q. self-resonance frequency. The increase in CSi can be attributed to the fact that in a more conductive substrate, the electric eld is terminated closer to the silicon surface and therefore the effective substrate is thinner. Figure 3.26 illustrates the effect of layout area on Q for inductors with the same inductance but different layout parameters. Three 8-nH inductors are designed with outer dimension equal to 550, 400, and 300 m. The inductors fabricated using larger area can accommodate wider line width; and as a result, achieve lower series resistance. However, they also have more shunt substrate parasitics because they occupy larger area. At low frequencies, the larger inductors offer higher Qs because of lower series resistance. At high frequencies, the substrate effects dominate and the smaller inductors actually achieve higher Qs. At about 1 GHz, the medium size inductor achieves the highest Q because the resistive loss and the substrate effects are balanced. Published results are used to further confirm the inductor model and the equation for Q. Figure 3.27 shows a comparison of the measured Qpeak of the inductors presented by
65
8 Outer Dimension, Line Width 550 m, 41 m 400 m, 24 m 300 m, 13 m Model
0 0.1
1 Frequency (GHz)
10
Figure 3.26: Effect of layout area on Q. 20 Line Width 5 m Q Predicted by our model 10 9 m 14 m 19 m 10 24 m (b) 5
0 0 5 10 15 Measured Qpeak presented by Ashby et al. 20
Figure 3.27: Verication of the physical model using published data.
66
Ashby et al. [12] and the Q values predicted by our model. These 15 inductors were fabricated using 4.5 m of gold on silicon with high substrate resistivity of about 200 ohm-cm. Excellent agreement is obtained.
3.6 Design Methodology

The trade-off between series resistance and substrate losses represents a practical scenario that RF designers encounter when using on-chip inductors in their circuits. As an example, consider that a 8 nH inductor is needed for an application at 1.6 GHz. Furthermore, because of the chip size limit, the inductor can occupy an area no larger than 400 m by 400 m. A design tool capable of optimizing the inductor layout by considering these constraints and the technology profile can significantly expedite the design flow. In Figure 3.28, Q contour plots are presented. These plots are generated using the physical inductor model. The contour curves represent the values of Q which are plotted as a function of the inductance and the outer dimension of the square spiral. Each point on the contour plot corresponds to a specific inductor layout design which is defined by the parameter set {N, w, s, od}, where N is the number of turns, w is the metal width, s is the metal spacing, and od is the outer dimension of the inductor. These contour plots can identify the optimal spiral layout for achieving a specific inductance with the highest Q possible for a given technology at the frequency of interest. At low frequencies, such as 600 MHz shown in Figure 3.28(a), larger areas result in higher Qs for all inductance values considered. This is because lower series resistances can be achieved and they are the limiting loss mechanism at low frequencies. As the frequency increases to 1 GHz, the substrate loss and self-resonance effects are starting to become important for inductors occupying large areas. As a result, the Q contours at the upper-right-hand corner begin to roll off. For the design example (maximum Q for a 8 nH inductor at 1.6 GHz), the contour plot in Figure 3.28(c) shows that the highest Q achievable for 8 nH is 5.5 using this technology. This is achieved with a spiral that has an outer dimension of 300 m. This is confirmed by the experimental data. Note that if the 8-nH
3.6. Design Methodology
67
10 0.6 GHz Inductance (nH) 8
Measured Q 1.7 3.4 1.0 GHz 1
Measured Q 2.9 4.6
1 3 5 3 5 7 9
6 4 2 0 0
100 200 300 400 Outer Dimension (m) (a) Measured Q 4.0 5.2 1.6 GHz 1 3 5 4
100 200 300 400 Outer Dimension (m) (b) Measured Q 4.0 6.1 3.0 GHz 1 4 2 4 5
10 Inductance (nH) 8 6 4 2 0 0
7 9
7 9
100 200 300 400 Outer Dimension (m) (c)
100 200 300 400 Outer Dimension (m) (d)
Figure 3.28: Contour plots of Q as a function of inductance and outer dimension of square spiral inductors at (a) 0.6 GHz, (b) 1.0 GHz, (c) 1.6 GHz, and (d) 3.0 GHz.
68
inductor were fabricated using the maximum area available (i.e. 400 m by 400 m), a lower Q would result while precious chip area would be wasted. Figure 3.28(d) shows that if the frequency of operation is increased to 3 GHz, the inductor with an outer dimension of 300 m will no longer be the optimal design because the substrate effects are now even more severe. In fact, an inductor layout that has an outer dimension of 220 m will offer the highest Q of slightly above 5. In addition to optimizing Q in a limited area, the inductor design methodology presented above can have different combinations of optimization targets and constraints. For example, in a tuned amplifier with shunt-peaking load [3], it is desirable to maximize the product of Q and inductance instead of Q. For inductors used as emitter or source degeneration [5], it is important to limit the parasitic capacitances. In general, the contour plots can be tailored for specic design goals.
3.7 Summary
In this chapter, a physical model for planar spiral inductors on silicon is presented. The characteristics of each component in the model have been investigated extensively. The physical phenomena important to the prediction of Q are considered and analyzed. The scalable inductor model shows excellent agreement with measured and published data. The effects of various layout and process parameters on Q are explained using the inductor model and confirmed with experimental data. Finally, Q contour plots are introduced to assist RF designers to optimize inductor design under various constraints.
Chapter
Patterned Ground Shields
It has been shown that the inductor quality factor (Q) degrades at high frequencies due to energy dissipation in the semiconducting silicon substrate in Chapter 3. For RF circuits, the importance of noise coupling via the substrate at gigahertz frequencies has been reported [69][70]. As spiral inductors occupy substantial chip area, they can potentially be the source and receptor of detrimental noise coupling. Furthermore, the physical phenomena associated with the substrate effects are complicated to characterize and model. Therefore, decoupling the inductor from the substrate can enhance the overall performance: increase Q, improve isolation, and simplify modeling. Some approaches have been proposed to address the substrate issues; however, they are accompanied by drawbacks. Ashby et al. [12] suggested the use of high-resistivity (150 to 200 -cm) silicon substrate to mimic the low-loss semi-insulating GaAs substrate, but this is an uncommon option for current silicon technologies. Chang et al. [71] demonstrated that etching a pit in the silicon substrate under the inductors can remove the substrate effects. However, the etch adds extra processing cost and is not readily available. Moreover, it raises reliability concerns such as packaging yield and long-term mechanical stability. For low-cost integration of inductors, the solution to substrate problems should avoid increasing process complexity. This chapter presents a patterned ground shield, which is compatible with standard silicon technologies, to reduce the unwanted substrate effects. To provide some background, Section 4.1.1 presents a discussion on the fundamental definitions of Q for inductors and LC-tanks. Next, the physical model for spiral inductors on silicon is reviewed. The mag69
70
Chapter 4: Patterned Ground Shields
netic energy storage and loss mechanisms in an on-chip inductor are discussed. Based on this insight, it is shown that energy loss can be reduced by shielding the electric eld of the inductor from the silicon substrate. Then, the drawbacks of a solid ground shield are analyzed. This leads to the design of a patterned ground shield. Design guidelines for parameters such as shield pattern and resistance are given. In Section 4.2, experimental results are reported to study the effects of shield resistance and pattern on inductance, parasitic resistances and capacitances, and inductor Q. Next, the improvement in Q of a 2-GHz LC tank using a shielded inductor is illustrated. A study of the noise coupling between two adjacent inductors and the efficiency of the ground shield for isolation are also presented.
4.1 Design Considerations

4.1.1 Denitions of Quality Factor
The efciency of an inductor is measured by its quality factor, Q, which is dened as [72] Energy Stored Q = 2 ------------------------------------------------------------------------------------------ . Energy Loss in One Oscillation Cycle (4.1)
Interestingly, (4.1) also defines the Q of a LC tank. The definition in (4.1) is fundamental in the sense that it does not specify which element stores or dissipates the energy. The subtle distinction between an inductor Q and a LC-tank Q lies in the intended form of energy storage. For an inductor, only the energy stored in the magnetic field is of interest. Any energy stored in the inductors electric field, because of some inevitable parasitic capacitances in a real inductor, is counter-productive. Hence, Q is proportional to the net magnetic energy stored, which is equal to the difference between the peak magnetic and electric energies. An inductor is at self-resonance when the peak magnetic and electric energies are equal. Therefore, Q vanishes to zero at the self-resonant frequency. Above the self-resonant frequency, no net magnetic energy is available from an inductor to any external circuit. In contrast, for a LC tank, the energy stored is the sum of the average magnetic and electric energies. Since the energy stored in a (lossless) LC tank is constant and oscil-
4.1. Design Considerations
71
lates between magnetic and electric forms, it is also equal to the peak magnetic energy, or the peak electric energy. The rate of the oscillation process is the tanks resonant frequency at which Q is dened. For a lossless LC tank, Q is innite. To illustrate the distinction between these two cases, consider a simple parallel RLC circuit first as an inductor model, then as a LC-tank model. The expressions for the energies and the resonant frequency, 0, are: V0 E Peak Magnetic = -------------, 22 L V 0C -, E Peak Electric = ---------2 2 V 0 - ------, E Loss in One Oscillation Cycle = ---- 2R V0 E Average Magnetic = -------------, 42 L V 0C E Average Electric = ----------, 4 and 1 -, 0 = ----------LC (4.7)
2 2 2 2 2
(4.2)
(4.3)
(4.4)
(4.5)
(4.6)
where V0 denotes the peak voltage across the circuit terminals. In terms of an inductor model, C is regarded as the parasitic capacitance of the inductor. According to the definition of inductor Q, it can be shown that Peak Magnetic Energy Peak Electric Energy Q Inductor = 2 --------------------------------------------------------------------------------------------------------------Energy Loss in One Oscillation Cycle 2 R = ------- 1 ------ L 0 (4.8)
72
which equals to zero at = 0, and is less than zero beyond 0. It is worthwhile to mention that the result in (4.8) can also be obtained using the ratio of the imaginary to the real parts of the circuit impedance. The circuit impedance is inductive below 0 and capacitive above 0. In terms of a LC-tank model, C is regarded as the tank capacitance of the LC oscillator. The Q can be expressed as Average Magnetic Energy + Average Electric Energy Q Tank = 2 ------------------------------------------------------------------------------------------------------------------------------------Energy Loss in One Oscillation Cycle = 0 Peak Magnetic Energy = 2 -----------------------------------------------------------------------------------------Energy Loss in One Oscillation Cycle R = -------- L 0 = 0
(4.9)
Peak Electric Energy = 2 -----------------------------------------------------------------------------------------= 0 RC Energy Loss in One Oscillation Cycle = 0 R = -------------LC The above result can also be derived using a more well-known relationship: the ratio of the resonant frequency to the 3-dB bandwidth. Both Q definitions discussed are of importance, and their applications are determined by the intended function in a circuit. When evaluating the quality of an on-chip inductor as a single element, the denition in (4.8) is more appropriate. In Section 4.2, when LC tanks are studied, the denition in (4.9) is used.
4.1.2 Understanding of Substrate Effects

The physical model developed in Chapter 3 is shown in Figure . 4.1 An on-chip inductor is physically a three-port element including the substrate. The one-port connection shown avoids unnecessary complexity in the following analysis and at the same time preserves the inductor characteristics. In the model, the series branch consists of Ls, Rs, and Cs. Ls represents the spiral inductance which can be computed using the Greenhouse method. Rs is the metal series resistance whose behavior at RF is governed by the eddy current effect. This resistance symbolizes the energy losses due to the skin effect in the spiral intercon-
73
Cox
Rs
Cs Ls RSi CSi
Figure 4.1: Lumped physical model of a spiral inductor on silicon.
nect structure as well as the induced eddy current in any conductive media close to the inductor. The series feed-forward capacitance, Cs, accounts for the capacitance due to the overlaps between the spiral and the center-tap underpass. The effect of the inter-turn fringing capacitance is usually small because the adjacent turns are almost equipotential, and therefore it is neglected in our model. The overlap capacitance is more signicant because of the relatively large potential difference between the spiral and the center-tap underpass. The parasitics in the shunt branch are modeled by Cox, CSi, and RSi. Cox represents the oxide capacitance between the spiral and the substrate. The silicon substrate capacitance and resistance are modeled by CSi and RSi respectively. The ohmic loss in RSi signies the energy dissipation in the silicon substrate. In Figure 4.2 , the combined impedance of Cox, CSi, and RSi is substituted by Rp and Cp which are therefore frequency dependent while Ls, Rs, and Cs remain unchanged as in Figure 4.1. The reason for this substitution is twofold: it facilitates the analysis of Rps effect on Q and the extraction of the shunt parasitics from measured S parameters. In terms of the circuit elements in Figure 4.2, the energies can be expressed as:
74
Rs
Rp
Cp
Cs Ls
Figure 4.2: Equivalent model with the combined impedance of Cox, CSi, and RSi in Figure 4.1 substituted by Rp and Cp.
V 0 Ls E Peak Magnetic = ------------------------------------------, 2] 2 [ ( Ls ) 2 + Rs V 0(Cs + C p) -, E Peak Electric = ------------------------------2 and Rs 2 V 0 1 - ------ ------ + -----------------------------E Loss in One Oscillation Cycle = ----, 2 R p ( L )2 + R 2
s s 2 2
(4.10)
(4.11)
(4.12)
where R si ( C ox + C Si ) 1 R p = ------------------------ + --------------------------------------- , 2 2 2 C ox R Si C ox

2
(4.13)
75
1 + ( C ox + C Si ) C Si R Si -, C p = C ox -------------------------------------------------------------2 2 2 1 + ( C ox + C Si ) R Si derived by substituting (4.10)(4.12) into (4.8):

2(C + C ) Ls Rp Rs s p - ------------------------------------------------------------- 1 ------------------------------Q = -------- 2 Ls ( C s + C p ) 2 Rs R + [ ( L R ) + 1 ] R Ls p s s s
(4.14)
and V0 denotes the peak voltage across the inductor terminals. The inductor Q can be
Ls - Substrate Loss Factor Self-resonance Factor = --------Rs
(4.15)
where L s / Rs accounts for the magnetic energy stored and the ohmic loss in the series resistance. The second term in (4.15) is the substrate loss factor representing the energy dissipated in the semiconducting silicon substrate. The last term is the self-resonance factor describing the reduction in Q due to the increase in the peak electric energy with frequency and the vanishing of Q at the self-resonant frequency. Hence, the self-resonant frequency can be solved by equating the last term in (4.15) to zero. From (4.15), it can be seen that the substrate loss factor approaches unity as R p approaches infinity. In other words, by increasing Rp to infinity, we can reduce the substrate loss. From (4.13), it can be shown that Rp approaches infinity as RSi goes to zero or infinity. This is an important observation because it implies that Q can be improved by making the silicon substrate either a short or an open thereby eliminating energy dissipation. Using high-resistivity silicon, or etching away the silicon, is equivalent to making the substrate an open circuit. In this paper, we explored the option of making the substrate a short circuit to eliminate the loss. The approach is to insert a ground plane to block the inductor electric eld from entering the silicon.
4.1.3 Drawback of Solid Ground Shields

The effectiveness of solid ground shield for reducing silicon parasitics has been reported. Rofougaran et al. used metal one as ground shields for metal-two bond-pads to improve
76
the input impedance matching of a low-noise-amplier fabricated in CMOS process [73]. Tsukahara et al. used a similar technique with polysilicon layer as ground shields for metal-insulator-metal capacitors in a bipolar process [74]. The polysilicon ground shields eliminated the silicon parasitics associated with the bottom plate of the capacitors. At 1 GHz, 30-dB reduction in substrate cross-talk was reported. A solid conductive ground shield (see Figure 4.3 )can be inserted between the inductor
and the substrate to provide a short to ground. This is equivalent to placing a small resistance in parallel with CSi and RSi of the circuit model in Figure 4.1. Physically, the electric eld of the inductor is terminated before reaching the silicon substrate. One of the serious drawbacks with this approach is that the solid ground shield also disturbs the inductors magnetic field. According to the Lenzs Law, image current, also known as loop current, will be induced in the solid ground shield by the magnetic eld of the spiral inductor. The image current in the solid ground shield will ow in a direction opposite to that of the current in the spiral. The resulting negative mutual coupling between the currents reduces the magnetic eld, and thus the overall inductance. Using an equivalent circuit model, one can treat the inductor with the ground shield as a transformer. In Figure 4.4, the primary and secondary circuits represent the spiral and the solid ground shield respectively. The induced current flowing in the secondary inductor will impose a counter-electromotive-force on the primary inductor. This effect can be accounted for by adding a reected impedance, Zr, in series with the impedance of the primary circuit [75]. Zr can be expressed in terms of the mutual inductance, M, and the series impedance of the secondary circuit as (M ) -. Z r = ------------------------R2 + j L2 Therefore, the input impedance seen by the source is Z in = R 1 + j L 1 + Z r . (4.17)
2
(4.16)
77
(a)
(b) Figure 4.3: (a) Perspective view of a spiral inductor on solid ground shield and the resulting electromagnetic eld lines. The elds are substantially attenuated by the shield. (b) Perspective view of a solid ground shield showing the induced loop current and its associated magnetic eld lines.
78
I1
I2
R1 Zin M L1
R2
L2
Figure 4.4: Circuit model for illustrating the effects of negative mutual coupling between a spiral inductor and a solid ground shield. Note that the imaginary part of Zr is negative which signifies the reduction in the overall inductance. Also of importance is the increase in the overall resistance due to the real part of Zr, which denotes the additional energy loss associated with the ground shield conductor. From (4.16) and (4.17), one can easily show that the effect of Zr on Zin diminishes as R2 approaches infinity. An infinite R2 can be achieved by inserting features in the ground shield that oppose the ow of the image current.
4.1.4 Design of Patterned Ground Shields

To increase the resistance to the image current, the ground shield is patterned with slots orthogonal to the spiral as illustrated in Figure 4.5 [76]. The slots act as an open circuit to cut off the path of the induced loop current. The slots should be sufficiently narrow such that the vertical electric field cannot leak through the patterned ground shield into the underlying silicon substrate. With the slots etched away, the ground strips serve as the ter-
79
Induced Loop Current
Ground Strips
Slots between Strips
Figure 4.5: Close-up photo of the patterned ground shield.
mination for the electric eld. The ground strips are merged together around the four outer edges of the spiral. The separation between the merged area and the edges is not critical. However, it is crucial that the merged area does not form a closed ring around the spiral since it can potentially support unwanted loop current. The merged area of the shield should be strapped with the top layer metal to provide a low-impedance path to ground. The general rule is to prevent negative mutual coupling while minimizing the impedance to ground.
80
The shield resistance is another critical design parameter. The purpose of the patterned ground shield is to provide a good short to ground for the electric field. Since the finite shield resistance contributes to energy loss of the inductor, it must be kept minimal. Specifically, by keeping the shield resistance small compared to the reactance of the oxide capacitance, the voltage drop that can develop across the shield resistance is very small. As a result, the energy loss due to the shield resistance is insignificant compared to other loses. A typical on-chip spiral inductor has parasitic oxide capacitance between 0.25 to 1 pF depending on the size and the oxide thickness. The corresponding reactance due to the oxide capacitance at 1 to 2 GHz is on the order of 100 , and hence shield resistance of a few ohms is sufciently small not to cause any noticeable loss. As the magnetic eld passes through the patterned ground shield, its intensity is weakened due to the skin effect [52]. This directly causes a decrease in the inductance since the magnetic flux is lessened in the space occupied by the ground shield layer. To avoid this attenuation, the shield must be signicantly thinner than the skin depth at the frequency of interest. For example, the skin depth of aluminum at 2 GHz is approximately 2 m which is only three to four times the typical metal-one thickness. This implies that using a typical metal one layer for the shield may result in reduction of the magnetic field intensity and hence the inductance. Polysilicon could be a better choice for the ground shield.
4.2 Experimental
4.2.1 Experiment Design
In Figure 4.6, the test structures are shown for the inductors studied in this work: (a) no ground shield (NGS), (b) solid ground shield (SGS), and (c) patterned ground shield (PGS). Each spiral is fabricated using 2-m thick aluminum with 12-m /s q . sheet resistance. A 1-m thick underpass is used to contact the center of the spiral. The spiral and the ground shield are separated by 5.2-m of oxide. The ground shield is separated from the silicon substrate by 0.4-m of oxide. The inductors are fabricated on 10 to 20 -cm bulk
4.2. Experimental
81
(a)
(b)
(c) Figure 4.6: Die photos of ground-signal-ground (GSG) test structure and the inductors: (a) spiral inductor with no ground shield (NGS), (b) solid ground shield (SGS) shown without and with spiral, (c) patterned ground shield shown without and with spiral.
82
silicon substrates. Each inductor has 7 turns, 15-m line width, and 5-m line space. The outer dimension of the spirals is 300 m. The spiral layout is optimized to achieve maximum Q for the un-shielded inductor at about 1.5 GHz. The same layout is used for the shielded inductors to demonstrate the general advantage of inserting the PGS beneath an inductor without deliberate optimization. This implies that further improvement for the shielded inductor is attainable with the layout optimized to account for the parasitics of the shield. To investigate the effect of shield pattern, ground shields with different slot widths (1.5 and 2.5 m) and pitches (5 and 20 m) are fabricated. To study the effect of shield resistance, 0.5-m aluminum (64 m / sq.) and 0.5-m doped polysilicon (12 / sq.) are used to implement the shield. The polysilicon sheet resistance is chosen to be similar to that of MOSFET gates or BJT emitters. In technologies with silicided gate or emitter, the sheet resistance of the polysilicon layer can be as low as a few ohms per square which is more suitable for our purpose. Nevertheless, the measured results will reveal that our doped polysilicon is conductive enough not to cause any observable loss. Noise coupling between inductors is studied. Crosstalk was measured between two adjacent un-shielded inductors on substrates with different resistivities. The test structure is shown in Figure 4.7. Each inductor has one end grounded, and the metal ground rings surrounding the inductors are not connected. The efciency of the ground shield for isolation is evaluated using the same test structure with shields inserted underneath the inductors.
4.2.2 Effects on Inductance and Parasitics

In Figure 4.8(a) , measurement results for the effect of aluminum ground shields on Ls are plotted. Two inductors with NGS on 11 and 19--cm substrates are included for comparison. For the inductors without ground shields, the extracted Lss are about 8 nH: the slight decrease with frequency justifies the assumption that Ls is almost frequency-invariant. Furthermore, no noticeable difference in the Lss is observed for the two different sub-
4.2. Experimental
83
Figure 4.7: Two-port test structure for measuring crosstalk via substrate between two adjacent inductors (shown with un-shielded inductors). strates conrming that the magnetic elds of the inductors do not interact strongly with the substrates. The extracted Css are 18 fF: both inductors have the same Cs since the layout and process parameters are identical except the substrate resistivity. In the shielded inductors, however, Ls can no longer be assumed as frequency-invariant due to the induced loop current and attenuation of the magnetic flux in the shield layer. The extraction of Ls, consequently, is more difficult. In contrast, it is reasonable to expect Cs to remain the same, with the introduction of the shield. Therefore, Ls of the shielded inductors are extracted with Cs equal to 18 fF. For the inductor with SGS, the extracted Ls decreases signicantly as frequency increases. This is caused by the negative mutual coupling between the spiral and the SGS as explained in Section II-C. With the PGS, most of the inductance is recovered, which confirms the effectiveness of the slot pattern for stopping the image current. Close inspection reveals that the inductance for the PGS case is lower than the two NGS cases and the difference increases with frequency. This suggests that aluminum is too conductive to be optimal as the ground shield layer. In Figure 4.8(b), the extracted Rs of the inductors with NGS increases with frequency due to the skin effect of the spiral conductor.
84
10
Ls (nH)
6 PGS SGS NGS (19 -cm) NGS (11 -cm)
0 0.1 1 Frequency (GHz) (a) 10
20
Rs ()
15
10
0.1
10
Figure 4.8: Effect of aluminum ground shields on: (a) spiral inductance (Ls), (b) series resistance (Rs).
4.2. Experimental
85
The SGS case has signicantly higher Rs due to the image current. On the other hand, the inductor with PGS has the same Rs as the inductors with NGS because there is no image current. For the shunt parasitics shown in Figure 4.9, the two NGS cases show a strong frequency dependence. The frequency behaviors of Cp and Rp are governed by Cox, CSi, and RSi. At low frequencies, the electric eld terminates at the oxide-Si interface and Cp is primarily determined by Cox. Since almost all electric energy is stored within the oxide layer along the spiral, little conduction current ows in the silicon substrate and thus Rp is large. As frequency increases, the electric eld starts to penetrate into the silicon substrate which reduces Cp because of the series connection of oxide and silicon substrate capacitances. The roll-off in Rp signies increasing energy dissipation in the silicon substrate. At high enough frequencies, Cp and Rp approach CSi and RSi respectively as Cox is effectively short-circuited. For the shielded inductors, Cps are determined by the oxide capacitance between the spiral and the ground shield, which is slightly higher than the un-shielded cases because of a thinner oxide. Rps of the shielded inductors are very large indicating that there is essentially no energy loss in the ground shields. Although lower Cps for the NGS cases would seem more desirable, the lossy Rps are more detrimental. Measured results will prove that eliminating the substrate loss, i.e. making Rp approach innity, is far more important for improving the inductor Q. That is, the PGS eliminates the lossy frequency-variant capacitance with a larger lossless frequency-invariant one. In Figure 4.10 and Figure 4.11, the measured results for inductors with polysilicon ground shields are plotted against the same un-shielded inductors. In the SGS case, the image current starts to build up above 1 GHz. Although it does not lead to noticeable reduction in Ls, it causes Rs to increase more rapidly than the NGS cases. On the other hand, the polysilicon PGS does not deteriorate Ls or Rs, and terminates the inductors electric field to provide the desired shielding from the substrate. For both aluminum and polysilicon PGSs, the measurement results are similar for the different slot widths and pitches.
86
300 250 200 Cp (fF) 150 100 50 0 0.1 1 Frequency (GHz) (a) 10 PGS SGS NGS (19 -cm) NGS (11 -cm)
20
15 Rp (k)
PGS SGS NGS (19 -cm) NGS (11 -cm)
10
0.1
10
Figure 4.9: Effect of aluminum ground shields on: (a) parasitic capacitance (Cp), and (b) parasitic resistance (Rp).
4.2. Experimental
87
10
Ls (nH)
PGS SGS NGS (19 -cm) NGS (11 -cm) 0.1 1 Frequency (GHz) (a) 10
20
Rs ()
15
10
0.1
10
Figure 4.10: Effect of polysilicon ground shields on: (a) spiral inductance (Ls), (b) series resistance (Rs).
88
300 250 200 Cp (fF) 150 100 50 0 0.1 1 Frequency (GHz) (a) 10 PGS SGS NGS (19 -cm) NGS (11 -cm)
20
15 Rp (k)
PGS SGS NGS (19 -cm) NGS (11 -cm)
10
0.1
10
Figure 4.11: Effect of polysilicon ground shields on: (a) parasitic capacitance (Cp), and (b) parasitic resistance (Rp).
4.2. Experimental
89
4.2.3 Improvement in Inductor Q

Figure 4.12 show the effects of aluminum and polysilicon ground shields on Q. The inductor with aluminum SGS has the lowest Q because of its lowest Ls and highest Rs. In Figure 4.12(b), the polysilicon SGS yields a Q similar to those of the NGS cases indicating that it is resistive enough to prevent most of the image current from flowing. Finally, the polysilicon PGS, which combines the appropriate sheet resistance and pattern, yields the most improvement in Q, range from 10-33%, between 1 to 2 GHz. Note that the inclusion of the ground shields increases Cp, which causes a fast roll-off in Q above the peak-Q frequency and a reduction in the self-resonant frequency. Comparison between the inductor parameters for the NGS (11 -cm) and polysilicon PGS cases is shown in Table 4.1. The results at 2 GHz are compared to emphasize that the relative importance of the degradation mechanisms above the peak-Q frequency. In particular, the un-shielded inductor suffers greatly from substrate loss with nearly 50% reduction from L s / Rs. Although the shielded inductor has a lower self-resonance factor, it is almost free of substrate loss. The overall effect is a 33% improvement in Q at 2 GHz with the addition of polysilicon PGS. Further optimization of the shielded inductor layout to decrease the self-resonance factor and increase the Q is possible.
Table 4.1:
Comparison of measured inductor parameters for the NGS (11 -cm) and polysilicon PGS cases at 2 GHz. NGS Polysilicon PGS 7.4 8.5 18.0 268.2 15.0
Ls (nH) Rs () Cs (fF) Cp (fF) Rp (k)
7.5 8.2 18.0 108.1 1.2
90
0.1
1 Frequency (GHz) (a)
10
0.1
10
Figure 4.12: Effect of (a) aluminum and (b) polysilicon ground shields on Q.
4.2. Experimental
91
NGS L s /Rs Substrate Loss Factor Self-resonance factor Q Self-resonant Frequency (GHz) 11.5 0.52 0.85 5.08 6.8
Polysilicon PGS 10.9 0.94 0.66 6.76 3.6
4.2.4 Improvement in Q of a LC-Tank

In RF circuits, an inductor is often used to form a LC tank. Figure 4.13 plots the frequency behavior of the tank impedance for two 2-GHz LC tanks to demonstrate the impact of the 8-nH inductor with polysilicon PGS on the tank quality factor, QTank. The tuning capacitance for the shielded and un-shielded cases are 0.5 pF and 0.7 pF, respectively, to account for the difference in inductors parasitic capacitance. As mentioned in Section II-A, QTank 1.50 PGS fo 1.25 Q Tank = -------NGS (11 -cm) BW Impedance Magnitude (k) 1.00 0.75 0.50 0.25 0
1.0
1.5
2.0 Frequency (GHz)
2.5
3.0
Figure 4.13: Effect of polysilicon patterned ground shield on Q of a 2-GHz LC tank.
92
can be determined by ratio of the resonant frequency, at which the tank impedance is maximum, to the 3-dB bandwidth. Even though the parasitic capacitance of both inductors are incorporated as part of the tank capacitance, the tank with the un-shielded inductor suffers from a lossy Rp. As a result, QTank is improved from 6.0 to 10.2 when a shield is used under the inductor. It is important to note that maximum QTank exceeds the maximum inductor Q for both cases (see Table 4.1). This can be attributed to the fact that the reduction of the inductors Q caused by their parasitic capacitances become irrelevant as the capacitances are absorbed by the LC tanks as discussed in Section 4.1.1.
4.2.5 Suppression of Substrate Noise Coupling

Substrate noise coupling between two adjacent inductors is measured by the magnitude of the transmission coefficient, |S21|. During the measurements, the substrate is grounded to study realistic scenario in RF ICs. Figure 4.14 shows that for the un-shielded inductors, -40 PGS NGS (19 -cm) NGS (11 -cm) Probes up
-50
|S21| (dB)
-60
-70
-80
-90 0.1 1 10 Frequency (GHz) Figure 4.14: Effect of polysilicon patterned ground shield on substrate coupling between two adjacent inductors.
4.3. Summary
93
the one on a more conductive substrate (11 -cm) has stronger coupling due to the higher substrate admittance. The peaks in |S21| for the NGS cases correspond to the onset of significant electric field penetration into the silicon substrate, and hence more coupling through the substrate. In contrast, the inductors shielded by the polysilicon PGSs show signicantly better isolation, up to 25 dB improvement, at gigahertz frequencies. It should be noted that like any other isolation structure, such as a guard ring, the efficiency of the PGS is highly dependent on the integrity of the ground connection. Designers often need to make a trade-off between the desired isolation level and the chip area that is required for a low-impedance ground.
4.3 Summary
On-chip spiral inductors with patterned ground shields are presented. The parasitic effects of an inductor on silicon are analyzed with the aid of a physical model. A patterned ground shield is devised to eliminate the silicon parasitics of the on-chip spiral inductor. The effects of shield resistance and pattern are studied both theoretically and experimentally. Measurement results confirmed that a patterned ground shield improves Q and isolation of an on-chip inductor. Furthermore, with the addition of the ground shield, an inductors characteristics are less dependent on substrate variation and hence are easier to model. The implementation of the ground shield is compatible with standard silicon IC technology. The experimental results presented in this chapter are exclusively based on lightly-doped (1020 -cm) substrates. Given the increasing interest in CMOS RF ICs, the effectiveness of the patterned ground shields on heavily-doped (1020 m-cm) substrates will be discussed in the next chapter.
94
Chapter
Effects of Epitaxial and Lightly Doped Substrates
Based on measured results, this chapter presents an extensive study of substrate effects on RF passive components with an emphasis on spiral inductors. The results facilitate the integration of passive components on epitaxial (epi) and lightly doped substrates for silicon-based RF ICs. There is growing interest in CMOS RF ICs because CMOS offers low-cost production and the potential of integrating RF and base-band circuits. Epi substrates are routinely employed in CMOS logic and ASIC processes while lightly doped (130 -cm) substrates are commonly used in bipolar or BiCMOS processes and CMOS memory technologies. Epi substrates are comprised of a lightly doped (130 -cm) epitaxial layer grown on a degenerately doped (1020 m-cm) bulk substrate. The heavily doped silicon bulk provides immunity to latch and enhances defect gettering. Although numerous results for inductors on silicon have been reported, most of them are limited to lightly doped substrates. Furthermore, it is generally believed that the highly conductive bulk of epi substrates cause more loss. The goal of this work is to investigate the substrate effects and thus improve the performance of on-chip passive components. This chapter begins with an interfacial charge model that describes the substrate parasitics. Then, measured results of bond pads and spiral inductors on different substrates are presented. The study shows that substrate parasitic capacitance is significantly larger for epi substrates. However, the results also reveal that epi substrates are actually less lossy than lightly doped cases, which is counter-intuitive to the common perception. For spiral
95
96
Chapter 5: Effects of Epitaxial and Lightly Doped Substrates
inductors, substrate eddy current are proven to be negligible even in epi wafers. Inductors on epi substrates with and without patterned ground shields are measured. Experimental data show an increase of 15% in inductor Q at 1.5 GHz and an improvement of 400% in resonator Q at 3.75 GHz with the introduction of the patterned ground shields. Furthermore, it is shown that patterned ground shields implemented using MOSFET gate polysilicon or source/drain diffusion layers achieve similar improvement in Q.
5.1 Theory and Simulation

On-chip passive components are realized using interconnect layers which are insulated from the semiconducting silicon by oxide. Therefore, the substrate parasitics can be represented by a generic SiO 2 -Si system such as the one shown in Figure 5.1(a). The characteristics of a SiO2-Si system can be explained using a parallel-plate capacitor model with both SiO 2 and Si as dielectric slabs [60][77]. When an ac voltage is applied, a time-varying electric field is established across the capacitor. Under the influence of the electric field, the majority carriers in the silicon form a layer of surface charge at the oxide-silicon interface. The relaxation time constant of this interfacial charge density, s, can be determined by solving the following eld equations: s = Si E Si ox E ox , s t = J Si = Si E Si , and t ox E ox + t Si E Si = V , which yield ox t re s = ------- V e 1 t ox where (5.4) (5.3) (5.1) (5.2)
5.1. Theory and Simulation
97
Oxide (ox) interfacial charge (s)
Eox
tox
Vox
+ V
ESi Silicon (Si, Si)
tSi
VSi
(a) ox C ox = ------t ox Si G Si = ------t Si Si C Si = -----t Si
(b)
Figure 5.1: (a) A parallel-plate capacitor with SiO2 and Si as dielectric slabs. (b) A equivalent circuit model for the SiO2-Si system.
Si + ox ( t Si t ox ) re = ------------------------------------------. Si
(5.5)
The value of re governs whether or not the majority carriers can follow the time-varying electric field instantaneously. If re is small compared to the period of the time-varying electric eld, then the silicon acts as a potent supply of charge and therefore terminates the electric eld at the SiO2-Si interface. The SiO 2 -Si system can also be modeled by the equivalent circuit shown in Figure 5.1(b). The transient behavior of s can be obtained using the following circuit equations:
98
s = C Si V Si C ox V ox , d d - V ox = G Si V Si + C Si ----V , C ox ---dt dt Si and V ox + V Si = V , which yield

t re s = C ox V e 1
(5.6) (5.7)
(5.8)
(5.9)
where C Si + C ox Si + ox ( t Si t ox ) - = ------------------------------------------. re = ----------------------G Si Si This is the same result as in (5.5) as expected. For conventional ICs, the silicon substrate thickness is about 500 m whereas the oxide thickness varies between 26 m. As a result, re is usually much greater than the dielectric relaxation time constant of silicon (Si = Si/ Si) due to the large ratio of tSi to tox. It is worthwhile to mention that the transient behavior of s is the physical origin of the slow-wave phenomena for microstrip structures on SiO2-Si [61]. The relaxation frequency, fre, associated with s is dened as 1 f re = ------------. 2 re (5.11) (5.10)
For instance, a lightly doped silicon wafer with resistivity of 10 -cm, tSi = 500 m, and tox = 4 m, re and fre are 450 ps and 350 MHz, respectively. This implies that the interfacial charge can only track signals not exceeding a couple hundred mega-hertz. For passive components, fre marks the frequency limit above which the substrate parasitics becomes signicant and must be considered in the equivalent model. For the heavily doped bulk of an epi wafer with resistivity of 10 m-cm and the same oxide and silicon thickness, re decreases to 450 fs and fre increases to 350 GHz. This indicates that the bulk parasitics can
5.1. Theory and Simulation
99
be neglected for signals up to a couple hundred gigahertz. However, the thin lightly doped epi layer causes the substrate effects to appear at much lower frequencies. To verify the interfacial charge theory, a MOS structure is simulated using the Maxwell software. The metal width is 16 m. The oxide and silicon substrate thickness is 1 m and 500 m, respectively. Three substrate resistivity values are simulated: 20, 0.1, and 0.01 -cm. The simulation results for the equivalent substrate parallel capacitance (Cp) and resistance (Rp) are plotted in Figure 5.2. Below 100 MHz, Cp is equal to the oxide layer capacitance. For the lightly doped case (20 ohm-cm), Cp start to decreases as frequency is increased above 300 MHz. This indicates that the electric eld begins to penetrate into the silicon substrate as the interfacial charge can no longer track the high-frequency electric eld. The above analysis is incomplete because it only describes the behavior of the substrate in response to a time-varying electric eld. But it provides no information about the potential magnetic coupling between the metal feature and the underlying silicon substrate. The magnetic coupling is important for on-chip inductors. On-chip magnetic parasitic effects are difficult to model analytically because the substrate behave as a volume ground plane with a finite conductivity. In order for the substrate to noticeably interfere with the time-varying magnetic eld, the substrate must have sufcient carriers to oppose the time-varying magnetic eld in accordance to the Lenzs Law. Recently, results based on FASTHENRY simulation showed that even for heavily doped substrate with doping concentration of 1019 cm-3 (resistivity 6 m-cm), inductive coupling with the substrate is negligible up to 20 GHz [78]. And for a lightly doped substrate with 1017 cm-3 doping (resistivity 0.1 -cm), the frequency limit extends to as high as 100 GHz. Furthermore, our experimental results on the solid polysilicon ground shield, as described in Chapter 4, supports these simulations. This suggests that the substrate eddy current is probably insignificant even for epi substrates. To verify this, a set of spiral inductors on glass, lightly doped, and epi substrates are fabricated and measured. The results will be presented in the next section.
100
10-9
Cp (F/m)
10-10 20 -cm 0.1 -cm 0.01 -cm 10-11 0.01
0.10 1.00 Frequency (GHz) (a)
10.00
1e+07
1e+05 Rp (/m)
20 -cm 0.1 -cm 0.01 -cm
1e+03
1e+01
1e-01 0.01
0.10 1.00 Frequency (GHz) (b)
10.00
Figure 5.2: Simulation results of (a) Cp and (b) Rp for a MOS structure with 16-m wide metal on 1 m thick oxide and 500 m thick silicon.
5.2. Experimental Results
101
5.2 Experimental Results

5.2.1 Bond Pads
To investigate capacitive substrate effects, bond pads are fabricated on epi, lightly doped, and quartz (r = 3.9) wafers. Description of the substrate profile under the pads are listed in Table 5.1. S 11 are measured using an HP8720B Network Analyzer and coplanar ground-signal-ground probe. During measurements, the wafer backsides are grounded through the testing chuck. S11 are converted to Y11 from which pad capacitance (Cpad), resistance (Rpad), and quality factor (Qpad) are extracted using the following relationships: Im [ Y 11 ] C pad = -------------------- , 1 R pad = -------------------- , Re [ Y 11 ] and Im [ Y 11 ] Q pad = -------------------Re [ Y 11 ] = R pC p where is the angular frequency. (5.12)
(5.13)
(5.14)
Table 5.1: Pad Epi4.1m Ld4.5m Ld5.5m Ld6.5m Qz2.1m
Summary of 100 100 m2 bond pads. Capacitance at 175 MHz 114.3 fF 100.0 fF 79.9 fF 67.2 fF 5.0 fF Substrate Profile 4.1 m oxide on epi on p+ Si 4.5 m oxide on 10 -cm Si 5.5 m oxide on 10 -cm Si 6.5 m oxide on 10 -cm Si 2.1 m oxide on quartz
102
The frequency behavior of Cpad and Rpad is plotted in Figure 5.3 . Cpad and Rpad are in parallel with each other. In the quartz case, C p a d is approximately 6 fF and is frequency-independent since the electric field penetrates through the entire substrate. In contrast, the silicon samples show strong frequency dependence. At low frequencies, Cpad is equal to the oxide capacitance. As frequency increases, Cpad decreases and finally approaches the high-frequency limit of CSi. The relaxation frequency, fre, is seen to range from 300 to 600 MHz depending on the oxide thickness, which are consistent with the predictions based on the interfacial charge theory. Above 1 GHz, Cpad of the epi sample begins to decrease from the oxide capacitance as the electric field penetrates into the epi layer. Cpad of the epi sample is larger than the lightly doped cases because the epi layer is only 7 m thick and the electric field is terminated at the interface of the epi layer and bulk. Figure 5.3(b) shows that Rpad decreases with frequency indicating that there is more energy loss to the substrate as frequency increases. The quartz sample has much higher Rpad than the silicon samples because it does not support the flow of conductor current to ow. The quality factor of the pad capacitance, Qpad, is a measure of energy loss in the substrate, that is high Q represents low loss. The measured results are plotted in Figure 5.4. The insulating quartz substrate has signicantly higher Qpad compared to the semiconducting silicon substrates. Comparing the lightly doped substrates which have 4.5, 5.5, and 6.5-m oxide, it shows that Qpad is larger with thicker oxide since the lossy silicon is further away from the pad. On the other hand, Qpad on the epi substrate is the highest among all the silicon samples even though it has the thinnest oxide (4.1 m). This indicates that epi substrate is much less lossy compared to lightly doped substrates. While it seems counter-intuitive, this observation is actually consistent with the interfacial charge theory. The p+ bulk behaves as a ground for the electric eld up to a couple hundred gigahertz and therefore dissipates little energy. Therefore, the electric field can only penetrate into the resistive epi layer. Since the epitaxial layer is thin with typical thickness of 310 m, the lossy volume is considerably smaller than the lightly doped bulk substrates.
103
140 120 Cpad = (Im[Y11])/ (fF) 100 80 60 40 20 0 0.1 1 Frequency (GHz) (a) 10 Epi4.1m Ld4.5m Ld5.5m Ld6.5m Qz2.1m
1000
Rpad = 1/(Re[Y11]) (k)
100
10
Epi4.1m Ld4.5m Ld5.5m Ld6.5m Qz2.1m 0.1 1 Frequency (GHz) (b) 10
0.1
Figure 5.3: Frequency response of (a) Cpad and (b) Rpad for metal pads on various substrates (see Table 5.1).
104
30
10 Qpad
Epi4.1m Ld4.5m Ld5.5m Ld6.5m Qz2.1m 1 0.1 1 Frequency (GHz) 10
Figure 5.4: Frequency response of Q for the metal pads.
5.2.2 Spiral Inductors

Spiral inductors are fabricated on epi, lightly doped, and quartz wafers to investigate potential inductive coupling with substrates. The quartz sample serves as a control since no substrate eddy current can be induced in the dielectric. The inductor Gp8nH is fabricated with a 0.32-/sq. aluminum solid ground plane (SGP) underneath the spiral to deliberately create the image current. By comparing the inductors on epi substrate to the ones on quartz and SGP, one can evaluate the significance of the substrate eddy current. Moreover, the GP sheet resistance is adjusted to be similar to that of the p+ bulk for the epi substrate. This allows a direct measure of the magnetic interference caused by the p+ volume ground. Detailed descriptions of the inductors are summarized in Table 5.2 including measured spiral inductance at 175 MHz and resistance at dc. For comparison purposes, the inductors are designed to have similar L/R ratio of about 1.6. Inductance, parasitic resis-
105
tances and capacitances, and Q are extracted from measured two-port S parameters using the techniques described in Chapter 3.
Table 5.2: Inductor Epi5nH Epi10nH Ld8nH Gp8nH Qz8nH Inductance at 175 MHz 5.3 nH 10.5 nH 8.1 nH 7.9 nH 7.9 nH
Summary of spiral inductors. Substrate Profile 4.1 m oxide on epi on p+ Si 4.1 m oxide on epi on p+ Si 5.6 m oxide on 19 -cm Si 5.2 m oxide on ground plane 2.1 m oxide on quartz
Resistance at dc 3.0 7.0 5.0 5.0 5.0
The measured series inductance and resistance are shown in Figure 5.5 . Both the interconnect resistance and substrate resistance resulting from induced image current contribute to the series resistance as discussed in Section 4.1.3. The same spiral layout and metal thickness are used for Ld8nH, Gp8nH, and Qz8nH to produce equal interconnect resistance. As shown in Figure 5.5, Ld8nH and Qz8nH have the same series inductance and resistance indicating that the substrate resistance due to inductive coupling is insignificant for the 19--cm lightly doped substrate. In contrast, Gp8nH exhibits much lower inductance and higher resistance owing to the image current flowing in the SGP. For the inductors on epi substrates, Epi5nH and Epi10nH manifest the same kind of inductance and resistance frequency behavior as Ld8nH and Qz8nH, proving that inductive coupling with the epi substrate is indeed insignificant up to 10 GHz. Although the p+ bulk has sheet resistance close to that of the SGP in Gp8nH, it does not allow noticeable image currents to be induced. This can be attributed to the fact that the carriers in the p+ bulk are distributed over a much larger volume and hence are effectively much farther away from the spiral.
106
12 10 Series Inductance (nH) 8 6 4 2 0 0.1 1 Frequency (GHz) (a) 10 Epi5nH Epi10nH Ld8nH Gp8nH Qz8nH
100 Epi5nH Epi10nH Ld8nH Gp8nH Qz8nH 10
Series Resistance ()
0.1
10
Figure 5.5: Measured results of (a) series inductance and (b) series resistance for the inductors listed in Table 5.2.
107
30 Epi5nH Epi10nH Ld8nH Gp8nH Qz8nH
10 Q 1 0.1
1 Frequency (GHz)
10
Figure 5.6: Frequency response of Q for the inductors.
In Figure 5.6, measured inductor Q are plotted. Qz8nH has the highest Q because it has the lowest substrate loss and the smallest capacitance. Gp8nH has the worst Q due to the severe inductive coupling which resulted in decrease in inductance and increase in resistance. Epi5nH and Epi10nH have much lower self-resonant frequency (srf) compared to Ld8nH. This is because the epi substrate has a much larger substrate capacitance (Cp). To confirm this, Figure 5.7 shows that for the lightly doped substrate, at 12 GHz, Cp decreases to 3040% of its low-frequency value whereas for the epi substrate, Cp only reduces to 65% of its low-frequency value. To understand the degradation mechanism for inductors on epi substrate, substrate loss and self-resonance need to be considered (see Chapter 4). Figure 5.8 shows that Epi5nH and Ld8nH have the same Ls/Rs. In Figure 5.9, it shows that the substrate loss factor is also the same but the self-resonance factor for Epi5nH is considerably smaller than that
108
1.0 0.8 0.6 0.4 0.2 0 0.1 1 Frequency (GHz) 10
Cp /Cp at 175 MHz
Epi5nH (Cp = 445.6 fF at 175 MHz) Ld8nH (Cp = 219.2 fF at 175 MHz)
Figure 5.7: Comparison of substrate parasitic capacitance for inductors on epi and lightly doped substrate.
Epi5nH Ld8nH 10 Ls/Rs 1 0.1
1 Frequency (GHz)
10
Figure 5.8: Ls/Rs for Epi5nH and Ld8nH.
109
1.0 Substrate Loss Factor 0.8 0.6 0.4 Epi5nH 0.2 0 0.1 1 Frequency (GHz) (a) 1.0 Self-resonance Factor 0.8 0.6 0.4 0.2 0 Epi5nH Ld8nH 0.1 1 Frequency (GHz) (b) Figure 5.9: Substrate loss and self-resonance factors for Epi5nH and Ld8nH. 10 10 Ld8nH
110
for Ld8nH. This is an important observation because it proves that inductors on epi substrate have lower Q at high frequencies than on the lightly doped substrate not because of substrate eddy current, but rather due to the larger epi parasitic capacitance. Although substrate loss due to magnetic coupling is insignicant, loss in the epi layer caused by electric field penetration is present. However, the electric loss can easily be eliminated by using the patterned ground shield. To confirm this, Epi5nH is fabricated with a patterned ground shield as described in Chapter 4. It was shown that polysilicon PGS offers the most improvement. In this experiment, PGSs implemented using gate polysilicon and source/drain p+ diffusion layers are fabricated in a standard 0.5-m CMOS process. As shown in Figure 5.10, the inductor Q is improved by about 15% with both polysilicon and p+ diffusion PGS. As suggested in [34], another technique for evaluating the inductor quality is by measuring the inductor impedance near srf and taking the ratio of srf to 3-dB bandwidth. This technique essen8 Epi5nH (Diff. PGS) Epi5nH (Poly. PGS) Epi5nH
0 0.1 1 Frequency (GHz) 10
Figure 5.10: Frequency response of Q for Epi5nH with and without PGS. Diffusion and polysilicon PGS are considered.
5.3. Summary
111
1500.0 srf Q = ---------------------3-dB BW Epi5nH (Diff. PGS) Epi5nH (Poly. PGS) Epi5nH
1200.0
900.0 |Z| 600.0 300.0
0.0 2.0 3.0 4.0 Frequency (GHz) 5.0 6.0
Figure 5.11: Resonator Q of Epi5nH with and without PGS. Diffusion and polysilicon PGS are considered. tially treats the inductor as a resonator and measures the resonator Q. The measured results are shown in Figure 5.11 . The inductor impedance, Z, is maximum at srf. All three cases have a srf of 3.8 GHz. The un-shielded Epi5nH has a resonator Q of about 3. With the PGS, Q is improved to more than 12. The inductor with diffusion PGS has slightly higher srf than the one with polysilicon PGS because the oxide between the spiral metal and the diffusion layer is slightly thicker than that between the spiral metal and the polysilicon. This is consistent with the extracted parasitic capacitances as shown in Figure 5.12 .
5.3 Summary
Effects of epi and lightly doped substrates on passive components are investigated. The results demonstrate that the energy dissipation, which degrades Q, occurs throughout the
112
500 400 Cp (fF) 300 200 100 0 0.1 1.0 Frequency (GHz) 10.0 Epi5nH (Diff. PGS) Epi5nH (Poly. PGS) Epi5nH
Figure 5.12: Substrate parasitic capacitance of Epi5nH with and without PGS. Diffusion and polysilicon PGS are considered. entire bulk for lightly doped substrates but only in the epi layer for epi substrates. It is shown that epi substrates have larger substrate capacitances then the lightly doped substrates as the electric eld penetration is conned to the thin epi layer. For spiral inductors, substrate eddy currents are proven to be negligible even in epi substrates. It is shown that the high-frequency roll-off of Q for inductors on epi substrates is caused by self-resonance. Furthermore, the substrate loss is only due to electric coupling. As a result, the PGS is equally effective on epi substrates and is able to improve inductor Q by 15% and the resonator Q by a factor of 4. Moreover, measured results also show that a p+ diffusion layer is as effective as a polysilicon layer for implementing PGS. However, the effectiveness of the p+ diffusion layer in reducing substrate coupling is yet to be evaluated.
Chapter
6
6.1 Summary
Conclusions
The wireless communication market has experienced tremendous growth in recent years. It is projected to expand at an even faster pace during the next decade with new spectrum allocated for increasing applications. Portable electronic appliances will become an integral part of the overall communication infrastructure in the 21st century. The low-power, low-cost, and small-form-factor requirements for future radio-frequency (RF) systems continue to motivate innovations at the levels of system, circuit, device, and fabrication. One of the characteristics of RF systems is the relatively large ratio of passive components to active devices. In particular, inductors are indispensable to achieve many RF circuit functions and are especially important for low power operation. For low cost production, it is advantageous to utilize the ever-improving high-volume silicon integrated circuit (IC) technologies to implement as many circuit functions as possible. Therefore, it is desirable to integrate inductors and other passive elements on chip for the next generation RF systems. In addition, reducing the number of off-chip passive components can significantly reduce the printed circuit broad area, which leads to smaller form factor for the final product. In Chapter 2, different approaches for inductor integration are studied. It was shown that active inductors are impractical due to the extra power consumption, inferior noise properties, and limited dynamic range. Bond wire inductors offer high Q, but their inductance are difficult to predict and control due to the wire curvature. Moreover, bond wire inductors have large unwanted mutual coupling and poor matching properties. The attain-
113
114
Chapter 6: Conclusions
able inductance is limited by the chip size. Spiral inductors are the most practical and common choice for RF ICs. The most challenging problem associated with on-chip inductor is modeling and characterization. Chapter 3 presented a physical model which accounts for the important parasitic effects in an on-chip inductor. Using this model, the impact of technology and layout parameters on inductor performance are addressed. Contour plots of Q are presented as an effective design tool for optimizing inductor layout. Patterned ground shields (PGS) are introduced in Chapter 4 to eliminate substrate loss due to the electric eld penetration into the silicon substrate at high frequencies. The fundamental definitions of inductor Q and resonator Q are elucidated. The design criteria for PGS are explained in detail. The improvement in Q and substrate noise coupling are presented. Based on experimental and simulation results, Chapter 5 presented a study of the substrate effects on RF passive components with an emphasis on spiral inductors. The results show that lightly doped substrates are actually more lossy than epi substrates. This is counter-intuitive to the general belief that higher substrate conductivity mean more loss and lower Q. The analysis also demonstrates that epi substrates have significantly greater substrate parasitic capacitance in comparison to lightly doped substrates. Substrate eddy currents induced by an on-chip inductor is proven to be negligible even in epi substrates. The effectiveness of patterned ground shields for inductors on epi substrate is established with measured data.
6.2 Future Work

6.2.1 Improvement in Q
Todays multi-level interconnect technology typically has three to four layers of 0.51 m thick metal and a total oxide thickness of about 45 m. Therefore, inductor Q is often limited to 10. Such performance level is adequate for many RF functions. However, for
6.2. Future Work
115
circuits such as narrow-band bandpass filters and low-phase-noise voltage-controlled oscillators, inductor Q in the range of 50100 is needed. One approach to attain high Q values is to use thick metals and dielectrics on the orders of tens and hundreds of micro-meters. These layers can be added on top of the finished standard wafers through post-processing steps similar to those described in [38]. The key challenges include yield, thermal budget, and processing cost. New materials and processing techniques maybe required to fulfill these stringent requirements. Due to the large potential improvement, active research are being conducted in this area [79].
6.2.2 On-Chip Transformers and Baluns

Transformers are often used in RF designs for impedance matching and other functions [80][81]. Balanced-to-unbalanceds, or baluns are useful for conversion between differential and single-ended signals [80][82]. In order for transformers and baluns to become standard IC components, they must have accurate models. The physical inductor model developed in this work can be expanded into transformer and balun models. Since the physical phenomena such as skin effects, mutual coupling, substrate loss, and self-resonance are common to inductors, transformers, and baluns, only a few modifications are required to convert the inductor model into a transformer or balun model. However, validation and optimization of the new models will demand more effort in terms of layout design and parameter extraction technique. Moreover, on-chip inductive components will continue to benet from the usage of patterned ground shields.
6.2.3 On-Chip Tunable Bandpass Filters

High-Q tunable bandpass filters are useful building blocks in a RF front-end system [13]. These filters have traditionally been realized off-chip using dielectric resonators and surface-acoustic-wave devices. With high-Q inductor using advanced processing technology or novel circuit techniques [83] and new devices such as the accumulation-mode MOS varactors [84], on-chip tunable bandpass filters can potentially replace the bulky off-chip parts in a highly integrated RF system.
116
Chapter 6: Conclusions
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Inductor On Chips

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ON-CHIP SPIRAL INDUCTORS FOR SILICON-BASED RADIO-FREQUENCY INTEGRATED CIRCUITS

Chik Patrick Yue July 1998

Copyright by Chik Patrick Yue 1998 All Rights Reserved

3.2 3.3 3.4

3.5 3.6 3.7

Table 1.1: Table 3.1:

Table 4.1: Table 5.1: Table 5.2:

Figure 1.2: Figure 1.3: Figure 1.4:

Figure 2.1: Figure 2.2: Figure 2.3: Figure 2.4:

Figure 2.5: Figure 2.6: Figure 2.7:

Figure 3.15: Figure 3.16: Figure 3.17: Figure 3.18:

Figure 4.1: Figure 4.2: Figure 4.3:

Figure 4.4: Figure 4.5: Figure 4.6:

Figure 4.7: Figure 4.8: Figure 4.9: Figure 4.10:

1.1 Worldwide Wireless Communication Market

Asia Pacic 19 Million 22% Europe 25 Million 29%

North America 38 Million 43%

Asia Pacic 80 Million 27%

North America 125 Million 41%

Europe 75 Million 25%

Year 1996 87 Million Subscribers (a)

Year 2000 300 Million Subscribers (b)

1.2. System on a Chip

1.2 System on a Chip

1.3 The Role of Inductors in RF Designs

1.3. The Role of Inductors in RF Designs

Gain Without L BW = (RC) -1 With L BW = (RC) -1

fcenter= (LC) -1/2

1.4 The Advantages of Integration

1.4. The Advantages of Integration

RF front-end component count. 11 >100 >50 5 12 1 2

Inductor Capacitor Resistor IC Transistor Crystal Filter

1.5. Dissertation Organization

1.5 Dissertation Organization

2.1 Active Inductors

Chapter 2: On-Chip Inductors

i1 -gm1 iin C L eff = -------------------gm 1 gm 2

2.1. Active Inductors

Chapter 2: On-Chip Inductors

2.2 Bond Wire Inductors

2.2. Bond Wire Inductors

2l L self = 2 l ln ---- 0.75 r

Chapter 2: On-Chip Inductors

2.3. Spiral Inductors

2.3 Spiral Inductors

Chapter 2: On-Chip Inductors

Metal Metal Metal

2.3. Spiral Inductors

Chapter 2: On-Chip Inductors

od Figure 2.6: Layout of a 3-turn square spiral inductor.

2.3. Spiral Inductors

Chapter 2: On-Chip Inductors

AA t toxM1-M2 tox Oxide

2.3. Spiral Inductors

Figure 2.8: Scanning electron micrographs of a 7-turn square spiral inductor.

Chapter 2: On-Chip Inductors

Modeling and Characterization

Chapter 3: Modeling and Characterization

3.1 Inductance and Parasitics of a Spiral Inductor

3.1. Inductance and Parasitics of a Spiral Inductor

3.1.1 Series Inductance

Chapter 3: Modeling and Characterization