CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W.

Allison

8051 Timers count up, incrementing the Timers respective count register each time there is a triggering clock pulse. When the count register rolls over from all 1s to all 0s, a Timer Flag bit will be raised to indicate Timer Overflow.
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Once the Timer Flag is set, the programmer must clear it before it can be set again (dont forget this) Once the Timer Flag is set, the Timer does not stop counting, thus the programmer will usually stop the Timer to handle the event (dont forget this) Once a Timer overflows, the programmer must reload the initial start value to begin counting up from (dont forget this) We may configure a timer channel to generate an internal interrupt in the event of the Timer Flag being set. Otherwise, we will have to test for it in the program (e.g. Wait_Timer0: jnb TF0,Wait_Timer0 ;wait for T0 Flag

The triggering clock pulse that causes a timers count register to be incremented comes from one of two sources:
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(1) The 8051s external oscillator frequency 12 (2) A 1 0 transition event (i.e. falling edge) on an external input

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

8051 has two Timers; 8052 has three timers.

Timer 0 and Timer 1 are 16 bits wide Both may be used as (1) timers or (2) event counters
A timer allows program to keep track of elapsed time A counter allows program to count external events
What real-life apps keep count??

Both are configured by Special Function Registers

TCON (88H) Timer CONtrol (control/status for both T1 and T0) TMOD (89H) Timer MODe (mode for both T1 and T0) TH0/TL0 (8CH/8AH) Timer 0 High/Low bytes TH1/TL1 (8DH/8BH) Timer 1 High/Low bytes T2CON (C8H) Timer 2 Control (control/status for only T2) T2MOD (C9H) Timer 2 Mode (mode for only T2) RCAP2(H/L) (CBH/CAH) Timer 2 Reload/Capture bytes TH2/TL2 (CDH/CCH) Timer 2 High/Low bytes
CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

Timer 2, although similar, has special operational modes


Bit 7 6 5 4 3 2 1 0

TMOD (89H) (Timer Mode Control Registernot bit addressable)

Name Gate C/T* M1 M0 Gate C/T* M1 M0
Timer Clock Timer Clock Timer Clock

Timer 1 1 1 1 0 0 0 0

Comments Gate Bit Normally 0; if 1 Timer1 only runs when INT1* = 1 Counter/Timer select ( 0 = Timer / 1 = Counter) Timer Mode 00: 13 bit timer (not used much) 01: 16 bit timer Select 10: 8 bit timer, auto-reload (same) 11: Split mode (same) (same) (same)
Overflow Flag

M0
M1 M2

TLx(8) THx(5) TLx(8) THx(8)

TFx TFx

M3

Timer Clock

TL1(8) TH1(8)
Overflow Flag

TLx(8)
reload

TFx

Timer Clock FOSC 12

TL0(8) TH0(8)

TF0 TF1

THx(8)

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

TCON (88H) (Timer Control Registerbit addressable)

8Fh Comments Timer1 overflow flag. Set by hardware on T1 overflow;

Bit Name Address 7 TF1

clear by software 8051 vectors to Timer ISR

TR1

8Eh

or automatically cleared by hardware when Timer1 run-control, set/cleared by software to turn Timer1 on/off

TF0

8Dh

Timer0 overflow flag. Set by hardware on T0 overflow; clear by software

or automatically cleared by hardware when 80512 vectors to Timer ISR

4 3 2 1 0

TR0 IE1 IT1 IE0 IT0

8Ch 8Bh 8Ah 89h 88h

Timer0 run-control bit, set/cleared by software to turn Timer0 on/off External Interrupt1 edge flag. Set by hardware when a falling edge is
detected on INT1* input; clear by software or automatically cleared by hardware when 8051 vectors to Timer ISR

External Interrupt1 type control, set/cleared by software. (1=detect falling edge, 0=detect low-level) External Interrupt0 edge flag External Interrupt0 type control

Bits 7, 5, 3 and 1 are status flags, bits 6, 4, 2 and 0 are control bits Bits 7, 6, 3 and 2 are for using Timer1 Bits 5, 4, 1 and 0 are for using Timer0

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

C/T* bit in TMOD controls whether it is a timer or a counter

On-chip oscillator Divide By 12
921.6 KHz 1.0 MHz F 12 (1.0851 uSec) (1.0 uSec)

11.0592 12.00 MHz crystal crystal

C/T*=0

T0 or T1 pin P3.4 = T0 P3.5 = T1

One machine cycle S1 P1 Osc. P2 P1 S2 P2 S3 P1 P2 P1 S4 P2 P1 S5 P2

C/T*= 1

Timer Clock
0 is up 1 is down

C/T*

S6 P1 P2 P1

S1

P2

P1

S2

In counter mode (C/T*=1) the external input (T0 or T1) is sampled in S5P2 of every machine cycle. Timer regs are incremented in response to 1-to-0 transition. Since it takes two machine cycles (2 us) to recognize a transition (10) , the maximum external frequency is 500 KHz (assuming 12MHz operation).
CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

When 8051 Timers are used in Timer mode, the incrementing period (Tinc) is 1/(F12)
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Example 1: if F=12 MHz then Tinc = 1 sec. Example 2: if F=11.0592 MHz then Tinc = 1.0851 sec.

Divide the desired delay time needed by Tinc to obtain # increments (Ninc)

Perform 65536 - Ninc (Dinc) Convert Dinc to the 4-digit hexadecimal value in the form yyxx Load TH with yy and TL with xx. TH yy, TL xx
Example: if F=12 MHz, find the Timer value to load to create a 50 ms delay
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Ninc = 50E-3 / 1E-6 = 50,000

Dinc = 65,536 50,000 = 15,536 15,536 0x3CB0; therefore yy=0x3C and xx=0xB0 TH 0x3C; TL 0xB0

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

What are the minimum and maximum delays that we can create ?
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Lets assume the 8051 is operating at 12MHz so Timers can be incremented at 1Mhz (once every sec). Minimum delay is limited not by timer clock frequency but by software.
Example: Write a code segment to create a waveform with the shortest possible period:
clr P2.0 cpl P2.0 sjmp Quick_Loop ;square wave on P2.0 What are the Frequency and ;toggle for hi to lo duty cycle of this waveform? ; and lo to hi sequence

Quick_Loop:

Maximum delays using Timers are based upon the timer register size

8-bit timer: max count is 0 to FFh, thus max overflow occurs after 256 increments 16-bit timer: max count is 0 to FFFFh, thus max overflow occurs after 65536 increments

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Maximum delay for 12MHz 8051 is 65536 sec, or 65.5 msec Maximum delay for 11.0592MHz 8051 is 65536*1.0851 sec = 71.1 msec

As with software delay routines, we can have 16-bit timer sections embedded in software loops to create unlimited delays

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

When TR=1 and Gate = 0

so that Timer1 is enabled to count

these signals are always 1

Block Diagram of Timer 1

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

When TR=1 and Gate = 1

Timer1 will only counts Timer1 When INT1* = 1 not count

this signal will be 0 this signal is only 1 when INT1*goes is deasserted (i.e. 1) when INT1* low (i.e. asserted)

Block Diagram of Timer 1

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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Using the Gate Bit set (i.e. 1) in conjunction with inputs INTx allows the measuring of the duration of external signals (a.k.a pulse measurement)

In this example we measure duration of signal on INT0*

Program Timer 0 to Mode 1 (16-bit timer) TH0/TL0 0000H Gate 1 TR0 1 When INT0* goes HIGH the OR-Gate is high and the count begins in 1 MHz increments (assuming 12MHz oscillator) When INT0* goes LOW the OR-Gate is low, counting will stop, and the count in TH0/TL0 is the number of microseconds that INT0* was asserted. You can program the 8051 to generate an interrupt on the HIGH to LOW transition on INT0* which tells you when to read the count

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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This provides an 8-bit timer (Timers 0 or 1) that will automatically refresh with the initial count upon reaching the terminal count
Timer Clock

TLx(8)
reload

TFx

Mode 2

THx(8)

THx is programmed with the base count

TLx is the timer that will get incremented and will set the TFx bit when TLx overflows When TFx bit is set, the contents of THx is automatically copied to TLx and the counting continues

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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Timer 0 in mode 3 is split into two 8-bit timers

TL0 and TH0 act as separate 8-bit timers with overflow setting the TF0 and TF1 flags respectively
Timer Clock

TH1(8) TL1(8)
Overflow Flags

Timer Clock

TL0(8) TH0(8)

TF0 TF1

Mode 3

Timer 1 is stopped in Mode 3 but can be started by switching it to another mode.

The limitation is that the overflow flag, TF1, will not be affected by Timer1 overflowing. You can use T1 as a serial port BAUD rate generator

Benefit: Mode 3 provides an extra 8-bit timer.

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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1 KHz Square Wave Generation

Use Timer 0

(thus T=1.0 msec = 1000 sec)

Assuming 12 MHz 8051, thus 1 usec increment rate Duty cycle of 50%, therefore 500 sec low-time and 500 sec high-time

16-bit timer mode (delay longer than 256 s so mode 2 cant be used)
65536 - 500 = 65036 = 0xFE0C Thus, TH0 0xFE and TL0 0x0C

Will need to be tuned if an exact output frequency is required

ORG mov mov mov setb jnb clr clr cpl sjmp END 5800H TMOD,#00000001b TH0, #0FEh TL0, #0Ch TR0 TF0,Wait TR0 TF0 P1.0 Loop
;16-bit timer0 mode ;-500 (high byte) ;-500 (low byte) ;start timer ;wait for overflow ;stop the timer ;clear timer overflow flag ;toggle port bit ;repeat

Loop:

Wait:

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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This third timer is only on the 8052 and derivatives

Five SFRs: TL2, TH2, TCON2 and RCAP2L, RCAP2H
TL2, TH2 and TCON2 are used similarly as with timers 0 and 1 RCAP2L and RCAP2H are for 16-bit auto-reload and 16-bit capture modes

TCON2 Register Summary

Bit Name Address 7 TF2 1) 6 EXF2 CEh 5 RCLK CDh 4 TCLK CCh 3 EXEN2 CBh 2 TR2 CAh 1 C/T2 C9h 0 CP/RL2C C8h Comments CFh Timer2 overflow flag. (Not set when TCLK or RCLK = Timer2 external flag. Set on either a reload or capture Timer2 receiver clock. When set, Timer2 provides serial Rx baud clock Timer2 transmit clock. When set, Timer2 provides serial Tx baud clock Timer2 external enable. Enables reload/capture on T2EX falling edge Timer2 run control, set/cleared by software to turn Timer2 on/off Timer2 counter/timer select (1=counter, 0=timer) Timer2 capture/reload flag (1=capture enable, 0=reload enable)

Like TCON, the TCON2 register is bit-addressable

Bits 7 and 6 are status flags, the remaining 6 are control bits

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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Timer 2 in 16-bit Auto-reload mode

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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Timer 2 in 16-bit Capture mode

CSULB -- CECS 285 Chapter Nine Fall 2010 -- R.W. Allison

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