226 Power systems electromagnetic transients simulation

i (t) 1 Interpolation 2 Backward Euler step (half step) 3 Trapezoidal step (normal step)

tZ t 1 2 3 t + t tZ + t/2 tA + t

tZ

tZ+

Figure 9.8

Interpolating to point of switching

iL (t) vL (t)

tS + t tS

Time

Figure 9.9

Jumps in variables

step as the values at tZ + i.e. vL (tZ + ) = vL tZ + iC (tZ + ) = iC t 2

t tZ + 2

(9.10)

Using these values at time point tZ + , the history terms for a normal full step can be calculated by the trapezoidal rule, and a step taken. This procedure results in a shifted time grid (i.e. the time points are not equally spaced) as illustrated in Figure 9.8. PSCAD/EMTDC also interpolates back to the zero crossing, but then takes a full time step using the trapezoidal rule. It then interpolates back on to t + t so as to

Power electronic systems 227

i (t)

t t tZ 1 2 t + t tZ + t 3

Figure 9.10

Double interpolation method (interpolating back to the switching instant)

keep the same time grid, as the post-processing programs expect equally spaced time points. This method is illustrated in Figure 9.10 and is known as double interpolation because it uses two interpolation steps. Interpolation has been discussed so far as a method of removing spikes due, for example, to inductor current chopping. PSCAD/EMTDC also uses interpolation to remove numerical chatter. Chatter manifests itself as a symmetrical oscillation around the true solution; therefore, interpolating back half a time step will give the correct result and simulation can proceed from this point. Voltage across inductors and current in capacitors both exhibit numerical chatter. Figure 9.11 illustrates a case where the inductor current becoming zero coincides with a time point (i.e. there is no current chopping in the inductive circuit). Step 1 is a normal step and step 2 is a half time step interpolation to the true solution for v(t). Step 3 is a normal step and Step 4 is another half time step interpolation to get back on to the same time grid. The two interpolation procedures, to nd the switching instant and chatter removal, are combined into one, as shown in Figure 9.12; this allows the connection of any number of switching devices in any conguration. If the zero crossing occurs in the second half of the time step (not shown in the gure) this procedure has to be slightly modied. A double interpolation is rst performed to return on to the regular time grid (at t + t ) and then a half time step interpolation performed after the next time step (to t + 2 t ) is taken. The extra solution points are kept internal to EMTDC (not written out) so that only equal spaced data points are in the output le. PSCAD/EMTDC invokes the chatter removal algorithm immediately whenever there is a switching operation. Moreover the chatter removal detection looks for oscillation in the slope of the voltages and currents for three time steps and, if detected, implements a half time-step interpolation. This detection is needed, as chatter can be

228 Power systems electromagnetic transients simulation

v (t)

t t t + t t + 2t t + 3 t

4 3 2 1

Figure 9.11

Chatter removal by interpolation

initiated by step changes in current injection or voltage sources in addition to switching actions. The use of interpolation to backtrack to a point of discontinuity has also been adopted in the MicroTran version of EMTP [9]. MicroTran performs two half time steps forward of the backward Euler rule from the point of discontinuity to properly initialise the history terms of all components. The ability to write a FORTRAN dynamic le gives the PSCAD/EMTDC user great exibility and power, however these les are written assuming that they are called at every time step. To maintain compatibility this means that the sources must be interpolated and extrapolated for half time step points, which can produce signicant errors if the sources are changing abruptly. Figure 9.13 illustrates this problem with a step input. Step 1 is a normal step from t + t to t + 2 t , where the user-dened dynamic le is called to update source values at t + 2 t . Step 2, a half-step interpolation, is performed by the chatter removal algorithm. As the user-dened dynamic le is called only at increments the source value at t + t/2 has to be interpolated. Step 3 is a normal time step (from t + t/2 to t + 3 t/2) using the trapezoidal rule. This requires the source values at t + 3 t/2, which is obtained by extrapolation from the known values at t + t to t + 2 t . Step 4 is another half time step interpolation to get back to t + 2 t .

Power electronic systems 229

i (t) 1 Interpolate to zero crossing 2 Normal step forward 3 Interpolate half time step backward 4 Normal step forward 5 Interpolate on to original time grid

tZ t 1 2 v (t) 3 4 5 t + t t + 2t

2 5 t 1 3 t + t 4 t + 2t t

Figure 9.12

Combined zero-crossing and chatter removal by interpolation

The purpose of the methods used so far is to overcome the problem associated with the numerical error in the trapezoidal rule (or any integration rule for that matter). A better approach is to replace numerical integrator substitution by root-matching modelling techniques. As shown in Chapter 5, the root-matching technique does not exhibit chatter, and so a removal process is not required for these components. Rootmatching is always numerically stable and is more efcient numerically than trapezoidal integration. Root-matching can only be formulated with branches containing

230 Power systems electromagnetic transients simulation

Input Extrapolated source values Interpolated source values

Step input

t t t + t t + 2t 4 3 2 User dynamics file called t + t/2 1 t + 3t/2 User dynamics file called t + 3t

Figure 9.13

Interpolated/extrapolated source values due to chatter removal algorithm

two or more elements (i.e. RL, RC , RLC , LC, . . .) but these branches can be intermixed in the same solution with branches solved with other integration techniques.

9.5

HVDC converters

PSCAD/EMTDC provides as a single component a six-pulse valve group, shown in Figure 9.14(a), with its associate PLO (Phase Locked Oscillator) ring control and sequencing logic. Each valve is modelled as an off/on resistance, with forward voltage drop and parallel snubber, as shown in Figure 9.14(b). The combination of onresistance and forward-voltage drop can be viewed as a two-piece linear approximation to the conduction characteristic. The interpolated switching scheme, described in section 9.4.1 (Figure 9.10), is used for each valve. The LDU factorisation scheme used in EMTDC is optimised for the type of conductance matrix found in power systems in the presence of frequently switched elements. The block diagonal structure of the conductance matrix, caused by a travelling-wave transmission line and cable models, is exploited by processing each associated subsystem separately and sequentially. Within each subsystem, nodes to which frequently switched elements are attached are ordered last, so that the matrix refactorisation after switching need only proceed from the switched node to the end. Nodes involving circuit breakers and faults are not ordered last, however, since they

Power electronic systems 231

(a) 1 a b c 4 6 2 Rd + Efwd 3 5 (b) Ron Roff Cd

Figure 9.14

(a) The six-pulse group converter, (b) thyristor and snubber equivalent circuit
Reset at 2 1.2 0 + + + 0.8
0

VA

3 ph

X + +

GP

VB

1.0 S

VC 2 ph

Vb

X Vsin

GI S

Vcos

Figure 9.15

Phase-vector phase-locked oscillator

switch only once or twice in the course of a simulation. This means that the matrix refactorisation time is affected mainly by the total number of switched elements in a subsystem, and not by the total size of the subsystem. Sparse matrix indexing methods are used to process only the non-zero elements in each subsystem. A further speed improvement, and reduction in algorithmic complexity, are achieved by storing the conductance matrix for each subsystem in full form, including the zero elements. This avoids the need for indirect indexing of the conductance matrix elements by means of pointers. Although the user has the option of building up a valve group from individual thyristor components, the use of the complete valve group including sequencing and ring control logic is a better proposition. The ring controller implemented is of the phase-vector type, shown in Figure 9.15, which employs trigonometric identities to operate on an error signal following the phase of the positive sequence component of the commutating voltage. The output of the PLO is a ramp, phase shifted to account for the transformer phase

232 Power systems electromagnetic transients simulation

ra m p

al ve

al ve

ra m p

V al

ve

Firing order

ra

Interpolated firing of valve 1

Interpolated firing of valve 2

Figure 9.16

Firing control for the PSCAD/EMTDC valve group model

Normal operating point IR drop in d.c. line Rectifier characteristic at min

Current error characteristic Inverter characteristic at

min

min

limit

Current margin Current order

Figure 9.17

Classic V I converter control characteristic

shift. A ring occurs for valve 1 when the ramp intersects the instantaneous value of the alpha order from the link controller. Ramps for the other ve valves are obtained by adding increments of 60 degrees to the valve 1 ramp. This process is illustrated in Figure 9.16. As for the six-pulse valve group, where the user has the option of constructing it from discrete component models, HVDC link controls can be modelled by synthesis from simple control blocks or from specic HVDC control blocks. The d.c. link controls provided are a gamma or extinction angle control and current control with voltage-dependent current limits. Power control must be implemented from generalpurpose control blocks. The general extinction angle and current controllers provided with PSCAD readily enable the implementation of the classic V I characteristic for a d.c. link, illustrated in Figure 9.17.

Power electronic systems 233 General controller modelling is made possible by the provision of a large number of control building blocks including integrators with limits, real pole, PI control, second-order complex pole, differential pole, derivative block, delay, limit, timer and ramp. The control blocks are interfaced to the electrical circuit by a variety of metering components and controlled sources. A comprehensive report on the control arrangements, strategies and parameters used in existing HVDC schemes has been prepared by CIGRE WG 14-02 [10]. All these facilities can easily be represented in electromagnetic transient programs.

9.6

Example of HVDC simulation

A useful test system for the simulation of a complete d.c. link is the CIGRE benchmark model [10] (described in Appendix D). This model integrates simple a.c. and d.c. systems, lters, link control, bridge models and a linear transformer model. The benchmark system was entered using the PSCAD/draft software package, as illustrated in Figure 9.18. The controller modelled in Figure 9.19 is of the proportional/integral type in both current and extinction angle control. The test system was rst simulated for 1 s to achieve the steady state, whereupon a snapshot was taken of the system state. Figure 9.20 illustrates selected waveforms of the response to a ve-cycle three-phase fault applied to the inverter commutating bus. The simulation was started from the snapshot taken at the one second point. A clear advantage of starting from snapshots is that many transient simulations, for the purpose of control design, can be initiated from the same steady-state condition.

9.7

FACTS devices

The simulation techniques developed for HVDC systems are also suitable for the FACTS technology. Two approaches are currently used to that effect: the FACTS devices are either modelled from a synthesis of individual power electronic components or by developing a unied model of the complete FACTS device. The former method entails the connection of thyristors or GTOs, phase-locked loop, ring controller and control circuitry into a complicated simulation. By grouping electrical components and ring control into a single model, the latter method is more efcient, simpler to use, and more versatile. Two examples of FACTS applications, using thyristor and turn-off switching devices, are described next.

9.7.1

The static VAr compensator

An early FACTS device, based on conventional thyristor switching technology, is the SVC (Static Var Compensator), consisting of thyristor switched capacitor (TSC) banks and a thyristor controlled reactor (TCR). In terms of modelling, the TCR is the FACTS technology more similar to the six-pulse thyristor bridge. The ring instants are determined by a ring controller acting in accordance with a delay angle

1.671 3.342 3.342 IR1A IR1C IR1B VRC VRB

VRA

A B C NCR NBR

NAR

83.32 0.0136 6.685 83.32 0.0136 6.685 83.32 1.0E6 0.0136 6.685

Com Bus

Com Bus

74.28 .1364 29.76 6.685 261.87 74.28 .1364 29.76 6.685 261.87 74.28 .1364 29.76 6.685 AO KB 261.87 2160.633 0.151 2160.633 2 6

DCRC

DCRMP 6

AM ARD GM

AM ARS GM

GRS

GRD MPV

A 3.737 B 3.737 3.737 C

CMIX

CMRX

MPVX

0.151 AOR 2160.633 GMES 0.151 KB

MPV

Min D E

A 0.7406 B 0.7406 0.7406 C

24.81 0.7406 0.0365 0.0365 TIME

GMID

GMIS

24.81 0.7406 0.0365 0.0365

24.81 0.7406 0.0365 0.0365 AMIS AO KB KB AO GM AM AMID 0.497333 GM AM

167.2 0.0606 13.23 15.04 116.38

167.2 0.0606 13.23 15.04 116.38

DCIMP 4 1

Com Bus

Com Bus

167.2 0.0606 13.23 15.04 116.38

B B #2

B B #2

0.0061 15.04 1.0E6 37.03 0.0061 15.04 37.03 0.0061 15.04 37.03 B A LOGIC FAULT TIMED FAULTS C

A NBI 7.522 7.522 7.522 B NCI C

Figure 9.18
A B C 1.0 1.0 IR1A A Tmva = 603.73 A A 1 VDCRC 3 CMR 5 0.497333 CMI CMR 2.5 DCMP 21.66667 VDCRC VDCIC 2.5 2 CMI 6 VDCIC DCIC A A Tmva = 591.79 A NAI A B C

234 Power systems electromagnetic transients simulation

CIGRE benchmark model as entered into the PSCAD draft software

VRA VRC VRB 1.0 C 345.0 213.4557 C C 4 5 3 1 C C 209.2288 230.0 C #1 B 1.0 B #1 #2 B B 1.0 A Tmva = 603.73 A A 4 1 3 2 5 2 6 4 A A Tmva = 591.79 A AO AOI 5 3 C C 209.2288 230.0 C #1 B KB 1.0 IR1C C 345.0 213.4557 C C IR1B B #1 #2 B B

Arc Cos Lineariser CERRR *

0.63661977 D

CORD TIME 0.1

CMARG

1.0

Figure 9.19
P BETAR + F F Arc Cos D + BETARL I AOR 3.141590 CERRIM I F CNLG P BETAIC PI CERRI D B + F D VDCL E Max BETAI D + AOI DGEI B D + F + GERRI GNLG I P BETAIG GMIN

CMRX

CMRS

G 1 + sT

CMIX

G 1 + sT

CMIS

F +

MPVX

G 1 + sT

MPVS

GMES

Min in 1 Cycle

GMESS

Power electronic systems 235

Controller for the PSCAD/EMTDC simulation of the CIGRE benchmark model

0.26180

236 Power systems electromagnetic transients simulation

2 1.5 p.u. 1 0.5 0 Alpha order @ rectifier 150 120 degs 90 60 30 0 Inverter phase A Volts 1.2 0.8 p.u. 0.4 0 0.4 0.8 1.2 Inverter measured current 2.5 2 p.u. 1.5 1 0.5 0 0 0.1 0.2 0.3 0.4 0.5 Time (s) 0.6 0.7 0.8 0.9 1 Alpha order @ inverter r Rectifier measured current

Figure 9.20

Response of the CIGRE model to ve-cycle three-phase fault at the inverter bus

passed from an external controller. The end of conduction of a thyristor is unknown beforehand, and can be viewed as a similar process to the commutation in a six-pulse converter bridge. PSCAD contains an in-built SVC model which employs the state variable formulation (but not state variable analysis) [3]. The circuit, illustrated in Figure 9.21, encompasses the electrical components of a twelve-pulse TCR, phase-shifting

Power electronic systems 237

Vp1 Ip1 Vp2 Ip2 Vp3 Ip3

Is1

Neutral Is4 Is6 Is5

IL1 Rs
T5 T1 T2 T4

Cs
TCR

T6

L/2

T3

L/2

TSC

C1

Figure 9.21

SVC circuit diagram

transformer banks and up to ten TSC banks. Signals to add or remove a TSC bank, and the TCR ring delay, must be provided from the external general-purpose control system component models. The SVC model includes a phase-locked oscillator and ring controller model. The TSC bank is represented by a single capacitor, and when a bank is switched the capacitance value and initial voltage are adjusted accordingly. This simplication requires that the current-limiting inductor in series with each capacitor should not be explicitly represented. RC snubbers are included with each thyristor. The SVC transformer is modelled as nine mutually coupled windings on a common core, and saturation is represented by an additional current injection obtained from a ux/magnetising current relationship. The ux is determined by integration of the terminal voltage. A total of 21 state variables are required to represent the circuit of Figure 9.21. These are the three currents in the delta-connected SVC secondary winding, two of

238 Power systems electromagnetic transients simulation

Symbol t IL t Dt Description Original EMTDC time step SVC time step Catch-up time step

Switch-OFF occurs tx Time tA t tA1 tA2 tA3 tB

t Dt

Figure 9.22

Thyristor switch-OFF with variable time step

the currents in the ungrounded star-connected secondary, two capacitor voltages in each of the two delta-connected TSCs (four variables) and the capacitor voltage on each of the back-to-back thyristor snubbers (4 3 = 12 state variables). The system matrix must be reformed whenever a thyristor switches. Accurate determination of the switching instants is obtained by employing an integration step length which is a submultiple of that employed in the EMTDC main loop. The detection of switchings proceeds as in Figure 9.22. Initially the step length is the same as that employed in EMTDC. Upon satisfying an inequality that indicates that a switching has occurred, the SVC model steps back a time step and integrates with a smaller time step, until the inequality is satised again. At this point the switching is bracketed by a smaller interval, and the system matrix for the SVC is reformed with the new topology. A catch-up step is then taken to resynchronise the SVC model with EMTDC, and the step length is increased back to the original. The interface between the EMTDC and SVC models is by Norton and Thevenin equivalents as shown in Figure 9.23. The EMTDC network sees the SVC as a current source in parallel with a linearising resistance Rc . The linearising resistance is necessary, since the SVC current injection is calculated by the model on the basis of the terminal voltage at the previous time step. Rc is then an approximation to how the SVC current injection will vary as a function of the terminal voltage value to be calculated at the current time step. The total current owing in this resistance may be

Power electronic systems 239

ISVC (t)

VC (t t) RC

RC V (t) RC

Outside network

SVC model

EMTDC network

Figure 9.23

Interfacing between the SVC model and the EMTDC program

large, and unrelated to the absolute value of current owing into the SVC. A correction offset current is therefore added to the SVC Norton current source to compensate for the current owing in the linearising resistor. This current is calculated using the terminal voltage from the previous time step. The overall effect is that Rc acts as a linearising incremental resistance. Because of this Norton source compensation for Rc , its value need not be particularly accurate, and the transformer zero sequence leakage reactance is used. The EMTDC system is represented in the SVC model by a time-dependent source, for example the phase A voltage is calculated as Va = Va + t (Vc Vb ) 1 ( t)2 3 (9.11)

which has the effect of reducing errors due to the one time-step delay between the SVC model and EMTDC. The ring control of the SVC model is very similar to that implemented in the HVDC six-pulse bridge model. A ring occurs when the elapsed angle derived from a PLO ramp is equal to the instantaneous ring-angle order obtained from the external controller model. The phase locked oscillator is of the phase-vector type illustrated in Figure 9.15. The three-phase to two-phase dq transformation is dened by V = V = 2 Va 3 1 Vb 3 1 Vc 3 (9.12) (9.13)

1 (Vb Vc ) 3

The SVC controller is implemented using general-purpose control components, an example being that of Figure 9.24. This controller is based on that installed at Chateauguay [11]. The signals Ia , Ib , Ic and Va , Vb , Vc are instantaneous current and voltage at the SVC terminals. These are processed to yield the reactive power