SCAN Test

The combinational network is easy to test ; just by applying test vector & observe output. In sequential network such thing is not sufficient ; here one should observe state of all flip-flops which is simplified by brute force approach in which sequential network is divided into combinational network ;but still it is not sufficient because it required much number of test vector ; which take much time for small design. One approach for sequential network would be to connect output of each flip-flops to next flip-flop which form shift register , then we could shift out the state of the flip-flops bit by bit using single serial pin of IC. which known as scan path testing. Each portion of integrated circuit is tested using ATPG technique to detect intraportion faults. But inter- portion faults are detected by SCAN test. In SCAN test there is scan chain containing:1. Memory elements in fan-in of the output of number of portion. 2. Memory elements in fan-out of the input of number of portion. 3. Memory elements connected to combinational logic propagating data input to the memory element. 4. Control signal. ATPG is most simple for combinational but much harder for sequential logic. So most common sequential structured test approach converts sequential logic to combinational logic. In full scan design we replace every sequential element with scan flip-flop. The result is an internal form of boundary scan & we can use IEEE1149.1 TAP to access an internal scan chain. In highly structured full scan allows test software to perform automatic scan insertion using scan design we can turn the output of each flip-flop into a pseudo primary input & input to each flipflop into pseudo primary output. ATPG software can then generate test vectors for the combinational logic between scan flip-flop .

The following figure is showing scan path testing based on two state flip-flop. In the usual way, the sequential network separated into combinational part and state register composed of flip-flop.

In above circuit green path indicating test vector path via shift register. In normal mode (not scan mode) SE(scan enable) is active low; input are applied (1.6) & output (1..2) are generated when clock pulsed network goes to next state. In scan mode (test mode) :1. SE is active high. 2. By using test clock test vector passed via SDI(serial data input).

3. Then allow corresponding test values to input(16). 4. After sufficient time interval signal propagated through combination network then verify the output (1..2) . 5. Then make SE low and apply system clock to store new value( ) into flip-flop. 6. Scan out & verify Q(i) values by using clock; at same time new test vector is inserted via SDI. So generally in digital IC combinational & sequential circuit are separated & in order to scan test to IC , we need to replace flip-flop with two port flip-flop. Digital chip under test is shown below

When multiple ICs are mounted on a pc board ,it is possible to chain together the scan register in each IC so that the entire board can be tested using a single serial access point.