Features

High-performance, Low-power AVR 8-bit Microcontroller Advanced RISC Architecture

133 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers + Peripheral Control Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier Nonvolatile Program and Data Memories 128K Bytes of In-System Reprogrammable Flash Endurance: 1,000 Write/Erase Cycles Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation 4K Bytes EEPROM Endurance: 100,000 Write/Erase Cycles 4K Bytes Internal SRAM Up to 64K Bytes Optional External Memory Space Programming Lock for Software Security SPI Interface for In-System Programming JTAG (IEEE std. 1149.1 Compliant) Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses and Lock Bits through the JTAG Interface Peripheral Features Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes Two Expanded 16-bit Timer/Counters with Separate Prescaler, Compare Mode and Capture Mode Real Time Counter with Separate Oscillator Two 8-bit PWM Channels 6 PWM Channels with Programmable Resolution from 1 to 16 Bits 8-channel, 10-bit ADC 8 Single-ended Channels 7 Differential Channels 2 Differential Channels with Programmable Gain (1x, 10x, 200x) Byte-oriented 2-wire Serial Interface Dual Programmable Serial USARTs Master/Slave SPI Serial Interface Programmable Watchdog Timer with On-chip Oscillator On-chip Analog Comparator Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and Extended Standby Software Selectable Clock Frequency ATmega103 Compatibility Mode Selected by a Fuse Global Pull-up Disable I/O and Packages 53 Programmable I/O Lines 64-lead TQFP Operating Voltages 2.7 - 5.5V (ATmega128L) 4.5 - 5.5V (ATmega128) Speed Grades 0 - 8 MHz (ATmega128L) 0 - 16 MHz (ATmega128)

8-bit Microcontroller with 128K Bytes In-System Programmable Flash ATmega128 ATmega128L Preliminary Summary

Rev. 2467AS-08/01

Note: This is a summary document. A complete document is available on our web site at www.atmel.com .

Pin Configurations

Figure 1. Pinout ATmega128

AVCC GND AREF PF0 (ADC0) PF1 (ADC1) PF2 (ADC2) PF3 (ADC3) PF4 (ADC4/TCK) PF5 (ADC5/TMS) PF6 (ADC6/TDO) PF7 (ADC7/TDI) GND VCC PA0 (AD0) PA1 (AD1) PA2 (AD2)

Overview

The ATmega128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

ATmega128(L)
2467AS08/01

(OC2/OC1C) PB7 TOSC2/PG3 TOSC1/1PG4 RESET VCC GND XTAL2 XTAL1 (SCL/INT0) PD0 (SDA/INT1) PD1 (RXD1/INT2) PD2 (TXD1/INT3) PD3 (IC1) PD4 (XCK1) PD5 (T1) PD6 (T2) PD7

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PEN RXD0/(PDI) PE0 (TXD0/PDO) PE1 (XCK0/AIN0) PE2 (OC3A/AIN1) PE3 (OC3B/INT4) PE4 (OC3C/INT5) PE5 (T3/INT6) PE6 (IC3/INT7) PE7 (SS) PB0 (SCK) PB1 (MOSI) PB2 (MISO) PB3 (OC0) PB4 (OC1A) PB5 (OC1B) PB6

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2(ALE) PC7 (A15) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10) PC1 (A9) PC0 (A8) PG1(RD) PG0(WR)

ATmega128(L)
Block Diagram
Figure 2. Block Diagram

PF0 - PF7

PA0 - PA7

PC0 - PC7

VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS

DATA REGISTER PORTF

DATA DIR. REG. PORTF

DATA REGISTER PORTA

DATA DIR. REG. PORTA

DATA REGISTER PORTC

DATA DIR. REG. PORTC

8-BIT DATA BUS

AVCC AGND AREF PROGRAM COUNTER STACK POINTER WATCHDOG TIMER ADC INTERNAL OSCILLATOR

CALIB. OSC

OSCILLATOR JTAG TAP

OSCILLATOR

ON-CHIP DEBUG

PROGRAM FLASH

SRAM

MCU CONTROL REGISTER

TIMING AND CONTROL

BOUNDARYSCAN

INSTRUCTION REGISTER

GENERAL PURPOSE REGISTERS

X Y Z

TIMER/ COUNTERS

PEN

PROGRAMMING LOGIC

INSTRUCTION DECODER

INTERRUPT UNIT

CONTROL LINES

ALU

EEPROM

STATUS REGISTER

USART0

SPI

USART1

2-WIRE SERIAL INTERFACE

ANALOG COMPARATOR

DATA REGISTER PORTE

DATA DIR. REG. PORTE

DATA REGISTER PORTB

DATA DIR. REG. PORTB

DATA REGISTER PORTD

DATA DIR. REG. PORTD

DATA REG. PORTG

DATA DIR. REG. PORTG

+ -

PORTE DRIVERS

PORTB DRIVERS

PORTD DRIVERS

PORTG DRIVERS

PE0 - PE7

PB0 - PB7

PD0 - PD7

PG0 - PG4

RESET

XTAL1

XTAL2

3
2467AS08/01

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATmega128 provides the following features: 128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 4K bytes EEPROM, 4K bytes SRAM, 53 general-purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible timer/counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with internal oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction Mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main oscillator and the asynchronous timer continue to run. The device is manufactured using Atmels high-density nonvolatile memory technology. The on-chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an on-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

ATmega103 and ATmega128 Compatibility

The ATmega128 is a highly complex microcontroller where the number of I/O locations supersedes the 64 I/O location reserved in the AVR instruction set. To ensure backward compatibility with the ATmega103, all I/O locations present in ATmega103 have the same location in ATmega128. Most additional I/O locations are added in an Extended I/O space starting from $60 to $FF, (i.e., in the ATmega103 internal RAM space). These location can be reached by using LD/LDS/LDD and ST/STS/STD instruction only, not by using IN and OUT instruction. The relocation of the internal RAM space may still be a problem for ATmega103 users. Also, the increased number of interrupt vectors might be a problem if the code uses absolute addresses. To solve these problems, an ATmega103 compatibility mode can be selected by programming the fuse M103C. In this mode, none of the functions in the Extended I/O space are in use, so the internal RAM is located as in ATmega103. Also, the extended interrupt vectors are removed.

ATmega128(L)
2467AS08/01

ATmega128(L)
The ATmega128 is 100% pin compatible with ATmega103, and can replace the ATmega103 on current Printed Circuit Boards. The application note Replacing ATmega103 by ATmega128 describes what the user should be aware of replacing the ATmega103 by an ATmega128. ATmega103 Compatibility Mode By programming the M103C fuse, the ATmega128 will be compatible with the ATmega103 regards to RAM, I/O pins and interrupt vectors as described above. However, some new features in ATmega128 are not available in this compatibility mode, these features are listed below: One USART instead of two, asynchronous mode only. Only the 8 least significant bits of the Baud Rate Register is available. One 16 bits Timer/Counter with 2 compare registers instead of two 16-bit Timer/Counters with 3 compare registers. 2-wire serial interface is not supported. Port G serves alternate functions only (not a general I/O port). Port F serves as digital input only in addition to analog input to the ADC. Boot Loader capabilities is not supported. It is not possible to adjust the frequency of the internal calibrated RC oscillator. The External Memory Interface can not release any Address pins for general I/O, neither configure different wait-states to different External Memory Address sections.

Pin Descriptions
VCC GND Port A (PA7..PA0) Digital supply voltage. Ground. Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega128 as listed on page 68. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATmega128 as listed on page 69. Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

5
2467AS08/01

Port C also serves the functions of special features of the ATmega128 as listed on page 72. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega128 as listed on page 73. Port E (PE7..PE0) Port E is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128 as listed on page 76. Port F (PF7..PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS) and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input Port only. Port G (PG4..PG0) Port G is a 5-bit bidirectional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. In ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32 kHz oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins. RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 19 on page 46. Shorter pulses are not guaranteed to generate a reset. Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

XTAL1

ATmega128(L)
2467AS08/01

ATmega128(L)
XTAL2 AVCC Output from the inverting oscillator amplifier. This is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. This is the analog reference pin for the A/D Converter. This is a programming enable pin for the serial programming mode. By holding this pin low during a power-on reset, the device will enter the serial programming mode. PEN has no function during normal operation.

AREF PEN

7
2467AS08/01

Register Summary
Address
($FF) .. ($9E) ($9D) ($9C) ($9B) ($9A) ($99) ($98) ($97) ($96) ($95) ($94) ($93) ($92) ($91) ($90) ($8F) ($8E) ($8D) ($8C) ($8B) ($8A) ($89) ($88) ($87) ($86) ($85) ($84) ($83) ($82) ($81) ($80) ($7F) ($7E) ($7D) ($7C) ($7B) ($7A) ($79) ($78) ($77) ($76) ($75) ($74) ($73) ($72) ($671 ($70) ($6F) ($6E) ($6D) ($6C) ($6B) ($6A) ($69) ($68) ($67) ($66) ($65) ($64) ($63) ($62)

Name
Reserved Reserved Reserved UCSR1C UDR1 UCSR1A UCSR1B UBRR1L UBRR1H Reserved Reserved UCSR0C Reserved Reserved Reserved Reserved UBRR0H Reserved Reserved Reserved TCCR3C TCCR3A TCCR3B TCNT3H TCNT3L OCR3AH OCR3AL OCR3BH OCR3BL OCR3CH OCR3CL ICR3H ICR3L Reserved Reserved ETIMSK ETIFR Reserved TCCR1C OCR1CH OCR1CL Reserved Reserved Reserved TWCR TWDR TWAR TWSR TWBR OSCCAL Reserved XMCRA XMCRB Reserved EICRA Reserved SPMCSR Reserved Reserved PORTG DDRG PING PORTF

Bit 7
RXC1 RXCIE1 FOC3A COM3A1 ICNC3

Bit 6
UMSEL1 TXC1 TXCIE1 UMSEL0 FOC3B COM3A0 ICES3

Bit 5
UPM11 UDRE1 UDRIE1 UPM01 FOC3C COM3B1 -

Bit 4
UPM10 FE1 RXEN1 UPM00 COM3B0 WGM33

Bit 3
USBS1 DOR1 TXEN1

Bit 2
UCSZ11 UPE1 UCSZ12

Bit 1
UCSZ10 U2X1 RXB81

Bit 0
UCPOL1 MPCM1 TXB81

Page

185 182 183 184 186 186

USART1 I/O Data Register

USART1 Baud Rate Register Low USART1 Baud Rate Register High USBS0 COM3C1 WGM32 UCSZ01 COM3C0 CS32 UCSZ00 WGM31 CS31 UCPOL0 -

185

USART0 Baud Rate Register High WGM30 CS30

186

132 127 130 132 132 133 133 133 133 133 133 134 134

Timer/Counter3 - Counter Register High Byte Timer/Counter3 - Counter Register Low Byte Timer/Counter3 - Output Compare Register A High Byte Timer/Counter3 - Output Compare Register A Low Byte Timer/Counter3 - Output Compare Register B High Byte Timer/Counter3 - Output Compare Register B Low Byte Timer/Counter3 - Output Compare Register C High Byte Timer/Counter3 - Output Compare Register C Low Byte Timer/Counter3 - Input Capture Register High Byte Timer/Counter3 - Input Capture Register Low Byte FOC1A FOC1B TICIE3 ICF3 FOC1C OCIE3A OCF3A OCIE3B OCF3B TOIE3 TOV3 OCIE3C OCF3C OCIE1C OCF1C -

135 136 131 133 133

Timer/Counter1 - Output Compare Register C High Byte Timer/Counter1 - Output Compare Register C Low Byte TWINT TWA6 TWS7 TWEA TWA5 TWS6 TWSTA TWA4 TWS5 TWSTO TWA3 TWS4 TWWC TWA2 TWS3 TWEN TWA1 TWA0 TWPS1 TWIE TWGCE TWPS0

198 199 200 199 197 38

2-wire Serial Interface Data Register

2-wire Serial Interface Bit Rate Register Oscillator Calibration Register XMBK ISC31 SPMIE PORTF7 SRL2 ISC30 RWWSB PORTF6 SRL1 ISC21 PORTF5 SRL0 ISC20 RWWSRE PORTG4 DDG4 PING4 PORTF4 SRW01 ISC11 BLBSET PORTG3 DDG3 PING3 PORTF3 SRW00 XMM2 ISC10 PGWRT PORTG2 DDG2 PING2 PORTF2 SRW11 XMM1 ISC01 PGERS PORTG1 DDG1 PING1 PORTF1 XMM0 ISC00 SPMEN PORTG0 DDG0 PING0 PORTF0 -

29 31 84 270

83 83 83 83

ATmega128(L)
2467AS08/01

ATmega128(L)
Register Summary (Continued)
Address
($61) ($60) $3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($23) $02 ($22)

Name
DDRF Reserved SREG SPH SPL XDIV RAMPZ EICRB EIMSK EIFR TIMSK TIFR MCUCR MCUCSR TCCR0 TCNT0 OCR0 ASSR TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 OCDR WDTCR SFIOR EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR0 UCSR0A UCSR0B UBRR0L ACSR ADMUX ADCSRA ADCH ADCL PORTE DDRE

Bit 7
DDF7 I SP15 SP7 XDIVEN ISC71 INT7 INTF7 OCIE2 OCF2 SRE JTD FOC0

Bit 6
DDF6 T SP14 SP6 XDIV6 ISC70 INT6 INTF6 TOIE2 TOV2 SRW10 WGM00

Bit 5
DDF5 H SP13 SP5 XDIV5 ISC61 INT5 INTF5 TICIE1 ICF1 SE COM01

Bit 4
DDF4 S SP12 SP4 XDIV4 ISC60 INT4 INTF4 OCIE1A OCF1A SM1 JTRF COM00

Bit 3
DDF3 V SP11 SP3 XDIV3 ISC51 INT3 INTF3 OCIE1B OCF1B SM0 WDRF WGM01

Bit 2
DDF2 N SP10 SP2 XDIV2 ISC50 INT2 INTF TOIE1 TOV1 SM2 BORF CS02

Bit 1
DDF1 Z SP9 SP1 XDIV1 ISC41 INT1 INTF1 OCIE0 OCF0 IVSEL EXTRF CS01

Bit 0
DDF0 C SP8 SP0 XDIV0 RAMPZ0 ISC40 INT0 INTF0 TOIE0 TOV0 IVCE PORF CS00

Page
83 9 12 12 39 12 85 86 86 103, 134, 153 103, 136, 154 29, 41, 58 49, 246 98 100 100

Timer/Counter0 (8 Bit) Timer/Counter0 Output Compare Register COM1A1 ICNC1 COM1A0 ICES1 COM1B1 COM1B0 WGM13 AS0 COM1C1 WGM12 TCN0UB COM1C0 CS12 OCR0UB WGM11 CS11 TCR0UB WGM10 CS10

101 127 130 132 132 133 133 133 133 134 134

Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 Timer/Counter2 (8 Bit) Timer/Counter2 Output Compare Register IDRD/ OCDR6 OCDR5 OCDR7 TSM -

151 153 153

OCDR4 WDCE ADHSM -

OCDR3 WDE ACME

OCDR2 WDP2 PUD

OCDR1 WDP1 PSR0

OCDR0 WDP0 PSR321

242 51 67, 104, 139, 237 19 19 20

EEPROM Address Register High

EEPROM Address Register Low Byte EEPROM Data Register PORTA7 DDA7 PINA7 PORTB7 DDB7 PINB7 PORTC7 DDC7 PINC7 PORTD7 DDD7 PIND7 SPI Data Register SPIF SPIE RXC0 RXCIE0 ACD REFS1 ADEN WCOL SPE TXC0 TXCIE0 ACBG REFS0 ADSC DORD UDRE0 UDRIE0 ACO ADLAR ADRF MSTR FE0 RXEN0 ACI MUX4 ADIF CPOL DOR0 TXEN0 ACIE MUX3 ADIE CPHA UPE0 UCSZ02 ACIC MUX2 ADPS2 SPR1 U2X0 RXB80 ACIS1 MUX1 ADPS1 SPI2X SPR0 MPCM0 TXB80 ACIS0 MUX0 ADPS0 PORTA6 DDA6 PINA6 PORTB6 DDB6 PINB6 PORTC6 DDC6 PINC6 PORTD6 DDD6 PIND6 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0

20 81 81 81 81 81 82 82 82 82 82 82 82 163 162 161 182 183 184 186 218 233 235 236 236

USART0 I/O Data Register

USART0 Baud Rate Register Low

ADC Data Register High Byte ADC Data Register Low byte PORTE7 DDE7 PORTE6 DDE6 PORTE5 DDE5 PORTE4 DDE4 PORTE3 DDE3 PORTE2 DDE2 PORTE1 DDE1 PORTE0 DDE0

82 83

9
2467AS08/01

Register Summary (Continued)

Address
$01 ($21) $00 ($20)

Name
PINE PINF

Bit 7
PINE7 PINF7

Bit 6
PINE6 PINF6

Bit 5
PINE5 PINF5

Bit 4
PINE4 PINF4

Bit 3
PINE3 PINF3

Bit 2
PINE2 PINF2

Bit 1
PINE1 PINF1

Bit 0
PINE0 PINF0

Page
83 83

Notes:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written. 2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

10

ATmega128(L)
2467AS08/01

ATmega128(L)
Instruction Set Summary
Mnemonics
ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU RJMP IJMP JMP RCALL ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC Rd,Rr Rd,Rr Rd,Rr Rd,K Rr, b Rr, b P, b P, b s, k s, k k k k k k k k k k k k k k k k k k k k

Operands
Rd, Rr Rd, Rr Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rdl,K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd,K Rd,K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr k

Description
Add two Registers Add with Carry two Registers Add Immediate to Word Subtract two Registers Subtract Constant from Register Subtract with Carry two Registers Subtract with Carry Constant from Reg. Subtract Immediate from Word Logical AND Registers Logical AND Register and Constant Logical OR Registers Logical OR Register and Constant Exclusive OR Registers Ones Complement Twos Complement Set Bit(s) in Register Clear Bit(s) in Register Increment Decrement Test for Zero or Minus Clear Register Set Register Multiply Unsigned Multiply Signed Multiply Signed with Unsigned Fractional Multiply Unsigned Fractional Multiply Signed Fractional Multiply Signed with Unsigned Relative Jump Indirect Jump to (Z) Direct Jump Relative Subroutine Call Indirect Call to (Z) Direct Subroutine Call Subroutine Return Interrupt Return Compare, Skip if Equal Compare Compare with Carry Compare Register with Immediate Skip if Bit in Register Cleared Skip if Bit in Register is Set Skip if Bit in I/O Register Cleared Skip if Bit in I/O Register is Set Branch if Status Flag Set Branch if Status Flag Cleared Branch if Equal Branch if Not Equal Branch if Carry Set Branch if Carry Cleared Branch if Same or Higher Branch if Lower Branch if Minus Branch if Plus Branch if Greater or Equal, Signed Branch if Less Than Zero, Signed Branch if Half Carry Flag Set Branch if Half Carry Flag Cleared Branch if T Flag Set Branch if T Flag Cleared Branch if Overflow Flag is Set Branch if Overflow Flag is Cleared

Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd Rr Rd Rd K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF Rd Rd $00 Rd Rd Rd v K Rd Rd ($FF - K) Rd Rd + 1 Rd Rd 1 Rd Rd Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr R1:R0 Rd x Rr R1:R0 Rd x Rr

Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None Z,C Z,C Z,C Z,C Z,C Z,C None None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None

#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2

ARITHMETIC AND LOGIC INSTRUCTIONS

1 R1:R0 (Rd x Rr) << 1 R1:R0 (Rd x Rr) << 1

PC PC + k + 1 PC Z PC k PC PC + k + 1 PC Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd Rr Rd Rr C Rd K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1

R1:R0 (Rd x Rr) <<

BRANCH INSTRUCTIONS

11
2467AS08/01

Instruction Set Summary (Continued)

Mnemonics
BRIE BRID MOV MOVW LDI LD LD LD LD LD LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM ELPM ELPM ELPM SPM IN OUT PUSH POP SBI CBI LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS Rd, P P, Rr Rr Rd P,b P,b Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b Rd, Z Rd, Z+ Rd, Z Rd, Z+

Operands
k k Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, - X Rd, Y Rd, Y+ Rd, - Y Rd,Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr - X, Rr Y, Rr Y+, Rr - Y, Rr Y+q,Rr Z, Rr Z+, Rr -Z, Rr Z+q,Rr k, Rr

Description
Branch if Interrupt Enabled Branch if Interrupt Disabled Move Between Registers Copy Register Word Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory Load Program Memory Load Program Memory and Post-Inc Extended Load Program Memory Extended Load Program Memory Extended Load Program Memory and Post-Inc Store Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag

Operation
if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1 Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd (Z) Rd (Z), Z Z+1 R0 (RAMPZ:Z) Rd (RAMPZ:Z) Rd (RAMPZ:Z), RAMPZ:Z RAMPZ:Z+1 (Z) R1:R0 Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0

Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S

#Clocks
1/2 1/2 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 3 3 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

DATA TRANSFER INSTRUCTIONS

BIT AND BIT-TEST INSTRUCTIONS

12

ATmega128(L)
2467AS08/01

ATmega128(L)
Instruction Set Summary (Continued)
Mnemonics
SEV CLV SET CLT SEH CLH MCU CONTROL INSTRUCTIONS NOP SLEEP WDR BREAK No Operation Sleep Watchdog Reset Break (see specific descr. for Sleep function) (see specific descr. for WDR/timer) For On-chip Debug Only None None None None 1 1 1 N/A

Operands

Description
Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG

Operation
V1 V0 T1 T0 H1 H0

Flags
V V T T H H

#Clocks
1 1 1 1 1 1

13
2467AS08/01

Ordering Information
Speed (MHz) 8 Power Supply 2.7 - 5.5V Ordering Code ATmega128-8AC ATmega128-8AI 16 4.5 - 5.5V ATmega128-16AC ATmega128-16AI Package 64A 64A 64A 64A Operation Range Commercial (0oC to 70oC) Industrial (-40oC to 85oC) Commercial (0oC to 70oC) Industrial (-40oC to 85oC)

Package Type 64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

14

ATmega128(L)
2467AS08/01

ATmega128(L)
Packaging Information
64A
64-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP), 14x14mm body, 2.0mm footprint, 0.8mm pitch. Dimensions in Millimeters and (Inches)* JEDEC STANDARD MS-026 AEB

16.25(0.640) SQ 15.75(0.620)

PIN 1 ID
PIN 1

0.45(0.018) 0.30(0.012) 0.80(0.0315) BSC

14.10(0.555) SQ 13.90(0.547) 0.20(0.008) 0.09(0.004)

0~7

1.20 (0.047) MAX

0.75(0.030) 0.45(0.018)
*Controlliing dimension: millimeter

0.15(0.006) 0.05(0.002 )

REV. A

04/11/2001

15
2467AS08/01

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2467AS08/01