NXP Semiconductors

74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter

10. Dynamic characteristics

Table 8. Symbol tpd Dynamic characteristics type 74HC193 Parameter propagation delay Conditions Min CPU, CPD to Qn; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPU to TCU; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V CPD to TCD; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL to Qn; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR to Qn; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Dn to Qn; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL to TCU, PL to TCD; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR to TCU, MR to TCD; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
74HC_HCT193

25 C Typ Max
[1]

40 C to +85 C 40 C to +125 C Unit Min Max Min Max

63 23 18 215 43 37 270 54 46 325 65 55 ns ns ns

39 14 11

125 25 21

155 31 26

190 38 32

ns ns ns

39 14 11

125 25 21

155 31 26

190 38 32

ns ns ns

69 25 20

220 44 37

275 55 47

330 66 56

ns ns ns

58 21 17

200 40 34

250 50 43

300 60 51

ns ns ns

69 25 20

210 42 36

265 53 45

315 63 54

ns ns ns

80 29 23

290 58 49

365 73 62

435 87 74

ns ns ns

74 27 22

285 57 48

355 71 60

430 86 73

ns ns ns

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 4 24 June 2013

13 of 30

NXP Semiconductors

74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter

Table 8. Symbol tpd

Dynamic characteristics type 74HC193 continued Parameter propagation delay Conditions Min Dn to TCU, Dn to TCD; see Figure 14 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 29 23 19 7 6 19 7 6 290 58 49 75 15 13 75 15 13 365 73 62 95 19 16 95 19 16 435 87 74 110 22 19 110 22 19 ns ns ns ns ns ns ns ns ns 25 C Typ Max 40 C to +85 C 40 C to +125 C Unit Min Max Min Max

tTHL

HIGH to LOW see Figure 12 output transition VCC = 2.0 V time VCC = 4.5 V VCC = 6.0 V LOW to HIGH see Figure 12 output transition VCC = 2.0 V time VCC = 4.5 V VCC = 6.0 V pulse width CPU, CPD (HIGH or LOW); see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR (HIGH); see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V PL (LOW); see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V

tTLH

tW

100 20 17

22 8 6

125 25 21

150 30 26

ns ns ns

100 20 17

25 9 7

125 25 21

150 30 26

ns ns ns

100 20 17

19 7 6

125 25 21

150 30 26

ns ns ns

trec

recovery time

PL to CPU, CPD; see Figure 11 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR to CPU, CPD; see Figure 12 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 50 10 9 0 0 0 65 13 11 75 15 13 ns ns ns 50 10 9 8 3 2 65 13 11 75 15 13 ns ns ns

74HC_HCT193

All information provided in this document is subject to legal disclaimers.

NXP B.V. 2013. All rights reserved.

Product data sheet

Rev. 4 24 June 2013

14 of 30