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Digital Integrated Circuits Lecture 0: Introduction
Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University cwliu@twins.ee.nctu.edu.tw
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About the Instructor and TA

, ED618, cwliu@twins.ee.nctu.edu.tw , ED412, kcchang@twins.ee.nctu.edu.tw Adapted from D. Harriss notes On-demand () Weste & Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd ed., Addison Wesley, 2005 HW+In-class Activities: 40%, Midterm Exam: 30%, Final Exam: 30%
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Introduction

Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor (CMOS)
Fast, cheap, low power transistors
Today: How to build your own simple CMOS chip, you will learn

CMOS transistors Building logic gates from transistors Transistor layout and fabrication
Rest of the course: How to build a good CMOS chip
Silicon Lattice

Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors
Si-substrate
Dopants

Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si Si Si Si Si Si B Si Si Si Si
+ -
As Si
p-n Junctions
A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction
p-type anode
n-type cathode
nMOS Transistor

Four terminals: gate, source, drain, body Gate oxide body stack looks like a capacitor

Gate and body are conductors SiO2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is Source Gate Drain no longer made of metal
Polysilicon SiO2
n+
Body p
n+ bulk Si
nMOS Operation

nMOS Body is usually tied to ground When the gate is at a low voltage (logical 0) :

P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF
Source Gate Drain Polysilicon SiO2
n+ p
n+ bulk Si
transistor is off
ground
nMOS Operation Cont.
When the gate is at a high voltage (logical 1)

Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON
Source Gate Drain Polysilicon SiO2 1 n+ p n+ S bulk Si D
transistor is on
pMOS Transistor
Similar, but doping and voltages reversed

Body tied to high voltage (VDD) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior
10
Power Supply Voltage

GND = 0 V In 1980s, VDD = 5V VDD has decreased in modern processes

High VDD would damage modern tiny transistors Lower VDD saves power
From generation to generation, VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0,
11
Transistors as Switches
We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain
g=0 d nMOS g s d pMOS g s s s d ON s d OFF s d OFF g=1 d ON
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CMOS Inverter
A 0 1 Y
VDD A Y
GND
CMOS Inverter
A 0 1 Y 0
A=1
VDD OFF
Y=0
ON
A Y
GND
CMOS Inverter
A 0 1 Y 1 0
A=0
VDD ON
Y=1
OFF
A Y
GND
CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y
Parallel; OR;
Y A B
Serial; AND;
16
CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1
ON A=0 B=0
ON Y=1 OFF OFF
17
CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1
OFF A=0 B=1
ON Y=1 OFF ON
18
CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1 1
ON A=1 B=0
OFF Y=1 ON OFF
19
CMOS NAND Gate

A 0 0 1 1 B 0 1 0 1 Y 1 1 1 0
OFF A=1 B=1

( A B)
OFF Y=0 ON ON
20
CMOS NOR Gate

A 0 0 1 1 B 0 1 0 1 Y 1 0 0 0
A B Y
( A + B)
21
3-input NAND Gate
Complementary !!
Y A B C
22
3-input NAND Gate

Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0
Y A B C
A B C
CMOS Fabrication

CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or etched Easiest to understand by viewing both top and crosssection of wafer in a simplified manufacturing process
24
Inverter Cross-section
A
VDD Y
Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors
A GND Y VDD SiO2
GND
n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1
25
Well and Substrate Taps

Substrate must be tied to GND and n-well to VDD Metal to lightly-doped semiconductor forms poor connection called Schottky Diode Use heavily doped well and substrate contacts / taps
A GND Y VDD
p+
n+
n+ p substrate
p+ n well
p+
n+
substrate tap
well tap
26
Inverter Mask Set

A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1
Transistors and wires are defined by masks Cross-section taken along dashed line
GND nMOS transistor substrate tap pMOS transistor well tap
VDD
27
Detailed Mask Views
Six masks

n well
n-well Polysilicon n+ diffusion p+ diffusion Contact Metal
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
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Fabrication Steps

Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

Cover wafer with protective layer of SiO2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO2
p substrate
29
Oxidation
Grow SiO2 on top of Si wafer
900 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
30
Photoresist
Spin on photoresist

Photoresist is a light-sensitive organic polymer Softens where exposed to light
Photoresist SiO2
p substrate
31
Lithography

Expose photoresist through n-well mask Strip off exposed photoresist
n-well mask
Photoresist SiO2
p substrate
32
Etch
Etch oxide with hydrofluoric acid (HF)
Seeps through skin and eats bone; nasty stuff!!!
Only attacks oxide where resist has been exposed
Photoresist SiO2
p substrate
33
Strip Photoresist
Strip off remaining photoresist
Use mixture of acids called piranah etch
Necessary so resist doesnt melt in next step
SiO2
p substrate
34
n-well

n-well is formed with diffusion or ion implantation Diffusion

Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Blast wafer with beam of As ions Ions blocked by SiO2, only enter exposed Si
SiO2 n well
Ion Implantation

35
Strip Oxide

Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps
n well p substrate
36
Polysilicon
Deposit very thin layer of gate oxide
< 20 (6-7 atomic layers) Place wafer in furnace with Silane gas (SiH4) Forms many small crystals called polysilicon Heavily doped to be good conductor
Chemical Vapor Deposition (CVD) of silicon layer

Polysilicon Thin gate oxide n well p substrate
37
Polysilicon Patterning
Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon Thin gate oxide n well p substrate
38
Self-Aligned Process
Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well contact
n well p substrate
39
N-diffusion

Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesnt melt during later processing
n+ Diffusion
n well p substrate
40
N-diffusion cont.

Historically dopants were diffused Usually ion implantation today But regions are still called diffusion
n+
n+ n well p substrate
n+
41
N-diffusion cont.
Strip off oxide to complete patterning step
n+
n+ n well p substrate
n+
42
P-Diffusion
Similar set of steps form p+ diffusion regions for pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+ p substrate
p+ n well
p+
n+
43
Contacts

Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed
Contact
Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+
44
Metalization

Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires
M e ta l
Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+
45
Layout

Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain
Set by minimum width of polysilicon
Feature size improves 30% every 3 years or so Normalize for feature size when describing design rules Express rules in terms of = f/2
E.g. = 0.3 m in 0.6 m process
46
Simplified Design Rules
Conservative rules to get you started
47
Inverter Layout
Transistor dimensions specified as Width / Length

Minimum size is 4 / 2, sometimes called 1 unit In f = 0.6 m process, this is 1.2 m wide, 0.6 m long
48
Summary

MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors Now you know everything necessary to start designing schematics and layout for a simple chip!
49

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Digital Integrated Circuits Lecture 0: Introduction

About the Instructor and TA

Fast, cheap, low power transistors

Rest of the course: How to build a good CMOS chip

nMOS Operation Cont.

When the gate is at a high voltage (logical 1)

Similar, but doping and voltages reversed

Power Supply Voltage

GND = 0 V In 1980s, VDD = 5V VDD has decreased in modern processes

CMOS NAND Gate

CMOS NAND Gate

ON Y=1 OFF OFF

CMOS NAND Gate

OFF A=0 B=1

CMOS NAND Gate

OFF Y=1 ON OFF

CMOS NAND Gate

OFF A=1 B=1

CMOS NOR Gate

3-input NAND Gate

3-input NAND Gate

Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

Well and Substrate Taps

Inverter Mask Set

GND nMOS transistor substrate tap pMOS transistor well tap

Detailed Mask Views

n-well Polysilicon n+ diffusion p+ diffusion Contact Metal

Grow SiO2 on top of Si wafer

900 1200 C with H2O or O2 in oxidation furnace

Photoresist is a light-sensitive organic polymer Softens where exposed to light

Expose photoresist through n-well mask Strip off exposed photoresist

Etch oxide with hydrofluoric acid (HF)

Seeps through skin and eats bone; nasty stuff!!!

Only attacks oxide where resist has been exposed

Strip off remaining photoresist

Use mixture of acids called piranah etch

Necessary so resist doesnt melt in next step

n-well is formed with diffusion or ion implantation Diffusion

Deposit very thin layer of gate oxide

Chemical Vapor Deposition (CVD) of silicon layer

Polysilicon Thin gate oxide n well p substrate

Use same lithography process to pattern polysilicon

Polysilicon Thin gate oxide n well p substrate

Strip off oxide to complete patterning step

Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Metal Thick field oxide p+ n+ n+ p substrate p+ n well p+ n+

Set by minimum width of polysilicon

E.g. = 0.3 m in 0.6 m process

Simplified Design Rules

Conservative rules to get you started

Transistor dimensions specified as Width / Length

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