CASE STUDY: High-Performance ARM Processor Sub-System Implementation

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The Problem Statement

Customer wanted to improve the performance of the existing ARM processor sub-system by 40% which will create a product differentiation and enable the customer to target the device for the high-end smart phone market from the current mid-level smart phone market, thereby extending the life span of the product. The challenge was to meet the performance requirements using the same process technology node, maintain the same area, power grid and the pin-out for the hard-macro as in the existing SoC, for there are no other changes being made to the design. The requirement was that the performance enhanced processor core sub-system will have to be an exact drop-in, to the existing processor core sub-system in the SoC.

How C2SiS Helped

C2SiS team took complete ownership of the Silicon Engineering of the processor core subsystem by thoroughly understanding the performance requirements, different power modes of operation and any specific restrictions in the timing optimization across all process corners. As the area of the macro in the SoC context cannot be changed, C2SiS team worked with the customer engineering team to understand the changes that can be made to the design in order to remove features that are not being used, so as to maintain a similar area after the 40% improvement in the performance of the processor core. C2SiS team worked on the following aspects as part of the physical implementation and tapeout of the design: Reviews of the architecture of the ARM processor sub-system and the data flow Removal of the software debugger block based on the initial synthesis and congestion analysis to maintain the area requirements after the 40% performance improvement Regressions for the modified RTL using the existing test cases Several synthesis trials 26 different synthesis optimizations were tried with different Vt cell usage, PVT (Process-Voltage-Temperature) corners along with uncertainty margins to nail down the final synthesis strategy Extensively analyzed the usage of the library cells in the design and worked with the customers library design team to customize the cells for specific delay requirements Several floorplan trials 22 different floorplan optimizations were tried with different memory locations, placement of logic clusters for better timing and least congestion along with uncertainty margins, appropriate placement blockages for routing channels to nail down the final floorplan for the design Placement through physical clustering and bounds o Manual tweaks to placement along with path based optimization Clock-Tree-Synthesis with appropriate Vt cell usage o Appropriate skewing techniques for better timing optimization o De-cap wrappers for minimizing the dynamic IR drop o Shield routing for the clock networks to minimize the significant cross-talk impact Routing and routing optimization across multiple modes and corners Power analysis and Power grid verification and repair Static and Dynamic Integration into the SoC
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Timing Closure both at the core level and in the context of the SoC Physical Verification and Tape-out

Business Impact
Meeting the Performance Specification: C2SiSs team completed the physical implementation and tape-out of the processor by beating the performance targets set forth for the design. Beating the performance specification of the design, enables the customer to extend the life-span of the product and look at alternate market segments for the same device. First Silicon Success: C2SiS teams flawless design execution by working diligently in understanding the customers sign-off requirements and thoroughly validating every step of the process upfront, enabled the design closure without any bugs in first silicon. TAT Reduction: C2SiS teams extensive know-how of the ARM processor core architecture and the experience in the process technology node being used for the design, helped in managing and successfully taping out the design, a week ahead of the customer planned tapeout date.

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