MSP430

August 18, 2013

MSP430

Outline Ultra low power features and Introduction

Architecture Functions, Interrupts, low power modes Digital input output On chip Peripherals Interfacing

MSP430

Factors contributing to power consumption Power= Vcc Icc

Clock frequency Dynamic power Current leakage Peripherals

MSP430

Ultra low power features

Flexible clock system
ACLK auxillary clock > crystal (32khz) , VLO (12khz) MCLK >main clock (100khz to 25Mhz) SMCLK > sub main clock ( DCO, external clk source)

MSP430

Ultra low power features

Multiple operating modes Need for dierent modes:
1 2

Processor not running Peripherals might be idle

Ultra low power stand by mode Minimum active duty cycle

MSP430

Ultra low power features

Instant wake up Ultra fast wake up of DCO
<1 s , here 204ns Allows CPU to spend more time in LPMs eg: immediate stability of UART

MSP430

Ultra low power features

Zero power BOR

MSP430

Ultra low power features

Other features Intelligent peripherals
1 2

SMCLK Generate PWM signals, takes ADC samples

Low pin leakage <50nA

MSP430

Pin out More than 1 function

Same function on more than 1 pin TCLK,TMS,TDI,TDO,TEST pins JTAG interface SBWTDIO,SBWTCK Spy Bi wire interface A0-,A0+,...A4+,A4- ADC SCLK,SD0,SCL universal serial interface

Figure: Pin-out of the MSP430F2003 and F2013

MSP430 9

Functional Block diagram

MSP430

10

Memory map

MSP430

11

Nomenclature

MSP430

12

Architecture

Central Processing Unit 16 bit RISC CPU

Von Neumann architecture 3 stage instruction pipeline 16 bit ALU, 16 registers 1 R0: Program Counter 2 R1: Stack Pointer 3 R2: Status Register 4 R2/R3: Constant Generator Registers 5 R4 - R15: General Purpose Registers
Figure: MSP430 CPU block diagram
MSP430 13

Architecture
Addressing modes 7 addressing modes for source
4 for destination

MSP430

14

Architecture

Instruction set Orthogonal instruction set 27 core instructions

1 2 3

Double operand Single operand Program ow control

24 emulated instructions Byte, word and address instructions

MSP430

15

Functions and subroutines Functions and Subroutines are lines of code that you use more than once
Functions are used in C ,subroutines used in ALP Local variables are used only when a function is called

MSP430

16

What happens when a subroutine is called? The return address to be pushed on to the stack
The address of the subroutine is then loaded into the PC and

execution continues from there

At the end of the subroutine the ret instruction pops the

return address o the stack into the PC

MSP430

17

Storage of local variables CPU registers are simple and fast

To use a xed location in RAM Disadvantages: The space in RAM is reserved permanently, even when the function is not being called, which is wasteful. The function is not reentrant. To allocate variables on the stack and is generally used when

a program has run out of CPU registers

MSP430

18

Program- example
%Subroutine from substk 0.s43, which now saves and restores R4 correctly ; Subroutine to give delay of R12 *0.1s ; Parameter is passed in R12 and destroyed ; R4 used for loop counter, stacked and restored ----------------------------------------------------------------------DelayTenths: push.w R4 ; Stack R4: will be overwritten jmp LoopTest ; Start with test in case R12 = 0 OuterLoop: mov.w #DELAYLOOPS ,R4

; Initialize loop counter

DelayLoop: ; [clock cycles in brackets] dec.w R4 ; Decrement loop counter [1] jnz DelayLoop ; Repeat loop if not zero [2] dec.w R12 ; Decrement number of 0.1s delays LoopTest: cmp.w #0,R12 ; Finished number of 0.1s delays? jnz OuterLoop ; No: go around delay loop again pop.w R4 ; Yes: restore R4 before returning Ret ; Return to caller

MSP430

19

Stack Operation

Figure: Stack operation

MSP430

20

Low power Operation

Very low power leakage, and it operates from a single supply rail Low current drain in standby mode Useful because it shuts down certain areas of the CPU in order to save power As the LPM mode rises power consumption decreases, the time needed to wake up increases register

The MSP430 is switched into a low power mode by altering bits in the status Processing within an interrupt routine will determine when the processor needs
to change from a low power mode to normal operation, and alters those same status register bits to achieve that

It does this by directly modifying the memory location where the processors
status register was pushed onto the stack at the start of the interrupt

When the interrupt routine returns, using the RETI instruction, the altered
status register value is loaded into the processor status register, and the processor continues operation in the newly selected mode

MSP430

21

MSP430 modes of operation

LPM0 - The CPU is disabled. LPM1 - The loop control for the fast clock (MCLK) is also disabled. LPM2 - The fast clock (MCLK) is also disabled. LPM3 - The DCO oscillator and its DC generator are also disabled. following 1 Active mode (AM), I = 300 uA All clocks are active 2 Low-power mode 0 (LPM0), I = 85uA CPU is disabled ACLK and SMCLK remain active, MCLK is disabled 3 Low-power mode 3 (LPM3), I = 1uA CPU is disabled MCLK and SMCLK disabled ACLK remains active DCOs dc-generator is disabled

LPM4 - The crystal oscillator is also disabled. The most popular 3 are the

As the number of the LPM mode number rises, the number of things disabled
on the chip also rises

But interrupts can wake up the device from any low power mode, process, and
decide whether to restore the low power or active mode.
MSP430 22

Interrupts in MSP430 The MSP430 processor responds to an interrupt in 9 steps:

Completing the currently executing instruction Pushing the PC, program counter which points to the next instruction, onto the
stack

Pushing the SR, status register, onto the stack Selects the highest priority interrupt, if more than one is waiting execution The interrupt request ag resets automatically on single-source ags; multiple
source ags remain set for servicing by software

The SR is cleared; This terminates any low-power mode; because the GIE
(interrupt enable) bit is cleared, further interrupts are disabled

The content of the interrupt vector is loaded into the PC; the program
continues with the interrupt service routine (ISR) at that address

On executing a return from an ISR, the SR and PC are popped from the stack;
returning to execute the instruction at the point of the interrupt

When the SR is restored, interrupts are re-enabled

MSP430

23

Interrupt Stack

Figure: Interrupt stack

MSP430

24

Interrupt vector table

The interrupt vector table is mapped

at the very highest end of memory space (upper 16 words of Flash/ROM), in locations 0FFE0h through to 0FFFEh

The MSP430 uses vectored

interrupts where each ISR has its own vector stored in a vector table located at the end of program memory

MSP430 requires 6 clock cycles

before the ISR begins executing

When interrupt occurs, the

corresponding ag (bit) is set to 1.

An interrupt handler should normally

disable the interrupt by setting ag to 0, allowing another interrupt to occur

Figure: Interrupt vector table

MSP430

25

Digital I/O
8 bit digital I/O port Multifunctional capabilities Digital I/O features: Independently programmable individual I/Os Individually congurable P1 and P2 interrupts Independent input and output data registers Individually congurable pullup or pulldown resistors Pins P2.6 and P2.7 - not digital inputs by default Avoiding oating pins Parallel port

MSP430

26

P1 Digital I/O control Digital I/O is user congurable

Input Register P1IN Output Register P1OUT Direction Register P1DIR Pullup/Pulldown Resistor Enable Register P1REN Function Select Register P1SEL Interrupt enable, P1IE Interrupt edge select, P1IES Interrupt ag, P1IFG

MSP430

27

On-chip peripherals: Outline

Mode of communication with outside world

MSP430 On-chip peripherals 1 Basic Timer1

2 3 4 5 6

Watchdog Timer Real-time clock Timer A, Timer B Comparator A ADC: ADC10, SD16 A

MSP430

28

Timers
Essential to almost every embedded application Functions 1 Generate xed-period events
2 3 4

Periodic wakeup Count edges Timer calls allow CPU to sleep, consuming much less power

MSP430 Timer modules 1 Basic Timer1

2 3 4

Watchdog Timer (WDT) RTC Timer A/B

MSP430

29

Basic Timer1
Present in all MSP430xF4xx devices BTCTL, counters not initialized by reset Provides clock for LCD module

Figure: Simplied block diagram of Basic Timer1

Figure: Basic Timer1 control register BTCTL

MSP430 30

Watchdog timer
Features Up-counter
Counts up and resets the MSP430 when it reaches its limit Always active after the MSP430 has been reset Protects the system against failure of software

Figure: Watchdog timer concept

MSP430

31

Watchdog timer

Figure: Watchdog timer circuitry

MSP430 32

WDT operation

Controlled by 16-bit register WDTCTL Password WDTPW = 0x5A in the upper byte Software reset

Figure: The lower byte of the watchdog timer control register WDTCTL

MSP430

33

Watchdog Timer

Important facts Always active after the MSP430 has been reset
Default period: 32,768 counts (32 ms) Counter (WDTCNTCL bit) must be repeatedly cleared:

petting, feeding, or kicking the dog Interval Timer Used when protective function is not desired
Set the WDTTMSEL bit

MSP430

34

Real-Time Clock

Features Added to recent devices in the MSP430xFxx family

32-bit counter mode with selectable clock sources Calendar and clock mode Automatic counting of seconds, minutes, hours, day of week,

month, year in calendar mode

Selectable BCD format Not an alarm clock

MSP430

35

Timer A Module

Features Most versatile, general-purpose timer

Async 16-bit timer/counter Selectable count mode Extensive interrupt capability Extensive connections to other modules

MSP430

36

Timer A Module

Figure: Simplied block diagram of Timer A

MSP430 37

Timer A: Capture mode

Measure time before a signal event occurs Input signal sources External pin
Internal signal (i.e., Comp A) Vcc/GND

Applications Analog signal rising to Comp A threshold

Slope ADC Frequency measurement Vcc threshold detect (via voltage divider)

MSP430

38

Timer A: Compare Mode

Cause an event after a dened period (exact opposite of capture mode) Event kinds CPU interrupt
Modules tied internally to timer output (DMA, start

ADC/DAC conversion)
External components

Applications PWM generation

RTC Timer A UART

MSP430

39

Timer A: Count Modes

Modes Continuous: Up to FFFF, rolls over to 0000, back up to FFFF
Up: Up to value specied by CCR0, rolls over to 0000, back

up to CCR0 value
Up/down: Up to value specied by CCR0, count down to

0000, back up to CCR0 value

Figure: Count modes of Timer A

MSP430 40

Timer B

Event kinds Provided on larger devices in all MSP430 families Dierences with Timer A
Registers are double buered Range of periods can be selected for the Continuous mode 3 Sampling mode is not possible (not suitable for receiving asynchronous signals) 4 All outputs can be put into a high-impedance state (TBOUTH pin)
1 2

MSP430

41

Timer usages

Scenarios PWM: Use Timer B if available, otherwise Timer A

Less regular outputs: Connect directly to an output of

Timer A or B.
Inputs to be sampled at regular intervals: Connect to Timer A

(Sampling mode)
Inputs to be timed: Timer A or B Periodic software interrupts 1 Watchdog timer (if it is not needed as a watchdog) 2 Basic Timer1 3 Timer A or B The last resort: Software loops

MSP430

42

Comparator A
Features Supports precision slope analog-to-digital conversion
Supply voltage supervision Monitoring of external analog signals Output provided to Timer A capture input Interrupt capability

Figure: Comparator A circuitry

MSP430 43

ADC10 Introduction ADC10 module supports

1 2 3 4 5

Fast, 10-bit analog-to-digital conversions Implements a 10-bit SAR core Sample select control Reference generator Data transfer controller (DTC)

MSP430

44

Features of ADC10 Greater than 200-ksps maximum conversion rate

Monotonic 10-bit converter Sample-and-hold with programmable sample periods Conversion initiation by software or Timer A Software selectable on-chip reference voltage generation

(1.5 V or 2.5 V)

MSP430

45

Features of ADC10..2 Up to eight external input channels

Conversion channels for internal temperature sensor, VCC Monotonic 10-bit converter Separates programs into self contained tasks Selectable conversion clock source

MSP430

46

10-Bit ADC Core What it does..

Converts an analog input to its 10-bit digital

representation
Stores the result in the ADC10MEM register Congured by two control registers,

ADC10CTL0 and ADC10CTL1

Enabled with the ADC10ON bit.

ADC10CLK What the clk does.. Used both as the conversion clock and to generate the sampling period Selection using ADC10SSELx bits and division from 1 to 8 using the ADC10DIVx ADC10OSC, generated internally, is in the 5-MHz range

MSP430

47

Conversion Modes
CONSEQx 00 01 10 11 Mode Single channel single-conversion Sequence-of-channels Repeat single channel Repeat sequence-of-channels Operation single channel is converted once. sequence of channels is converted once. single channel is converted repeatedly. sequence of channels is converted repeatedly.

NADC = 1023

Vin Vmin V max Vmin

Stopping Conversions Depends on the mode of operation

Resetting ENC Or by default set CONSEQx = 0

MSP430

48

Dierent Registers of the ADC10

Figure: ADC10 Registers

Among the various registers, the control register comprises of the following bits,

Figure: ADC10 Control Register

MSP430 49

SD16

Sigma Delta Convertors 1 Consists of up to three independent sigma-delta analog-to-digital converters

2

Each channel has up to 8 fully dierential multiplexed analog input pairs including a built-in temperature sensor Built-in temperature sensor accessible by all channels Selectable low-power conversion mode Software selectable on-chip reference voltage generation (1.2 V)

3 4 5

MSP430

50

Interfacing

Hardware Demonstration 1 Blinking LEDs

2 3 4

Random Light Display- John Davies ADC for thresholding using the 2 inbuilt LEDs LCD shield - a note on energia

MSP430

51

References

MSP430 Microcontroller Basics, John Davies

www.ti.com/msp430

http://www.uniti.in/teaching-material/79

en.wikipedia.org/wiki/TI_MSP430

MSP430

52