I2C Protocol Overview The Inter Integrated Circuit (I2C) protocol is defined by Philips. 4.3.2.

1 I2C (non EZI2C) I2C is a synchronous serial interface, with multi-master-multi-slave topology. Devices operate in either master mode, slave mode, or master-slave mode. In master-slave mode, its default role is slave. When it initializes a transfer, it is a master; when it is addressed by another master, it is a slave. When it is busy in data transfer on the bus (as master or slave), and another master try to address the master-slave device, bus collision will occur. Only a single master may be active during a data transfer. The active master is responsible for driving the serial interface clock on the serial interface clock lane. The I2C interface consists of 2 signals: master(s) and slave(s)). information (output and input to both master(s) and slave(s)). Figure 4-1 I2C Bus Connections The following revisions are distinguished:

To support Fast Mode Plus, please see CDT#101189, about the requirements of IO cells. Implementations use open-drain driver with pull up resistors, such that when a line is not driven, its value is 1. There are two special events that are identified by unique transitions on the I2C bus: START and STOP events. A START event is identified by a falling edge of SDA while SCL is high. A STOP event is identified by a rising edge of SDA while SCL is high. Apart from a START or STOP event, it is not allowed for the SDA line to change value while SCL is high. Four operation modes are distinguished:

Document No. 001-87790 Rev. ** ECN #: 4019697

m0s8scb_ver2 SoftIP BLOCK REQUIREMENTS OBJECTIVE SPEC (BROS) Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 22 of 153 Transitions between the operation modes are dependent on the type of data transfer. There are two types of data transfers: a write transfer and read transfer. A typical write transfer starts with the master transmitting a START event. Next, it transmits an I2C slave address and a write indicator (0). The addressed slave transmits an acknowledgement (0). If the slave address does not address a connected slave device or if the addresses device does not wish to acknowledge the request, no acknowledgement is transmitted. Note that the absence of an acknowledgement, results in a SDA line value of 1 (due to the pull up resistor implementation). If no acknowledgement is transmitted by the slave, the master may end the write transfer with a STOP event. If an acknowledgement is transmitted, the master may transmit write data. The addressed slave transmits an acknowledgement to confirm the receipt of the write data. Upon receipt of this acknowledgement, the master may transmit another write data. A typical read transfer starts with the master transmitting a START event. Next, it transmits an I2C slave address and a read indicator (1). The addressed slave transmits an acknowledgement. If the slave address does not address a connected slave device or if the addresses device does not wish to acknowledge the request, no acknowledgement is transmitted. If no acknowledgement is transmitted by the slave, the master may end the read transfer with a STOP event. Next, the addressed slave transmits read data. The master transmits an acknowledgement to confirm the receipt of the read data. Upon receipt of this acknowledgement, the addressed slave may transmit another read data. Individual data transfers (of one or more data elements) start with a START event and end with a STOP event. Combined data transfers consist of multiple individual transfers that are not separated by STOP events, but by repeated START events only. The following figure illustrates a write and read data transfer. Document No. 001-87790 Rev. ** ECN #: 4019697 m0s8scb_ver2 SoftIP BLOCK REQUIREMENTS OBJECTIVE SPEC (BROS) Company Confidential

A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 23 of 153 Figure 4-2 I2C Protocol Timing Diagram The I2C protocol is a multi-master, multi-slave interface. Bus arbitration is implemented on master devices by monitoring the SDA line. Bus collisions are detected when the master observes a SDA line value that is not the same as the value it is driving on the SDA line. E.g. When master 1 is driving the value 1 on the SDA line and master 2 is driving the value 0 on the SDA line, the actual line value will be 0 (due to the implementation of the I/O signal interface). Master 1 detects the inconsistency and loses control of the bus (release SCL/SDA and go to DEFAULT state). Master 2 does NOT detect any inconsistency and keeps control of the bus. When a slave device is not capable of processing data, it may hold down the SCL line by driving a 0'. Due to the implementation of the I/O signal interface, the SCL line value will be 0, independent of the values any other master or slave may be driving on the SCL line. This is known as clock stretching and is the only situation in which a slave drives the SCL line. The master device monitors the SCL line and detects it when it cannot generate a positive clock pulse (1) on the SCL line. It will react by postponing the generation of a positive edge on the SCL line, effectively synchronizing with the slave device that is stretching the clock. In internally clocked mode, the relationship between I2C SCL and the internal oversampling is controlled by HIGH_PHASE_OVS and LOW_PHASE_OVS in register I2C_CTRL, not by register CTRL.OVS. For internal clocked non-EZ I2C slaves, register CTRL.ADDR_ACCEPT can be used to configure whether to push received matching I2C slave address into RXFIFO. Document No. 001-87790 Rev. ** ECN #: 4019697 m0s8scb_ver2 SoftIP BLOCK REQUIREMENTS OBJECTIVE SPEC (BROS) Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 24 of 153 The slave implementation may be externally or internally clocked. Externally clocked implies operation off the interface clock SCL. Internally clocked implies operation off a clock that is present on the slave device. The System Management Bus (SMBus) is derived from the I2C protocol. The SMBus has more stringent electrical and timing requirements than

I2C; the current m0s8scb IP does not support SMBus timeout requirements. However, with the right Firmware, the current IP should be able to behave as a SMBus compatible slave device. 4.3.2.2 EZI2C The easy I2C (EZI2C) protocol is a meta-protocol on top of the I2C protocol. It is defined by Cypress, but does not have a standard spec. It adds master and slave agreed upon semantics to the use of the I2C protocol, allowing for data frame communication without the need for CPU intervention at the level of individual frames. The EZI2C protocol defines an EZ address that indexes a memory array located on the slave device. There are two types of transfers: an EZ write to a memory array index and an EZ read from a memory array index. An EZ write to a memory array index is by means of an I2C write transfer. The first transmitted write data is used to send an EZ address from the master to the slave. Any additional write data elements in the write transfer are bytes that are written to the memory array at locations indicated communicated EZ address. The EZ address is automatically incremented by the slave as bytes are written into the memory array. When the EZ address exceeds the amount of memory entries, it will not wrap around to 0. Note that when only a single write data is transmitted, only a new EZ address is set, no new bytes are written in the memory array. An EZ read from a memory array index is by means of an I2C read transfer. The EZ read relies on an earlier EZ write to have set the EZ address at the slave. The first received read data is the byte from the memory array at the EZ address memory location. The EZ address is automatically incremented as bytes are read from the memory array. Document No. 001-87790 Rev. ** ECN #: 4019697 m0s8scb_ver2 SoftIP BLOCK REQUIREMENTS OBJECTIVE SPEC (BROS) Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 25 of 153 Figure 4-3 EZI2C Protocol 4.3.2.2.1 Basic transactions From above Figure, it has two basic transactions: e data If the firmware writes only the EZ address in the write transaction, it will

have three basic transactions

The EZ address is incremented by write data or read data transactions, the firmware can easily set a new EZ address in write EZ address and data transactions, it can also set a new EZ address for read data transactions, by combining write EZ address, read data. 4.3.2.2.2 EZ address implementation M0s8scb_ver2 is updated to align with PSoC1/3/5 chips and touch controller chips. In which chips, the EZ address is set by I2C write EZ address transaction, but not affected by following write data transactions or read data transactions. For example, 0x24 0x00 0x11 0x22 0x33 0x44 0x55 Document No. 001-87790 Rev. ** ECN #: 4019697 m0s8scb_ver2 SoftIP BLOCK REQUIREMENTS OBJECTIVE SPEC (BROS) Company Confidential A printed copy of this document is considered uncontrolled. Refer to online copy for latest revision. Page 26 of 153 //0x24 is DUT slave address // write 5 bytes with offset 0x00 (EZ Address.) // read, starts from EZAddress 0x00, // expected data equal written data before