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VLSI PROJECTS

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VLSI PROJECTS, IEEE 2013 PROJECT TITLES

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FINAL YEAR PROJECTS

IEEE PROJECTS 2013-14

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NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)
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NCCT
Smarter way to do your Projects

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

VLSI PROJECT TITLES

VLSI IEEE 2013 PROJECT TITLES VLSI Projects using Spartan3 FPGA Kit
SL.NO
NVL 001 NVL 002 NVL 003 NVL 004 NVL 005 NVL 006 NVL 007 NVL 008 NVL 009 NVL 010 NVL 011 NVL 012 NVL 013

(Spartan3AN FPGA Kit / Xilinx ISE / Xilinx EDK) & CPLD CoolRunner TITLES

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering A Computationally Efficient Delay less Frequency-Domain Adaptive Filter Algorithm A Linear Programming Based Tone Injection Algorithm for PAPR Reduction of OFDM and Linearly Precoded Systems A Low-Complexity Turbo Decoder Wireless Sensor Networks Architecture for Energy-Efficient

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits Aliasing-Free Transmitters Digital Pulse-Width Modulation for Burst-Mode RF

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits Glitch-Free NAND-Based Digitally Controlled Delay-Lines IsoNet: Hardware-Based Architectures Job Queue Management for Many-Core

Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter with Low Adaptation-Delay Broadside and Skewed-Load Tests under Primary Input Constraints

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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NCCT
Smarter way to do your Projects
NVL 014 NVL 015 NVL 016 NVL 017 NVL 018 NVL 019 NVL 020 NVL 021 NVL 022 NVL 023 NVL 024 NVL 025 NVL 026 NVL 027 NVL 028 NVL 029 NVL 030 NVL 031

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

Built-In Generation of Functional Broadside Tests using a Fixed Hardware Structure Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip Design of Hardware Function Evaluators using Low-Overhead Nonuniform Segmentation with Address Remapping Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops Efficiency Optimization for Transmitters Burst-Mode Multilevel Radio Frequency

Efficient Implementation of Reconfigurable Warped Digital Filters With Variable Low-Pass, High-Pass, Band pass, and Band stop Responses Efficient Power-Analysis-Resistant Dual-Field Elliptic Curve Cryptographic Processor Using Heterogeneous Dual-Processing-Element Architecture Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function Eliminating Synchronization Latency Using Sequenced Latching Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes Low-Power Area-Efficient High-Speed I/O Circuit Techniques Low-Power Digital Signal Processor Architecture for Wireless Sensor Nodes Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic Low-Resolution DAC-Driven Linearity Testing of Higher Resolution ADCs Using Polynomial Fitting Measurements MDC FFT/IFFT Processor With Variable Length for MIMO-OFDM Systems Multivoltage Aware Resistive Open Fault Model Oscillation and Transition Tests for Synchronous Sequential Circuits Power-Planning-Aware Assignment Soft Error Hardening via Selective Voltage

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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NCCT
Smarter way to do your Projects
NVL 032 NVL 033 NVL 034 NVL 035 NVL 036 NVL 037 NVL 038 NVL 039 NVL 040 NVL 041 NVL 042 NVL 043 NVL 044 NVL 045 NVL 046 NVL 047 NVL 048 NVL 049 NVL 050 NVL 051 RATS: Restoration-Aware Validation Trace

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

Signal Selection for Post-Silicon

Reduced-Complexity LCC Reed Solomon Decoder Based on Unified Syndrome Computation Reducing the Cost of Implementing Error Correction Codes in Content Addressable Memories Smart Reliable Network-on-Chip Split-SAR ADCs: Improved Linearity With Power and Speed Optimization Spur-Reduction Frequency Synthesizer Exploiting Randomly Selected PFD Static Power Reduction Using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures Theoretical Modeling of Elliptic Curve Scalar Multiplier on LUT-Based FPGAs for Area and Speed Time-Based All-Digital Technique for Analog Built-in Self-Test Two-Tone Phase Delay Control of Center Frequency and Bandwidth in Low-Noise-Amplifier RF Front Ends Unique Measurement and Modeling of Total Phase Noise in RF Receiver VLSI Implementation of a Multi-Mode Turbo/LDPC Decoder Architecture WLS Design of Sparse FIR Digital Filters A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction A Current-Starved Inverter-based Differential Amplifier Design for UltraLow Power Applications A Fast Low-Light Multi-Image Fusion with Online Image Restoration A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS A Low Power Fault Tolerant Reversible Decoder using MOS Transistor A Low Power Single Phase Clock Distribution using VLSI technology

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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NCCT
Smarter way to do your Projects
NVL 052 NVL 053 NVL 054 NVL 055 NVL 056 NVL 057 NVL 058 NVL 059 NVL 060 NVL 061 NVL 062 NVL 063 NVL 064 NVL 065 NVL 066 NVL 067 NVL 068 NVL 069 NVL 070 NVL 071 NVL 072

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

A Novel modulo Adder for 2n-2k-1 Residue Number System A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier A Topology-Based Model for Railway Train Control Systems Achieving Reduced Area by Multi-Bit Flip Flop Design An Analysis of SOBEL and GABOR Image Filters for Identifying Fish An Efficient Denoising Architecture for Removal of Impulse Noise in Images An Efficient High Speed Wallace Tree Multiplier An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic An Interactive RFID-based Bracelet for Airport Luggage Tracking System Area-Delay Efficient Binary Adders in QCA Asynchronous Design of Energy Efficient Full Adder Background Subtraction Based on Threshold detection using Modified K Means Algorithm Comparison of Static and Dynamic Printed Organic Shift Registers CORDIC based Fast Radix-2 DCT Algorithm Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD Tool Design of High Speed Low Power Viterbi Decoder for TCM System Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix2by4 Algorithms
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NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

Www.ncct.in, www.ieeeprojects.net, ncctchennai@gmail.com

NCCT
Smarter way to do your Projects
NVL 073 NVL 074 NVL 075 NVL 076 NVL 077 NVL 078 NVL 079 NVL 080 NVL 081 NVL 082 NVL 083 NVL 084 NVL 085 NVL 086 NVL 087 NVL 088 NVL 089 NVL 090 NVL 091 NVL 092 NVL 093

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max Approximation Error FPGA Implementation of Pipelined Architecture For SPIHT Algorithm Hardware Implementation of a Digital Watermarking System for Video Authentication High-Throughput Compact Delay-Insensitive Asynchronous NOC Router High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic Improvement of the Security of Zigbee by a New Chaotic Algorithm Least Significant Bit Matching Steganalysis based on Feature Analysis Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials Low-Complexity Multiplier for GF (2m) based on All-One Polynomials Low-Overhead Fault-Tolerance Technique Reconfigurable Soft-core Processor for a Dynamically

Low-Power Digital Signal Processing Using Approximate Adders Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT Modified Gradient Search for Level Set Based Image Segmentation Multicarrier Systems based on Multistage Layered IFFT Structure Optical Flow Estimation for Flame Detection in Videos Parallel AES Encryption Engines for Many-Core Processor Arrays Performance Analysis of a New CMOS Output Buffer Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm Pipelined Radix-2k Feed forward FFT Architectures Prototype of a Fingerprint Based Licensing System For Driving

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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NCCT
Smarter way to do your Projects
NVL 094 NVL 095 NVL 096 NVL 097 NVL 098 NVL 099 NVL 100 NVL 101 NVL 102 NVL 103 NVL 104 NVL 105 NVL 106 NVL 107

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS Reconfigurable Processor for Binary Image Processing Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique Reverse Circle Cipher for Personal and Network Security RFID-based Location System for Forest Search and Rescue Missions RFID-based Tracking Deforestation System Preventing Trees Extinction and

Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter Secure Transmission in Downlink Cellular Network with a Cooperative Jammer Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes Shadow Removal for Background Subtraction Using Illumination Invariant Measures Teaching HW/SW Co-Design with a Public Key Cryptography Application Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes The Security Technology and Tendency of New Energy Vehicle in Future

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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NCCT
Smarter way to do your Projects

044-2823 5816, 98411 93224 ncctchennai@gmail.com

VLSI PROJECTS, IEEE 2013 PROJECT TITLES

VLSI Projects available only with Simulation VLSI Projects with Hardware Kit & Simulation - Spartan FPGA 3E KIT VLSI Projects with Hardware Kit & Simulation - CPLD XL, XC Cool Runner

VLSI HARDWARE
SPARTAN 3E KIT CPLD XL9572 XC Cool runner

SOFTWARE DETAILS
Simulation : MODELSIM 6.3G ALTERA Implementation : XILINX ISE 12.2 Language : VHDL / VERILOG Power Estimation : Altera XPE or XILINX Power Analyzer

FOR MORE TITLES VISIT OUR OFFICE DIRECTLY VISIT OUR WEBSITE / BLOGS FOR DOWNLOADS, TITLES & ABSTRACTS YOUR OWN IDEAS CAN ALSO BE IMPLEMENTED

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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NCCT Smarter way to do your Projects FINAL VLSI YEAR PROJECTS 2013 - 2014 PROJECTS, IEEE 2013 PROJECT TITLES

044-2823 5816, 98411 93224 ncctchennai@gmail.com

Why NCCT
Complete Guidance * On time Completion * Excellent Support * Multi platform Training * Flexibility

PROJECTS SUPPORTS & DELIVERABLES

Project Abstracts Project Diagram all required Diagrams PPT & Review preparation for Viva Project Report Guidance Project Demo & Explanation Working Procedure & Screen Shots Datasheets, Manuals & Reference Books in DVD Project Acceptance
Project Completion Certificate

NCCT, 109, 2 Floor, Bombay Flats, Nungambakkam High Road, Nungambakkam, Chennai 600 034, Tamil Nadu. (Next to ICICI Bank, Above IOB, Near Taj Hotel)

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