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    Avinash Hegde
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    The document contains 40 quiz questions about embedded system design topics like non-recurring engineering costs, latency and throughput, revenue loss calculations, performance comparisons, timer ranges, baud rate expressions, DAC and ADC resolutions, PWM remedies, write-back techniques, average PWM outputs, terminal count registers, ROM connections, memory refreshing, SRAM transistors, processor modes, exceptions, ARM memory management hardware, interrupt prioritization, register functions, cpsr fields, privileged modes, interrupt masking, ARM7 pipelining stages, interrupt request patterns, ARM data processing instructions, post-index addressing, logical shift instructions, cpsr/spsr transfers, software

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    Quiz questions on embedded system design

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    ESD_quiz

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    The document contains 40 quiz questions about embedded system design topics like non-recurring engineering costs, latency and throughput, revenue loss calculations, performance comparisons, timer ranges, baud rate expressions, DAC and ADC resolutions, PWM remedies, write-back techniques, average PWM outputs, terminal count registers, ROM connections, memory refreshing, SRAM transistors, processor modes, exceptions, ARM memory management hardware, interrupt prioritization, register functions, cpsr fields, privileged modes, interrupt masking, ARM7 pipelining stages, interrupt request patterns, ARM data processing instructions, post-index addressing, logical shift instructions, cpsr/spsr transfers, software

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    Attribution Non-Commercial (BY-NC)
    Download as DOC, PDF, TXT or read online from Scribd
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    68 views2 pages

    ESD Quiz

    Uploaded by

    Avinash Hegde
    The document contains 40 quiz questions about embedded system design topics like non-recurring engineering costs, latency and throughput, revenue loss calculations, performance comparisons, timer ranges, baud rate expressions, DAC and ADC resolutions, PWM remedies, write-back techniques, average PWM outputs, terminal count registers, ROM connections, memory refreshing, SRAM transistors, processor modes, exceptions, ARM memory management hardware, interrupt prioritization, register functions, cpsr fields, privileged modes, interrupt masking, ARM7 pipelining stages, interrupt request patterns, ARM data processing instructions, post-index addressing, logical shift instructions, cpsr/spsr transfers, software

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    QUIZ QUESTIONS (EMBEDDED SYSTEM DESIGN) 1. What is NRE cost? 2. Define the following: i) latency ii) throughput 3.

    Percentage revenue loss is given by ________ 4. Assume W = 0.26 and D = 4 weeks. Determine % revenue loss. 5. The common method of comparing the performance of two systems is ________ 6. Define timers range 7. Write the expression for baud rate 8. Write the expression for resolution of a DAC 9. The analog input range for an 8 bit ADC is 0-5V. Calculate the encoding for 1V. 10. PWM does not provide enough current to run the DC motor. The remedy for this problem is __________ 11. An extra bit required by the write back technique to reduce the number of writes to main memory is called __________ 12. Assume the PWM output is 5V when high and 0V when low. Determine the average output for an duty cycle of 75%. 13. Terminal count register indicates ____________ 14. The word lines are connected to data lines via __________ in ROM 15. Which memory needs to be refreshed periodically to restore the charge lost due to capacitive discharge? 16. How many transistors are required to represent a bit in SRAM? 17. List the different processor modes 18. What is an exception? 19. Write different types of memory management hardware in ARM core 20. ___________ prioritizes interrupts and simplifies the determination of the device which caused the interrupts. 21. Register r14 represents _____________ 22. The 4 fields of cpsr are 23. ____________ mode allows full read write access to the cpsr 24. The ___ and ___ interrupt mask bits of cpsr control the masking of _____ and _____ respectively.

    25. Write the stages of pipelining in ARM 7 26. Write the binary pattern corresponding to interrupt request mode 27. The data processing instructions that donot use the barrel shift are 28. The base address register is updated with ________________ when post index method is used. 29. The instruction ________ is used whenever there is requirement for register bits to logical shift left. 30. _______ instruction transfers the contents of a register into cpsr or spsr. 31. The SWI instruction causes a software instruction that forces the processor into _____ mode. 32. ____ and _____ branch instructions cause a switch between ARM and thumb state while branching to a routine. 33. ARM has specified _________ that defines how routines are called and how registers are allocated. 34. The flags in the cpsr are updated when ________ is used on data processing instructions. 35. Why coprocessors are used? 36. The software components that are included in embedded system are 37. The stack instructions in thumb instruction set support ___________ stack operations. 38. The thumb versions of the load store multiple instructions support _____ addressing mode. 39. PRE r0 = 0x00000000 r1 = 0x00000004 ADD r0, r1, r1, LSL #1 What is the final result and where is it stored? 40. PRE r1 = 0b00000000000100000000000000001000 CLZ r0, r1 What is the value of r0?

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