Journal of the Korean Physical Society, Vol. 48, January 2006, pp.

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Improved Current Saturation of Polycrystalline Silicon Thin-Film Transistors Employing Reverse Bias Depletion in the Channel
Woo-Jin Nam, Ji Hoon Kim, Jae-Hoon Lee, Hye-Jin Lee and Min-Koo Han
School of Electrical Engineering, Seoul National University, Seoul 151-742 (Received 12 October 2005) A new poly-Si TFT employing reverse bias depletion is proposed and fabricated in order to suppress the kink current and increase the output resistance in saturation regime. The counterdoped (p+ ) source is embedded and extended into the channel region. As VDS increased, the p+ n depletion width increased and the eective channel width is reduced. Also, the kink current is suppressed by the counter-doped region. In our experimental measurement, the proposed TFTs employing p+ n depletion successfully exhibit a good saturation current as well as kink current suppression.
PACS numbers: 85.30 De Keywords: Polycrystalline silicon, Thin-lm transistor, Kink, Counter doping, Saturation

I. INTRODUCTION Polycrystalline silicon thin-lm transistors (Poly-Si TFTs), of which the mobility and on-current are rather large, have attracted considerable attention for various device applications such as active-matrix liquid crystal displays (AMLCD) and organic light-emitting-diode displays (AMOLED) [13]. However, the kink current due to an inherent oating body structure of a thin-lm transistor is a critical issue [46]. It is well known that polySi TFTs under high-drain-eld condition have unstable output characteristics due to the kink eect, which originates from the undesirable parasitic bipolar transistor action. Kink eects degrade the device characteristics by decreasing the mobility and shifting the threshold voltage and also reduce the gain of an amplier [7, 8]. We have already proposed a counter-doped body tied to source (BTS) structure, and the kink current was considerably suppressed by hole collection of the counterdoped source terminals [9]. However, even though the kink current is successfully suppressed, the channel resistance is not in practice too large, so that the saturation current would be rather increased as VDS is increased. The output characteristic is aected by the channel resistance as well. The output resistance should be increased in order to achieve highperformance poly-Si driver circuits such as a high-gain amplier for an analog buer or a stable current source [10]. The purpose of our work is to propose poly-Si TFTs employing p+ n reverse bias depletion for kink suppres E-mail:

sion and high current saturation. The counter-doped (p+ ) source is embedded and prolonged into the channel region, so that a p+ n junction is formed in the channel region. As VDS is increased, the channel width is eectively controlled by reverse biased p+ n depletion. We have fabricated the proposed poly-Si TFTs, and the experimental data show that the kink current is suppressed and the output resistance is increased.

II. PROPOSED POLY-SI THIN-FILM TRANSISTORS The proposed poly-Si TFT employing counter-doped source is shown in Figure 1. In the n-type poly-SI TFTs, the counter-doped p+ source is tied to the n+ source and prolonged into the channel region. The channel doping concentration of thin-lm transistors is almost intrinsic typically, however, it exhibits n-channel characteristics by the positive gate bias (VGS ). Therefore, a p+ n junction is formed in the channel region when the electrons are accumulated in the surface of the channel by VGS > VT H . In the experiment, the width and length of the channel are W = 15 m and L = 10 m, respectively. The width and length of prolonged p+ source are Wp = 4 m and Lp = 6 m. The proposed structure employs n-type and p-type self-align doping by the gate and is compatible with the conventional CMOS process. The prolonged p+ source is constituted in the n-type channel region in order to achieve reverse bias depletion. When VDS is increased, the poly-Si TFT operates from linear regime to saturation regime and the potential in the channel region is also increased. Since the prolonged
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jintree@emlab.snu.ac.kr; Fax.: +82-2-871-7992

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Fig. 1. Proposed polycrystalline silicon thin-lm transistor (poly-Si TFT) employing the counter-doped p+ region in the channel. The n -region is hatched and the n+ -region is shaded. The Lp and Wp are the length and width of p-body into the channel.

Fig. 3. Calculated width of the channel: (a) the layout width of the proposed TFT; (b) the width of the reverse biased p+ n depletion xn ; (c) the eective channel width (Wef f ) of the proposed TFT according to the reverse bias VR .

Fig. 2. Device 2-D simulation (SILVACO ATLAS) result for the potential distribution in the channel region according to VDS bias VDS = 4 V, 6 V, 10 V with VGS = 5 V.

p+ source is connected to the source voltage VS , the potential increase in the channel means that the reverse bias of p+ n depletion is increased. The potential distribution in the channel region is simulated as shown in Figure 2. The prolonged p+ source is 6 m and the reverse bias voltage @ L = 6 m and VDS = 10 V is 1.5 V. The reverse bias depletion width of the n-channel region is described as: xn = 2 s (Vbi + VR ) Na 1 = e Nd Na + Nd Wef f = W 2xn . f (VDS ), (1)

Here, Vbi is the built-in potential of p+ n junction, and this is determined by the doping concentration Na (hole) and Nd (electron). VR is the reverse bias voltage from the p+ source to the n-channel and is a function of VDS . When VR is zero initially, the p+ n depletion is induced by Vbi only so that the depletion width is rather small. As VR is increased, the depletion width is increased in the manner described in equation (1). It is noted that the depletion width is mainly determined by the doping concentrations Na and Nd . In the proposed structure, the counter-doped source node is highly doped by p+ (Na = 1 1019 cm3 ) and the channel region is intrinsic (Nd = 1 1016 cm3 ) typically, so that the entire depletion width belongs to the n-channel region [10]. We calculated the reverse biased p+ n depletion width (xn ). When VR is 1 V, xn is calculated as about 0.49 m. The eective channel width in the p+ n depletion region is Wef f = W 2xn = 7 0.92 6 m. Figure 3 shows the calculated Wef f in the p+ n depletion region according to VDS increase. The Wef f is reduced by VDS and exhibits a root square curve. In the depletion region, the channel width is reduced eectively so that the current path is not allowed. Therefore, IDS current equations of the conventional and the proposed poly-Si TFTs may be described as:

IDS =

Wef f Cox (VGS VT H )2 [1 + (VDS VDS.SAT )] 2L (W 2xn )Cox = (VGS VT H )2 [1 + (VDS VDS.SAT )] 2L W Cox = (VGS VT H )2 [1 + (VDS VDS.SAT )][1 f (VDS )]. 2L

(2)

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Journal of the Korean Physical Society, Vol. 48, January 2006

IV. RESULTS AND DISCUSSION Figure 6 shows the IDS -VGS transfer curve of the fabricated poly-Si TFTs. The electrical properties such as the eld-eect mobility ( = 179 cm2 /Vs) and the threshold voltage (VT H = 2.8 V) were measured. The counterdoped p+ region is tied to the source node with the same potential and it is not aected by VGS voltages. The measured devices of single-gate length 15 m exhibit a low leakage current of about 1 1012 A due to the LDD process. The output characteristics of the conventional and the proposed poly-Si TFT are shown in Figure 7. The gate voltage VGS is from 5 V to 9 V, and the drain current is increased from 0 V to 10 V. The output current of the conventional TFT is increased as VDS is increased, while that of the proposed TFT is suppressed successfully. This is because the counter-doped p+ node induces a reverse bias depletion into the n-channel region and the current path is narrowed as VDS increases as shown in Figure 4. The current level is rather low compared with

Fig. 4. Eective channel width reduction of the proposed structure according to VDS increase.

Here, is the coecient obtained by Eq. (1) ( = 2/W). The lambda () indicates the channel length modulation factor generally in a short channel MOS device [12]. In this paper, denotes the current saturation factor for convenience, which is obtained empirically due to the kink eect and the low output resistance of poly-Si TFTs. By the proposed Eq. (2), the current increase due to the lambda factor may be suppressed by the reduced channel width in the reverse biased p+ n depletion as illustrated in Figure 4.

III. EXPERIMENTS 70-nm-thick a-Si lm was deposited by 280 C PECVD and dehydrogenation was performed by 400 C 2-hr furnace annealing. The a-Si lm was crystallized by XeCl excimer laser ( = 308 nm) [13]. 100-nm TEOS gate insulator and 300-nm aluminum (Al) gate metal were used. Ion implantation (phosphorus and boron) for source/drain, LDD (lightly doped drain) and counterdoped source regions and excimer laser annealing for dopant activation were performed. The fabrication process is compatible with the conventional CMOS poly-Si process and no additional mask step is required. A photograph of the fabricated poly-Si TFT is shown in Figure 5. The counter-doped p+ regions are successfully dened by a self-align doping process. Self-align doping is possible by combining gate-metal patterning and ion implantation simultaneously via photolithography.

Fig. 6. Measured transfer curve of the proposed poly-Si TFTs.

Fig. 5. Photograph and dimensions of the low-temperature (450 C) fabricated ELA poly-Si TFT employing the counterdoped p+ source.

Fig. 7. Measured output characteristics of the conventional and the proposed poly-Si TFTs. On considering the dierent geometries of the two TFTs, the current values are normalized by width and length dimensions.

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order to suppress the kink current and increase the saturation output resistance. The counter-doped region is tied to the source and prolonged into the channel region. As VDS is increased, the p+ n depletion is increased in the n-channel region by the reverse bias condition and the eective channel width is reduced. The reduction of channel width increases the output channel resistance, so that the output current is well saturated. Also, the kink eect is suppressed by the hole current collection in the counter-doped region. In our experiment, the proposed TFTs successfully exhibit a good saturation current as well as kink current suppression.
Fig. 8. Hot-carrier stress measurement comparison by investigating the ratio of initial maximum transconductance (gm0.max) before stress to the degraded ones (gm.max) after stress.

REFERENCES
[1] J. Jin, in Tech. Digest of AMLCD (Tokyo, Japan, Jul, 2002), p. l. [2] Y. K. Lee, K. M. Kim, J. I. Ryu, Y. D. Kim, K. H. Yoo, J. Jang, H. Y. Jeong and D. J. Choo, J. Korean Phys. Soc. 39, 291 (2001). [3] Min-Woo Ha, Byung-Chul Jeon, Min-Koo Han and Yearn-Ik Choi, J. Korean Phys. Soc. 44, 172 (2004). [4] M. Valdinoci, L. Colalongo, G. Baccarani, G. Fortunato, A. Pecora and I. Policicchio, IEEE Trans. Electron Device, 44, 2234 (1997). [5] M. Hack and A. G. Lewis, IEEE Electron Device Lett. 12, 203 (1991). [6] Sorin Cristoloveanu, J. Korean Phys. Soc. 45, 1189 (2004). [7] J. S. Yoo, C. H. Kim, M. C. Lee, M. K. Han and H. J. Kim, Intl Electron Device Meeting (Washington, DC, 2000), p. 217. [8] A. G. Lewis, T. Y. Huang, R. H. Bruce, M. Koyanagi, A. Chiang and I. W. Wu, Intl Electron Device Meeting (1988), p. 264. [9] J. H. Kim, in Society for Information Displays (SID) Tech. Dig. (Seattle, USA, 2004), p. 284. [10] H. G. Yang, P. Migliorato, C. Reita and S. Fluxman, IEE Electronics Lett. 29, 38 (1993). [11] Donald A. Neamen, Semiconductor Physics & Devices 2nd edition, (IRWIN, ISBN 0-25-20869-7, 1997), p. 219. [12] R. Jacob Baker, Harry W. Li and David E. Boyce, CMOS circuit design, layout, and simulation, WileyInterscience, ISBN 0-7803-3416-7, 96 (1998). [13] M. C. Lee, J. H. Jeon, S. H. Jung and M. K. Han, J. Korean Phys. Soc. 37, 870 (2000).

the conventional one. The Wef f is not the initial W = 15 m and is rather small, even at zero VR , because p+ n depletion is induced by the built-in potential Vbi only. In the proposed device, the kink current is also suppressed and the kink starting points are retarded compared with the conventional device. The kink-current suppression may be assisted by the hole current collection of the counter-doped p+ node [5]. We also observed the eects of electrical stress on the proposed poly-Si TFTs and conventional ones as shown in Figure 8. The degradation of the electrical characteristics of the poly-Si TFTs under hot-carrier stress was investigated by comparing the maximum transconductance (Gm.max). The stress conditions are VDS = 12 V and VGS of the conventional and the proposed TFT is 8 V and 9 V, respectively, in order to compare the Gm degradation from the same initial value (Gm0.max). The conventional TFTs exhibit more signicant degradation than the proposed ones, while the proposed ones do not suer the severe stress. It is noted that the kink current is suppressed and the reliability under electrical stress is rather improved in the proposed structure.

V. CONCLUSION A new poly-Si TFT employing p+ n reverse bias depletion has been proposed and veried by measurement in