TCNT0 (timer/Counter register)

D7

D6

D5

D4

D3

D2

D1

D0

TCCRO (Timer/Counter Control Register) FOC0 WGM00 COM01 COM00 WGM01 CS02 CS01 CS00 (D7) FOC0 Force compare match: This is a write-only bit, which can be used while generating a wave. Writing 1 to it causes the wave generator to act as if a compare match had occurred. WGM00, WGM01 Timer0 mode selector bits: 0 0 : Normal 0 1 : CTC (Clear Timer on Compare Match) D6 D3 1 0 : PWM, Phase Correct 1 0 : Fast PWM COM01, COM00 D5 D4 Compare Output Mode: These bits control the waveform generator (See Chapter 15) CS02, CS01, CS00 Timer0 clock selector: 0 0 0 : No clock source (Timer/Counter stopped) 0 0 1 : clk (No Prescaling) D2 D1 D0 0 1 0 : clk / 8 0 1 1 : clk / 64 1 0 0 : clk / 256 1 0 1 : clk / 1024 1 1 0 : External Clock source on T0 pin, clock on falling edge 1 1 1 : External Clock source on T0 pin, clock on rising edge TIFR (Timer/Counter Interrupt Flag Register) OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 OCF0 (D0) TOV0 : Timer0 overflow flag bit, 0 = Timer0 did not overflow, 1 = Timer0 has overflowed (going from $FF to $00) (D1) OCF0 : Timer0 output compare flag bit, 0 = Compare match did not occur. 1 = compare match occurred (D2) TOV1 : Timer1 overflow flag bit (D3) OCF1B : Timer1 output compare B match flag (D4) OCF1A : Timer1 output compare A match flag (D5) ICF1 : Input Capture flag (D6) TOV2 : Timer2 overflow flag bit (D7) OCF2 : Timer2 output compare match flag TCCR2 (Timer/Counter Control Register) (D7) FOC2 : Force compare match: WGM20, WGM21 D6 D3 COM21, COM20 CS22, CS21, CS20 D2 D1 D0 TOV0

FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 A write-only bit, which can be used while, is generating a wave. Writing 1 to it causes the wave generator to act as if a compare match had occurred. Timer2 mode 0 0 : Normal 0 1 : CTC (Clear Timer on Compare Match) selector bits: 1 0 : PWM, Phase Correct 1 0 : Fast PWM D5 D4 Compare Output Mode: These bits control the waveform generator (See Chapter 15) Timer2 clock selector: [0 0 0 : No clock source (Timer/Counter stopped)] [0 0 1 : clk (No Prescaling) ] [0 1 0 : clk / 8] [0 1 1 : clk / 32] [1 0 0 : clk / 64] [1 0 1 : clk / 128] [1 1 0 : clk / 256] [1 1 1 : clk / 1024] WGM10

TCCR1A (Timer1 Control Register A) COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B WGM11 COM1A1, COM1A0 D7 D6 Compare Output Mode for Chanel A: (See Chapter 15) COM1B1, COM1B0 D5 D4 Compare Output Mode for Chanel B: (See Chapter 15) (D3) FOC1A : Force Output Compare for Channel A (D2) FOC1B : Force Output Compare for Channel B WGM11, WGM10 D1 D0 Timer1 mode: (See Chapter 15)

TCCR1B (Timer1 Control Register B) ICNC1 ICES1 WGM13 WGM12 CS12 CS11 CS10 (D7) ICNC1 : Input Capture Noise Canceller : 0 = Input Capture is disabled 1 = Input Capture is enabled. (D7) ICES1 : Input Capture Edge Select: 0 = Capture on the falling (negative edge) 1 = Capture on the rising (positive edge) (D5) : Not Used , (D4) WGM13 , (D3) WGM12 : Timer 1 mode COM1B1, COM1B0 D5 D4 Compare Output Mode for Chanel B (D3) FOC1A : Force Output Compare for Channel A (D2) FOC1B : Force Output Compare for Channel B WGM11, WGM10 D1 D0 Timer1 mode Update of TOV1 Flag Mode WGM13 WGM12 WGM11 WGM10 Timer/Counter Mode of Operation Top OCR1x Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM, Phase Correct, 8-bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM, Phase Correct, 9-bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM, Phase Correct, 10-bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 Fast PWM, 8-bit 0x00FF TOP TOP 6 0 1 1 0 Fast PWM, 9-bit 0x01FF TOP TOP 7 0 1 1 1 Fast PWM, 10-bit 0x03FF TOP TOP 8 1 0 0 0 PWM, Phase and Frequency Correct ICR1 BOTTOM BOTTOM 9 1 0 0 1 PWM, Phase and Frequency Correct OCR1A BOTTOM BOTTOM 10 1 0 1 0 PWM, Phase Correct ICR1 TOP BOTTOM 11 1 0 1 1 PWM, Phase Correct OCR1A TOP BOTTOM 12 1 1 0 0 CTC ICR1 Immediate MAX 13 1 1 0 1 Reserved 14 1 1 1 0 Fast PWM ICR1 TOP TOP 15 1 1 1 1 Fast PWM OCR1A TOP TOP CS12, CS11, CS10 Timer1 clock selector: [0 0 0 : No clock source (Timer/Counter stopped)] [0 0 1 : clk (No Prescaling) ] D2 D1 D0 [0 1 0 : clk / 8] [0 1 1 : clk / 64] [1 0 0 : clk / 256] [1 0 1 : clk / 1024] [1 1 0 : External Clock source on T1 pin, clock on falling edge ] [1 1 1 : External Clock source on T1 pin, clock on rising edge ] ICR1 (Input Capture Register for Timer1) D15 D14 D13 D12 D11 ICR1H D10 D9 D8 D7 D6 D5 D4 D3 ICR1L D2 D1 D0

Page 1 of 4

SREG (Status Register) Description

I Global Interrupt Enable

T Bit Copy Storage

H Half Carry

S Sign Flag

V Overflow Flag

N Negative Flag

Z Zero Flag

C Carry Flag

TIMSK ( Timer Interrupt Mask Register ) OCIE2 TOIE2 (D0) TOIE0 Timer0 Overflow Interrupt Enable (D1) OCIE0 Timer0 Output Compare Match Interrupt Enable (D2) TOIE1 Timer1 Overflow Interrupt Enable (D3) OCIE1B Timer1 Output Compare B Match Interrupt Enable (D4) ICIE1A Timer1 Output Compare A Match Interrupt Enable (D5) TICIE1 Timer1 Input Capture Interrupt Enable (D6) TOIE2 Timer2 Overflow Interrupt Enable (D7) OCIE2 Timer2 Output Compare Match Interrupt Enable GICR (General Interrupt Control Register) INT1 (D7) INT1 External Interrupt Request 1 Enable (D6) INT0 External Interrupt Request 0 Enable (D5) INT2 External Interrupt Request 2 Enable INT0

TICIE1 ICIE1A OCIE1B 0 = Disable Timer0 Overflow Interrupt 0 = Disable Interrupt 0 = Disable Interrupt 0 = Disable Interrupt 0 = Disable Interrupt 0 = Disable Interrupt 0 = Disable Interrupt 0 = Disable Interrupt INT2 0 = Disable Interrupt 0 = Disable Interrupt 0 = Disable Interrupt SM1 ISC10 0 1 0 1 -

TOIE1 OCIE0 TOIE0 1 = Enable Timer0 Overflow Interrupt 1 = Enable Interrupt 1 = Enable Interrupt 1 = Enable Interrupt 1 = Enable Interrupt 1 = Enable Interrupt 1 = Enable Interrupt 1 = Enable Interrupt IVSEL 1 = Enable Interrupt 1 = Enable Interrupt 1 = Enable Interrupt IVCE

MCUCR ( MCU Control Register ) SE SM2 ISC01 ISC00 Description 0 0 A low level of INT0 generates an interrupt request 0 1 Any logical change on INT0 generates an Interrupt request 1 0 The falling edge of INT0 generates an interrupt 1 1 The rising edge of INT0 generates an interrupt MCUCSR ( MCU Control and Status Register ) JTD (D6) ISC2 Description 0 The falling edge of INT2 generates an interrupt GIFR ( General Interrupt Flag Register ) Interrupt External Interrupt request 0 External Interrupt request 1 External Interrupt request 2 Time/Counter2 Compare Match Time/Counter2 Overflow Time/Counterl Capture Event Time/Counterl Compare Match A Time/Counterl Compare Match B Time/Counterl Overflow Time/CounterO Compare Match INTF1 Vector Name in WinAVR INT0_vect INT1_vect INT2_vect TIMER2_COMP_vect TIMER2_OVF_vect TIMER1_CAPT_vect TIMER1_COMPA_vect TIMER1_COMPB_vect TIMER1_OVF_vect TIMERO_COMP_vect REFS0 ISC2

ISC11 0 0 1 1

SM0 ISC11 ISC10 ISC01 ISC00 Description A low level of INT1 generates an interrupt request Any logical change on INT1 generates an Interrupt req. The falling edge of INT1 generates an interrupt The rising edge of INT1 generates an interrupt JTRF WDRF BORF EXTRF Description The rising edge of INT2 generates an interrupt PORF

(D6) ISC2 1 INTF2

INTF0

Interrupt Time/CounterO Overflow SPI Transfer complete USART, Receive complete USART, Data Register Empty USART, Transmit Complete ADC Conversion complete EEPROM ready Analog Comparator Two-wire Serial Interface Store Program Memory Ready

Vector Name in WinAVR TIMERO_OVF_vect SPI_STC_vect USARTO_RX_vect USARTO_UDRE_vect USARTO_TX_vect ADC_vect EE_RDY_vect ANALOG_COMP_vect TWI_vect SPM_RDY_vect

ADMUX ( ADC Multiplexer Register ) REFS1 REFS1 REFS0 Reference Voltage Selection Bits 0 0 V REF = A REF Pin Set externally 0 1 V REF = AVCC Pin Same as VCC 1 0 Reserved 1 1 MUX40 00000 00100

V REF = Internal 2.56v Fixed regardless of VCC value Pin Select ADC0 ADC4 MUX40 00001 00101 Pin Select ADC1 ADC5

ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 (D5) ADLAR ADC Left Adjust Result 0 Result will be right adjusted 1 Result will be left adjusted MUX4 ~ MUX0: Analog Channel and Gain Selection Bits The value of these bits selects the gain for the differential channels and also selects which combination of analog inputs is connected to the ADC. MUX40 Pin Select MUX40 Pin Select 00010 ADC2 00011 ADC3 00110 ADC6 00111 ADC7

ADCSRA ( ADC Control and Status Register A ) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 (Bit 7) ADEN : ADC Enable : Setting this bit to one will enable the ADC, and enabled when you set this bit to one. clearing this bit to zero will disable it even while a conversion is in progress. (Bit 4) ADIF: 4 ADC Interrupt Flag : This bit is set when an ADC conversion (Bit 6) ADSC : ADC Start Conversion : To start each conversion you have to completes and the data registers are updated. set this bit to one. (Bit 3) ADIE: ADC Interrupt Enable : Setting this bit to one enables the ADC (Bit 5) ADATE: ADC Auto Trigger Enable : Auto triggering of the ADC is conversion complete interrupt. ADPS20 : ADC Presaler Select Bits: These bits determine the division factor between the XTAL frequency and the input clock to the ADC. ADPS2 ADPS1 ADPS0 ADC Clock ADPS2 ADPS1 ADPS0 ADC Clock 0 0 0 Reserved 1 0 0 Clk / 16 0 0 1 Clk / 2 1 0 1 Clk / 32

Page 2 of 4

0 0

1 1

0 1

Clk / 4 Clk / 8

1 1

1 1

0 1

Clk / 64 Clk / 128

LM35 Temperature Sensor Series Selection Guide Part Temp. Range Accuracy LM35A -55 C to+150 C +1.0 C LM35 -55 C to +150 C +1.5 C LM35CA -40 C to +110 C +1.0 C LM35C -40 C to +110 C +1.5 C LM35D 0 C to +100C +2.0 C

Output Scale 10 mV/C 10 mV/C 10 mV/C 10 mV/C 10 mV/C

LM34 Temperature Sensor Series Selection Guide Part Temp. Range Accuracy LM34A -50 F to +300 F +2.0 F LM34 -50 F to +300 F +3.0 F LM34CA -40 F to +230 F +2.0 F LM34C -40 F to +230 F +3.0 F LM34D -32 F to +212 F +4.0 F

Output Scale 10 mV/F 10 mV/F 10 mV/F 10 mV/F 10 mV/F

SPSR ( SPI Status Register ) SPIF SPI2X (Bit 7) SPIF : SPI Interrupt Flag : In master mode, this bit is set in two situations: when a serial transfer is completed, or when SS pin is an input and is driven low by an external device. Setting the SPIF flag to one will cause an interrupt if SPIE in SPCR is set and global interrupts are enabled. (Bit 6) WCOL : Write COLlision Flag : The WCOL bit is set if you write on SPDR during a data transfer. (Bit 0) SPI2X : Double SPI Speed : When the SPI is in master mode, setting this bit to one doubles the SPI speed. Notice that both the WCOL bit and the SPIF bit are cleared when you read the SPI Status Register and then access the SPI Data Register. Alternatively, the SPIF bit is cleared by hardware when executing the corresponding interrupt handler. SPCR ( SPI Control Register ) SPIE SPE DORD MSTR CPOL CPHA SPR1 SPRO (Bit 7) SPIE : SPI Interrupt Enable : 1 = enable the SPI interrupt. (Bit 3) CPOL: Clock Polarity : This bit set the base value of clock when it is idle. (Bit 6) SPE: SPI Enable : 1 = enable the SPI. 0 = disable the SPI. At CPOL = 0 the base value of the clock is zero while at CPOL = 1 the base value (Bit 5) DORD : Data Order : 1 = The LSB is transmitted first of the clock is one. 0 = The MSB is transmitted first. (Bit 2) CPHA : Clock Phase : CPHA = 0 means sample on the leading (first) clock (Bit 4) MSTR : Master/Slave Select : 1 = work in master mode edge, while CPHA = 1 means sample on the trailing (second) clock. 0 = work in slave mode. Notice that if the SS pin is configured as an input and (Bit 1) SPR1 : SPI Clock Rate Select 1 (Bit 0) SPRO: SPI Clock Rate Select 0 is driven low while MSTR is 1, MSTR will be cleared, and SPIF will become set. (Bit 1,2) control the SCK rate of the device in master mode. See Table below SPI2X SPR1 SPRO SCK Frequency SPI2X SPR1 SPRO SCK Frequency 0 0 0 Fosc/4 1 0 0 Fosc/2 (Not recommended) 0 0 1 Fosc/16 1 0 1 Fosc/8 0 1 0 Fosc/64 1 1 0 Fosc/32 0 1 1 Fosc/128 1 1 1 Fosc/64 SPDR ( The SPI Data Register ) D7 D6 D5 D4 D3 D2 D1 D0

List of Commands in MAX7221 Command D15D12 D11 D10 D9 D8 Hex Code No operation X 0 0 0 0 xo Set value of digit 0 X 0 0 0 1 XI Set value of digit 1 X 0 0 1 0 X2 Set value of digit 2 X 0 0 1 1 X3 Set value of digit 3 X 0 1 0 0 X4 Set value of digit 4 X 0 1 0 1 X5 Set value of digit 5 X 0 1 1 0 X6 Set value of digit 6 X 0 1 1 1 X7 Set value of digit 7 X 1 0 0 0 X8 Set decoding mode X 1 0 0 1 X9 Set intensity of light X 1 0 1 0 XA Set scan limit X 1 0 1 1 XB Turn on/ off X 1 1 0 0 XC Display test X 1 1 1 1 XF Notes: 1) X means do not care. 2) Digits are designated as 0-7 to drive total of eight 7-segment LEDs. TWBR ( TWI Bit Rate Register ) TWSR ( TWI Status Register ) TBR7 TWS7 TBR6 TWS6 TBR5 TWS5 TBR4 TWS4 TBR3 TWS3 TBR2 TBR1 TWPS1 TBR0 TWPS0

(Bit 7 3) TWS73 : TWI Status : These Five Bits show the status of the TWI control and Bus (Bit 1 0) TWPS10 : TWI Prescaler Bits : These bits control the bit rate prescaler TWCR ( TWI Control Register ) TWINT TWEA TWSTA TWSTO TWWC TWEN TWIE (Bit 7) TWINT: TWI Interrupt : This bit is set by hardware when the TWI (Bit 4) TWSTO: TWI STOP condition bit : In master mode, making this bit module has finished its current job. If the TWI and general interrupt are HIGH causes the TWI to generate a STOP condition. This bit is cleared by enabled, changing TWINT to one will cause the MCU to jump to the TWI hardware when the STOP condition is transmitted.

Page 3 of 4

interrupt vector. Clearing this flag starts the operation of the TWI. TW INT must be cleared by software. (Bit 6) TWEA: TWI Enable Acknowledge : Making this bit HIGH will enable the generation of ACK when needed in slave or receiver mode. (Bit 5) TWSTA: TWI START condition Bit : Making this bit HIGH will generate a START condition if the bus is free; otherwise, the TWI module waits for the bus to become free and then generates a START condition

(Bit 3) TWWC: TWI Write Collision Flag : This bit is set HIGH when we attempt to access the TWI Data Register when TWINT is low. This flag is cleared by writing to the TWDR register when TWINT is high. (Bit 2) TWEN: TWI Enable : Making this bit HIGH enables the TWI module. (Bit 0) TWIE: TWI Interrupt Enable : Making this bit HIGH enables the TWI interrupt if the general interrupt is enabled.

ADDRESS 00H 01H 02H 03H 04H 05H 06H 07H 08H-3FH

Bit7 CH 0 0 0 0 0 OUT

Simplified Block Diagram of DS1307 (Maxim / Dallas Semiconductor) Bit5 Bit4 Bit3 Bit2 Bit1 10 Seconds Seconds 10 Minutes Minutes 1 = 12 hr 0=AM 1=PM 10 Hour Hours 0 = 24 hr 10 Hour Hours 0 Day Date Month 10 Year Year 0 0 SQWE 0 0 RS1 Bit6

Bit0

RS0

Function Seconds Minutes Hours Hours Day Date Month Year Control RAM 56 x 8

Range 00 59 00 59 01 12 00 23 01 07 01 31 00 99 00 59 00H FFH

DS1307 Control Register (at address 07H) OUT 0 0 SQWE 0 0 RS1 RS0 OUT (output control): If the square wave output is disabled, setting the OUT bit to one will make the SQW/OUT pin low, and clearing the OUT bit to zero will make the SQW/OUT pin high. SQWE (square wave enable) : If this bit is set HIGH, the oscillator output is enabled; otherwise, it is disabled. RS1-RS0 (rate select) : These bits select the output frequency of the oscillator output according to the following table. RSI RSO Output Frequency 0 0 1Hz 0 1 4.096 kHz 1 0 8.192 kHz 1 1 32.768 kHz

ATMEGA32 Microcontrollers Registers Detail. Note you will not bring this stuff in the exam. It will be provided to you along with the Question Paper. (Engr. Rashid Farid Chishti, Lecturer FET, IIUI.) Page 4 of 4