Professional Documents
Culture Documents
The MITRE PRT Laboratory is a multidiscipline The Background section describes the traditional
electronic system rapid prototyping team focused on risk waveform porting procedure. The remaining sections
reduction and requirements specification with the mission discuss various aspects of the PRT Lab’s proposed
of assisting the government in the successful acquisition of approach to structured waveform delivery.
state-of-the-art communication, networking, sensor and
navigation systems. The HDR-RF Test Waveform BACKGROUND
developed by the PRT Lab is a risk reduction effort for the
HDR-RF ground terminal program. The power efficient Without structured design guidelines and a standard
Test Waveform uses a strong low-density parity-check delivery approach, porting an FPGA-based waveform onto
(LDPC) forward error correction (FEC) code with Offset a new hardware platform is often a daunting task. This is
Quadrature Phase Shift Keying (OQPSK) modulation, and reflected in [4] where it is argued that porting a poorly
operates at four different data rates. The first goal of the designed and delivered waveform can actually exceed the
PRT Lab is to deliver a complete handoff package of the costs of a new development. Why is porting FPGA-based
HDR-RF Test Waveform to the ground modem waveform so difficult and costly? The answer lies in the
contractors. The contractors are responsible for porting the tasks that a porter must perform - namely FPGA
Test Waveform to demonstrate the HBHT capability of repartitioning, retargeting and interfacing.
their hardware platforms currently under development.
The second goal is to demonstrate to the government a Repartitioning is the act of mapping the waveform to fit
powerful reuse strategy for FPGA-based waveforms. onto the hardware resources available on the target
platform. A waveform can be viewed as a chain of signal
1-6
978-1-4244-2677-5/08/$25.00 ©2008 IEEE
processing stages which the developer breaks up into the target hardware platform, but also a detailed
discrete segments called waveform components. The knowledge of the original design implementation, thus
porter can combine multiple components to fit into a larger making hardware retargeting a difficult and labor intensive
FPGA or rework a large component to fit into a smaller task.
device. Reworking may involve choosing an alternate
implementation or splitting the functionality into two or Interfacing requires the waveform porter to create
more smaller components. Repartitioning is continued specialized gaskets to translate waveform specific interface
until the waveform is completely mapped to the new to platform specific transport protocol and I/O standard.
hardware. Figure 1 below shows an example waveform The difficulty of this task is based on the uniformity of
being mapped to target platforms FPGA1 and FPGA2. component interfaces. If the waveform interface is
Note that WC3 had to be broken up into two pieces consistent across the components, the number of different
because the original implementation was too big to fit onto gaskets can be kept to a minimum. On the other hand, if
the target device. To effectively partition the waveform, the waveform interface varies from component to
the porter must have detailed knowledge of the resource component, the porter may need to develop more custom
utilization of each component. gaskets to interface the waveform to the hardware
platform. Figure 1 illustrates the worst case scenario where
every component in the waveform has slightly a different
interface as depicted by the different shapes. To port this
example waveform to the new FPGA devices, the porter
has to create custom gaskets at each point the component
interfaces with hardware I/O on FPGA1 and FPGA2. The
porter is again required to have detail understanding of the
waveform properly construct the corresponding gaskets for
the hardware platform.
2-6
DEVELOPMENT GUIDELINES device, thus increasing the chance of a successful
waveform port. The HDR-RF Test Waveform is simulated
Coding for reuse must be considered at every stage of the with Mentor Graphic and Synopsys simulator, and
waveform development process to reduce overall porting synthesized to target both Altera and Xilinx FPGA family.
effort. The focus of design for reuse is minimizing the
amount of rework of the waveform components during the
hardware retargeting and repartitioning process. The
guidelines below provide one approach toward design for
reuse and waveform portability.
3-6
requirements. Second, a component developed to run at a porter. Therefore, the burden falls upon the developer to
fast clocking rate on a high-end FPGA may not work in a provide the porter with the necessary information and tools
less capable device. By limiting the operating frequency of to ensure efficient porting of the waveform. The PRT Lab
the component, the designer maximizes waveform reuse looked to industry best practice for IP delivery approach to
across a variety of commercial hardware. create a release package for HDR-RF Test Waveform.
4-6
instantiate the components contained in each FPGA the porter to the FPGA-partitioning tool and the
partition. To ensure that the waveform is properly verification facilities provided in the handoff package. It is
configured and partitioned, an RTL testbench is the porter’s guide for running the tools, the scripts, and the
automatically generated to verify the partitioned design. simulation with the waveform model. Second, the
The RTL testbench has the capability to read test vectors Application document provides the porter an overview of
and compare them against the simulated data stream. the entire waveform. The document defines the specific
Figure 4 shows an example of an RTL testbench with three static and dynamic settings of the constituent components
FPGA partitions. It is important to note that the waveform to achieve the expected system performance. The dynamic
components and the RTL top level files both use the same settings are used to configure the system during platform
common OCP interface. integration. Third, the Component document describes the
high level function and interface of each waveform
component. This document is intended to be generic, since
the component may be reused with other waveforms. For
the porter, the component document serves as additional
reference to the waveform application document.
5-6
that the waveform has been properly configured and CONCLUSION
partitioned.
To support Above 2 GHz, high bandwidth high throughput
(HBHT), high data-rate (HDR) FPGA-based waveforms,
development and delivery of the firmware for advance
MILSATCOM terminals must be standardized. The
proposed waveform design guidelines push the
requirement for scalability and configurability down to the
waveform components. The result is a waveform that is
portable from the RTL up through the SCA framework.
Combined with a structured release process, the porting of
FPGA-based waveforms becomes much more efficient and
ultimately reduces the overall schedule and cost risk
associated with complex waveforms.
Figure 5. Waveform Porting Process Using the proposed guidelines, the HDR-RF Test
Waveform has met all of its requirements and objectives
In the second stage, the porter develops the hardware on design, system performance, IP delivery and waveform
dependent gaskets to connect the FPGA partitions to their portability. The PRT Lab structured methodologies
platform specific interface. These gaskets are verified discussed in this paper serve as a starting point for a wider
using bus functional model (BFM) of the I/O and device discussion on a structured approach to portable FPGA-
transports to check the links between the waveform and based waveform development.
the platform. The gaskets connections are shown at the
bottom of Figure 5. After the waveform is tested with the
hardware testbench, the waveform is ready to be deployed REFERENCES
onto the platform. This incremental approach to
verification makes the porting process much more [1] “Component Portability Infrastructure”, Mercury
predictable. Computer System, Inc 2007
[2] Lee Pucker, Geoff Holt, “Extending the SCA Core
Even with the structured delivery and extensive Framework inside the Modem Architecture of a Software
documentation, it is not reasonable for a developer to Defined Radio”, IEEE Radio Communication March 2004
consider every possible issue the porter might face. In [3] JTRS JPEO, “Joint Tactical Radio System (JTRS)
addition to the physical delivery of the waveform, it is Standard Modem Hardware Abstraction Layer Application
necessary that the developer provide some degree of Program Interface (API)”, Version 2.11.1, May 2007.
training to the porter in the use of the environments and [4] Manuel Uhm, “The Myths and Realities of Code
waveform. Furthermore, technical support during the Portability”, Xilinx, 2008
porting process can help resolve special conditions which [5] Open Core Protocol International Partnership, see:
were not considered during initial development. Since the http://www.ocp-ip.org
waveform components are treated as black boxes by the [6] IEEE Standard SystemC Language Reference Manual,
porter, the developer may be required to make any IEEE Standard 1666-2005, 2006
changes. [7] VMware Virtual Machine
see: http:// www.vmware.com/virtualization
6-6