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http://www.ecs.umass.edu/ece/ece232/
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB
Computer Organization
5 classic components of any computer
Computer Processor (CPU) Control Memory Devices Input
Datapath
Output
x = x n1 2n1 + x n2 2n2 + L + x1 21 + x 0 20
Range: 0 to +2n 1 Example 0000 0000 0000 0000 0000 0000 0000 10112 = 0 + + 123 + 022 +121 +120 = 0 + + 8 + 0 + 2 + 1 = 1110 Using 32 bits 0 to +4,294,967,295
ECE232: Adders 3
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
decimal
-8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7
x = x n1 2
+ x n2 2
n2
+ L + x1 2 + x 0 2
1
Bit n-1 is sign bit 1/0 for negative/non-negative numbers Range: 2n 1 to +2n 1 1 Example 1111 1111 1111 1111 1111 1111 1111 11002 = 1231 + 1230 + + 122 +021 +020 = 2,147,483,648 + 2,147,483,644 = 410 Using 32 bits 2,147,483,648 to +2,147,483,647 Most-negative: 1000 0000 0000 Most-positive: 0111 1111 1111
ECE232: Adders 4
1100 1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
Signed Negation
To get X complement X and add 1 Complement means 1 0, x+x 01 Example: negate +2 +2 = 0000 0000 00102 2 = 1111 1111 11012 + 1 = 1111 1111 11102 Subtraction: y x = y + (x +1)
= 1111...1112 = 1
x + 1 = x
Sign Extension
Representing a number using more bits Preserve the numeric value Replicate the sign bit to the left Examples: 8-bit to 16-bit +5: 0000 0101 => 0000 0000 0000 0101 5: 1111 1011 => 1111 1111 1111 1011
Koren
ECE232: Adders 5
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
ECE232: Adders 6
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
ECE232: Adders 7
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
ECE232: Adders 8
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
Full adder
combinational digital circuit with input bits xi,yi and incoming carry bit ci, producing output sum bit si and outgoing carry bit ci+1 incoming carry for next FA with input bits
xi+1,yi+1
Full-Adder (FA)
Examine the Full Adder table x y Cin Cout S Cin
x 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1
Cout
y Sum
In general, for bit i: ci+1 = xi yi + ci (xi+yi) where ci+1 = Cout, ci= Cin
Half adder has 2 inputs. In principle HA is same as FA, with Cin set to 0.
ECE232: Adders 10
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass Koren
Example
x3,x2,x1,x0=1111 y3,y2,y1,y0=0001 FA - operation time - delay Assuming equal delays for sum and carry-out Longest carry propagation chain when adding two 4-bit numbers In synchronous arithmetic units time allowed for adder's operation is worst-case delay - nFA
ECE232: Adders 12
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
Example: X = 0101, Y = 0010; Compute X Y First step: Complement Y 1101 Second step: add 0101 + 1101 + 1 = 0011
ECE232: Adders 13
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass Koren
p3
g3
p2
g2
p1
g1
C4
CLL (carry look-ahead logic) Gi =Xi. Yi : generated carry ; Pi=Xi + Yi : propagated carry
ECE232: Adders 15
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
Plumbing analogy
g0 p0
c1 = g0 + c0 p0 c1
c0
g0 g1
c2 = g1 + g0 p1 + c0 p0 p1
c0 p0 p1 g1 g0 c0 p0 p1 p2 p3
c2
g2
c4 = g3 + g2 p3 + g1 p2p3 + g0 p1 p2p3 + c0 p0 p1 p2 p3
g3
c4
ECE232: Adders 16
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass Koren
X1 Y1
X0 Y0
p3
g3
p2
g2
p1
g1
p0
g0
If inputs are available at time t=0, when are p and g signals available?
C3 C2 C1
p3
g3
p2
g2
p1
g1
p0
g0 C0
ECE232: Adders 17
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
p3
g3
p2
g2
p1
g1
p0
g0 C0
ECE232: Adders 18
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
3 What What What What if if if if there there there there were were were were 6 7 8 9 inputs? inputs? inputs? inputs?
ECE232: Adders 19
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
Total Delay
X3 Y3 S3 C3 S2 X2 Y2 C2 S1 X1 Y1 C1 S0 X0 Y0 C0 p0 g0
p3
g3 CLL
p2
g2
p1
g1
C4
+3+
+2
= 7
G*
P*
What is the delay of a 5 bit CLA? 6 bit CLA? 7 bit CLA? 8 bit CLA?
ECE232: Adders 20
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass Koren
CLL
ECE232: Adders 21
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
Plumbing Analogy
p0 p1 p2 p3
P*0
g0
g1 g2
p1 p2
g3
G*0
p3
ECE232: Adders 22
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
n-bit adder
n-bit adder
n-bit adder
n-bit adder
n-bit adder
MUX
Cout
ECE232: Adders 23
Carry-select adder
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass Koren
Summary
Throw hardware for performance Ripple Carry: least hardware, slowest CLA: faster, more hardware Carry Select: even faster, even more hardware Other techniques available, e.g., Carry skip adder See http://www.ecs.umass.edu/ece/koren/arith/simulator/ Combination of these techniques hybrid adders
ECE232: Adders 24
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
ECE232: Adders 25
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren
ECE232: Adders 26
Adapted from Computer Organization and Design, Patterson & Hennessy, UCB and Kundu, UMass
Koren