Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

FEATURES
Trench technology Low on-state resistance Fast switching High thermal cycling performance Low thermal resistance

BSP100

SYMBOL
d

QUICK REFERENCE DATA

VDSS = 30 V ID = 6 A
g

RDS(ON) 100 m (VGS = 10 V) RDS(ON) 200 m (VGS = 4.5 V)

s

GENERAL DESCRIPTION
N-channel enhancement mode field-effect transistor in a plastic envelope using trench technology. Applications: Motor and relay drivers d.c. to d.c. converters Logic level translator The BSP100 is supplied in the SOT223 surface mounting package.

PINNING
PIN 1 2 3 4 gate drain source drain (tab) DESCRIPTION

SOT223
4

LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

DM

PD Tj, Tstg

Pulsed drain current Total power dissipation Operating junction and storage temperature

Tsp = 25 C Tsp = 25 C

- 65

24 8.3 150

A W C

THERMAL RESISTANCES
SYMBOL Rth j-sp Rth j-amb PARAMETER Thermal resistance junction to solder point Thermal resistance junction to ambient CONDITIONS surface mounted, FR4 board surface mounted, FR4 board TYP. 12 70 MAX. 15 UNIT K/W K/W

1 Continuous current rating limited by package February 1999 1 Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER EAS IAS Non-repetitive avalanche energy Non-repetitive avalanche current CONDITIONS Unclamped inductive load, IAS = 6 A; tp = 0.2 ms; Tj prior to avalanche = 25C; VDD 15 V; RGS = 50 ; VGS = 10 V MIN. -

BSP100

MAX. 23 6

UNIT mJ A

ELECTRICAL CHARACTERISTICS
Tj= 25C unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) gfs ID(ON) IDSS IGSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage Drain-source on-state resistance CONDITIONS VGS = 0 V; ID = 10 A; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C VGS = 10 V; ID = 2.2 A VGS = 4.5 V; ID = 1 A VGS = 10 V; ID = 2.2 A; Tj = 150C Forward transconductance VDS = 20 V; ID = 2.2 A On-state drain current VGS = 10 V; VDS = 1 V; VGS = 4.5 V; VDS = 5 V Zero gate voltage drain VDS = 24 V; VGS = 0 V; current VDS = 24 V; VGS = 0 V; Tj = 150C Gate source leakage current VGS = 20 V; VDS = 0 V Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 2.3 A; VDD = 15 V; VGS = 10 V MIN. 30 27 1 0.4 2 3.5 2 TYP. MAX. UNIT 2 80 120 4.5 10 0.6 10 6 0.7 0.7 6 8 21 15 2.5 5 250 88 54 2.8 3.2 100 200 170 100 10 100 V V V V V m m m S A A nA A nA nC nC nC ns ns ns ns nH nH pF pF pF

VDD = 20 V; RD = 18 ; VGS = 10 V; RG = 6 Resistive load Measured tab to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Tsp = 25 C MIN. IF = 1.25 A; VGS = 0 V IF = 1.25 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V -

BSP100

TYP. MAX. UNIT 0.82 69 55 6 24 1.2 A A V ns nC

120 110 100 90 80 70 60 50 40 30 20 10 0

PD%

Normalised Power Derating

100 Peak Pulsed Drain Current, IDM (A) RDS(on) = VDS/ ID tp = 10 us 10 100 us d.c. 1 ms 10 ms 100 ms BSP100

0.1

20

40

60

80 Tsp / C

100

120

140

10 Drain-Source Voltage, VDS (V)

100

Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Tsp)

Fig.3. Safe operating area. Tsp = 25 C ID & IDM = f(VDS); IDM single pulse; parameter tp

120 110 100 90 80 70 60 50 40 30 20 10 0

ID%

Normalised Current Derating

100 Peak Pulsed Drain Current, IDM (A) BSP100

10

D = 0.5 0.2

0.1 0.05 P D tp D = tp/T

0.1

0.02 single pulse T 1E-03 1E-02 1E-01 1E+00 1E+01

0.01 1E-06

1E-05

1E-04

20

40

60

80 100 Tsp / C

120

140

Pulse width, tp (s)

Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Tsp); conditions: VGS 10 V

Fig.4. Transient thermal impedance. Zth j-sp = f(t); parameter D = tp/T

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

BSP100

1E-01

Sub-Threshold Conduction
10 9

Source-Drain Diode Current, IF (A) VGS = 0 V

1E-02 min typ max

8 7 6 5 4 Tj = 25 C 3 2 1 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5

1E-03

150 C

1E-04

1E-05

1E-06

Drain-Source Voltage, VSDS (V)

Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS

Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj

Non-repetitive Avalanche current, IAS (A) 10 BSP100 25 C

Capacitances, Ciss, Coss, Crss (pF) 1000

Ciss 1 100 Coss Crss

VDS

Tj prior to avalanche =125 C

tp ID

10 0.1 1 10 Drain-Source Voltage, VDS (V) 100

0.1 1E-06

1E-05

1E-04 Avalanche time, tp (s)

1E-03

1E-02

Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz

Fig.15. Maximum permissible non-repetitive avalanche current (IAS) versus avalanche time (tp); unclamped inductive load

Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 2.3A Tj = 25 C VDD = 15 V

4 5 6 7 Gate charge, QG (nC)

10

Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG); parameter VDS

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

PRINTED CIRCUIT BOARD

BSP100

Dimensions in mm.
36

18

60 9 4.6 4.5

10

7 15 50

Fig.16. PCB for thermal resistance and power rating for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 m thick).

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

MECHANICAL DATA
Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223

BSP100

c y HE b1 v M A

Q A A1

1
e1 e

2
bp

3
w M B detail X

Lp

2 scale

4 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A 1.8 1.5 A1 0.10 0.01 bp 0.80 0.60 b1 3.1 2.9 c 0.32 0.22 D 6.7 6.3 E 3.7 3.3 e 4.6 e1 2.3 HE 7.3 6.7 Lp 1.1 0.7 Q 0.95 0.85 v 0.2 w 0.1 y 0.1

OUTLINE VERSION SOT223

REFERENCES IEC JEDEC EIAJ

EUROPEAN PROJECTION

ISSUE DATE 96-11-11 97-02-28

Fig.17. SOT223 surface mounting package.

Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Discrete Semiconductor Packages, Data Handbook SC18. 3. Epoxy meets UL94 V0 at 1/8".

February 1999

Rev 1.000

Philips Semiconductors

Product specification

N-channel enhancement mode TrenchMOS transistor

DEFINITIONS
Data sheet status Objective specification Product specification Limiting values

BSP100

This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications.

Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.

Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.

February 1999

Rev 1.000

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