Voyager - The Journal of Computer Science and Information Technology ISSN 0973-4872, Vol. 3, No.1 (2006) pp.

67-69 Institute of Technology & Management

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AUTOMATIC TEST PATTERN GENERATION

Ms. Bhawna Saxena
Sr. Lecturer, CSE & IT

Introduction
Automatic Test Pattern Generation (ATPG) is the process of automatically generating input patterns or sequences that help in checking for the existence of fault(s) in a VLSI circuit. The input patterns are randomly generated and applied to the circuit, and the response of the circuit to each pattern is compared with the expected response from a faultfree circuit. A difference in the circuits response and the expected response indicates the existence of a fault in the circuit. An input pattern which when applied to the circuit generates a response that is different from the expected response and enables the testers to differentiate the correct circuit behavior from the faulty circuit behavior is known as a Test Pattern. The effectiveness of the ATPG process is measured by the fault coverage, the number of patterns generated, and the cost of performing the test.

Figure 1: Circuit diagram (Signal Line E is stuck-at 1)

In the absence of any fault, the correct behavior of the circuit would be as shown by the data in the table given below:

The Stuck-At Fault

A fault model is a hypothesis of how the circuit behavior may go wrong during the manufacturing process [2]. The most commonly used fault model is the single stuck-at fault model. In this model, one of the signal lines in the circuit is assumed to be stuck-at a particular logic value, 0 or 1. Regardless of the inputs supplied to the circuit, this signal line always has the same value at which it is stuck, i.e., stuck-at 0 or stuck-at 1. Consider the circuit shown in Figure 1. The signal lines A, B, C, and D are the Primary Inputs (PIs), and the signal line G is the Primary Output (PO).

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Now assume that the signal line E of the circuit is stuck-at 1, then the corresponding faulty behavior of the circuit would be as shown in table below:

When creating an input pattern, the process being followed should be efficient in terms of memory space, time, and the cost of performing the test. The aim of the process should be to generate the minimum possible set of patterns needed to detect the fault(s). The pattern generation process is basically a mathematical process that can be carried out either manually or algorithmically.

Algorithmic Methods
Testing VLSI circuits for fault detection is a hard (NP-complete) problem [5] and conventionally, the generation of tests is characterized as a search of N-dimensional 0-1 state space, where N is the number of primary inputs to the circuit to be tested. Therefore, many different approaches to ATPG have been devised to perform fault detection in both sequential and combinatorial circuits. Some popular ATPG algorithms are: D Algorithm: This was the first practical test generation algorithm devised in 1966 by Roth at IBM. The D algorithm introduced the D Notation, which continues to be used in most ATPG algorithms [2]. D has the value 1 in a good circuit and 0 in a faulty one. D (which is the opposite of D) has the value 0 in case of a good circuit and 1 for a faulty circuit. Path Oriented Decision Making (PODEM): This algorithm is an improvement over the D algorithm. PODEM was developed in 1981 by Goel, to address a problem that the D algorithm had with XOR gates [2]. Fan-Out Oriented (FAN): This algorithm is an improvement over PODEM. It limits the ATPG search space to reduce computation time and accelerates backtracking [2]. Pseudorandom test generation: This technique is the simplest method of creating tests. It uses a pseudorandom number generator for generation input patterns [2].

In case of the fault free circuit, the output for the input patterns 0000, 0100, and 1000 is 0, whereas with the presence of the stuck-at 1 fault at signal line E, the output for these patterns is 1. The input patterns 0000, 0100, and 1000 are thus the test patterns as they are enabling the tester in the detection of the faulty circuit behavior. ATPG Cycle The ATPG Cycle consists of three phases: (i) input pattern generation, (ii) input pattern application, and (iii) test pattern identification. During pattern generation a model of the circuit is first developed at the gate or transistor level. Thereafter, the input patterns are generated randomly by assigning the logic values (0,1) in different combinations at the Primary Inputs. The input patterns are then applied sequentially to the circuit. The response obtained at the Primary Output(s) of the circuit is compared with the expected response (of a fault-free circuit) and the test pattern(s) is/ are reached at.

The first three of the above mentioned algorithmic methods are complex, compute-intensive processes which in then case of complex circuits can be quite expensive and thus no longer feasible or practical. On the other hand, pseudorandom test generation is a comparatively simpler and inexpensive method that proves useful in the initial phases of test

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generation process to handle easy-to-detect faults. For faults not covered by the pseudorandom method, algorithmic methods have to be used. The algorithmic methods are deterministic in nature, as they generate the patterns in a systematic manner, whereas, the pseudorandom method is probabilistic in nature, as they generate the patterns by chance.

ATPG as Energy Minimization Problem

A pseudorandom technique for ATPG is the Optimization method. According to the Optimization method the test pattern generation problem can be formulated as an Energy Minimization Problem [3], [4]. For this a given VLSI with a specified fault, an Automatic Test Generation (ATG) network is first created. The ATG network is then transformed into a Hopfield neural network. An energy equation corresponding to this neural network is then derived. This energy equation is basically a polynomial equation of k variables, where k is the number of neurons in the corresponding neural network. A characteristic of this equation is that the variables can take a Boolean value only, i.e., the neurons can have an activation value of either 0 or 1. The input patterns generated are then sequentially applied to the energy equation. The test pattern(s) for the circuit can then be obtained by optimizing the value of the derived energy equation to a global minimum. The optimization approach is usually based on heuristic methodologies like genetic algorithms, simulated annealing theory, etc.

problems like testing of VLSI circuits. Depending upon the level of complexity of the circuit and the required fault coverage, either an algorithmic or pseudorandom method for ATPG can be adopted. To make the process more efficient in terms of space, time, and cost a distributed/ parallel environment can be used. Today, when the Grid computing paradigm is fast picking up, we need to develop and use distributed/ parallel algorithms to solve such compute-intensive problems that support adaptive parallelism. The availability of affordable parallel machines and distributed networks of idle workstations has opened a new front for the development of efficient distributed/ parallel algorithms for complex large scale techniques like Automatic Test Pattern Generation.

References
1. http://www.semiconfareast.com/atpg.htm 2. h t t p : / / e n . w i k i p e d i a . o r g / w i k i / Automatic_test_pattern_generation 3. S. T. Chakradhar, M. L. Bushnell, and V. D. Agarwal,Neural Models and Algorithms for Digital Testing, Kluwer Academic Publishers. 4. S. T. Chakradhar, M. L. Bushnell, and V. D. Agarwal, Towards massively parallel automatic test generation, IEEE Transactions on Computer-Aided Design, Vol. 9, No. 9, Sept. 1990, 2235-2258. 5. O. H. Ibarra and S. K. Sahni, Polynomially Complete Fault Detection Problems, IEEE Transactions on Computer, Vol. C-24, No. 3, pp. 242-249, March 1975.

Conclusion
ATPG is a feasible and practical approach to fault detection in the case of complex, NP-complete