Professional Documents
Culture Documents
Outline
SI + PI = EMI
These disciplines are no longer independent of each other
Fundamentals of EMI
Where does it come from and how is it minimized Five Step EMC Design Flow
Display Panel
Control IC
Memory
Driver IC
Power Integrity
Electromagnetic Interference
PCB
Power Supplies
Coupling process
Conduction EMI EMIFilters Filters Capacitive Shields Shields Inductive Space & Field
Conductive
Radiative
High Frequency
Shields Shields
A victim device
Differential mode current flows --- Loop Common mode current flows --- Open We can see Common mode current is more serious than Normal mode.
Antenna theory
-A Differential mode current flow -A Common mode current flow Loop antenna theory Dipole antenna theory
4 10 7 ( f Il ) sin E= r
r Length :l
FCC B level Mag. E limit :40dBuV/m @ 3m Mag. E( Loop antenna) : 20mA Mag. E( Dipole antenna) : 8uA
2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary
Impedance Analysis Planes deliver power to ICs and return path for signal Ensure that Plane impedance is smooth and low over broad frequency range
Resonance Analysis
Signal Extraction
Emissions Analysis
Enclosure Simulation
Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis
Enclosure Simulation
Impedance Analysis
Resonance Analysis
Signal Extraction If signal is not at the receiver, it went somewhere else Ensure clean signal transmission and good return path for critical nets Enclosure Simulation
Emissions Analysis
Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis
Non-ideal planes and tight routing can lead to unintentional signals Ensure there are no unintentional radiators
Enclosure Simulation
Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis Real enclosures are non-ideal and can pass radiation Ensure minimal radiation from PCB escapes the chassis holes
Enclosure Simulation
PI Methodology
Signal Integrity
Power Integrity
Electromagnetic Interference
Power Integrity A Case Study Active devices require clean power to operate correctly Power distribution system (PDS) design engineers must ensure that all parts receive voltage between certain limits and that noise is kept sufficiently low Todays designs with many separate power domains of high current and low voltage devices complicate power integrity analysis
Start
Finish Yes
No
Mag. of Z
ZTarget =
|Z|
f
1 GHz
1KHz 1MHz 100MHz
High Frequency Ceramic Capacitors Power/Ground Planes Buried Capacitance
Defining the Target Impedance To define the target impedance we need to consider two factors:
VRM
VRM
Peak current
Determines maximum impedance
Package Model
C58 Cpkg L59 Lpkg R60 0 Rpkg 0 V35
logic_in enable pullup
Name=vrm
Spectral power
Determines cutoff frequency
Driver
R5
pulldown
50
VRM
VRM
io out_of_in
V33
DC=VCC 0
Driver Current
Curve Info mag(Ipositive(vrm)) Transient
Driver
max 37.8706
35.00
30.00
mag(Ipositive(vrm)) [mA]
25.00
20.00
15.00
10.00
5.00
0.00 0.00 5.00 10.00 15.00 20.00 25.00 Time [ns] 30.00 35.00 40.00 45.00 50.00
Driver Spectrum
Ansoft Corporation
1.00E-003
XY Plot 4
Driver
1.00E-004
667 MHz
1.00E-005
Curve Inf o
1.00E-006
1.00E-007
1.00E-008
1.00E-009
1.00E-010
1.00E-011
1.00E-012 0.00 0.20 0.40 0.60 0.80 1.00 Spectrum [GHz] 1.20 1.40 1.60 1.80 2.00
1 0.9 0.8
CDF
C D F
0.2
0.4
0.6
0.8
1 Frequency [GHz]
1.2
1.4
1.6
1.8
J5_VCC
VCC_U41-2
VCC_U41-2
Driver
pullup
Board
VCC_U41-44 VCC_U41-63 VCC_U41-84 VCC_U41-44 VCC_U41-63 VCC_U41-84
J5_VCC
logic_in enable
io
50
V35
out_of_in
R5
pulldown
x6
J5_VCC
800 Mbps data rate DDR2 IBIS driver into ideal termination used as load for PDS Package decoupling modeled using a capacitor w/ ESR, ESL
VRM
V33
DC=VCC 0
U41 Power
Bulk
Bulk Only
~11-12 ns period
2.20
V(VCC_U41-2) Transient V(VCC_U41-21) Transient V(VCC_U41-42) Transient V(VCC_U41-44) Transient V(VCC_U41-63) Transient
0.6787
0.6995
0.8191
2.00
0.7597
0.7882
Y 1 [V ]
1.80
V(VCC_U41-84) Transient
0.6858
1.60
1.40
3Meter FF
Choosing a Decoupling Capacitor To reduce the effect of a resonance, choose a capacitor with a low impedance at the resonant frequency
22 nF Capacitor
No Resonance @ 50 MHz
U41 Power
HF1
Bulk Only
V(VCC_U41-2) 0.6481 Transient V(VCC_U41-21) 0.6979 Transient V(VCC_U41-42) 0.8802 Transient V(VCC_U41-44) 0.9182 Transient V(VCC_U41-63) 0.6925 Transient
2.20
2.00
Y1 [V]
1.80
1.60
1.40
1.20 0.00
3Meter FF
Extending Low Impedance 10 1.2 nF capacitors were added across the board to extend minimum high-frequency impedance 1.2 nF capacitor was chosen due to low impedance at 200 MHz 4 of these were located near U41
HF 1 vs. HF 2
Ansoft Corporation
2.40
U41 Power
Curve Info V(VCC_U41-2) Transient pk2pk
HF2
0.2552
2.20
0.2857
0.2930
2.00
0.4047
0.3083
Y1 [V]
1.80
V(VCC_U41-84) Transient
0.3359
1.60
1.40
Removing a Resonance Six 8 nF capacitors were added near U41 to cancel resonance at 80 MHz
Added capacitors
U41
HF 2 vs. HF 3
Ansoft Corporation
2.40
U41 Power
Curve Info V(VCC_U41-2) Transient
Final
pk2pk
0.2416
2.20
0.2685
0.2660
0.3264
0.3709
Y1 [V]
1.80
V(VCC_U41-84) Transient
0.3142
1.60
1.40
Buried Capacitance
Due to parasitic inductance it is impossible to decouple the board with capacitors at frequencies greater than a few hundred MHz Using a thinner dielectric layer between power and ground planes introduces additional capacitance and reduces high frequency impedance
A C = d
Ansoft, LLC Proprietary
Specification Met!
Ansoft Corporation
2.40
U41 Power
Curve Info V(VCC_U41-2) Transient
Buried
pk2pk
2.20
0.2177
0.2295
0.2418
2.00
0.2549
0.2729
Y 1 [V ]
1.80
V(VCC_U41-84) Transient
0.2169
1.60
3Meter FF
Conclusions SI / PI / EMI are all based on the same electromagnetic fundamentals and cannot be separated Impedance and resonant mode simulations connect the frequency domain to the spatial domain and allow selection of capacitor value and placement Frequency domain extractions are useful for quickly optimizing PDS designs, but time domain simulations are necessary to ensure compliance with device specs Using a single design environment can help reuse the same models for SI/PI/EMI simulations
2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary
Questions
Any Questions?
SI + PI = EMI
SIGNAL INTEGRITY
Trend: Cost / Performance targets drive the integration of ICs, SoCs, and SiPs onto low cost printed circuit boards. Chip/Package/Board Co-design is required
EMC/EMI
Far Field - CPM2 - 1.27v Baseline
60.00 50.00 40.00 30.00 20.00 10.00 0.00 -10.00 -20.00 0.00
dBuV/m_
0.50
1.00
GHz
1.50
2.00
POWER INTEGRITY
Differential signaling is a standard to improve signal-tonoise ratios, however, its use always leads to Common mode noise
Common Mode Conversion
SCD11=0.5*(S(1,1)-S(1,3)+S(3,1)-S(3,3)) SCD21=0.5*(S(2,1)-S(2,3)+S(4,1)-S(4,3))
Where is the problem? Unintentional Signaling Common mode will always exist
Common Mode noise is the main contributor to EMI
Crosstalk Definition and Sources Signal integrity examines the quality of transmitted waveforms through a physical interconnect; Traces, connectors, vias, etc Crosstalk is the coupling of energy from one current carrying conductor to another. It occurs when the electromagnetic fields from one conductor interferes with another conductor, thus changing its desired characteristics There are 2 main components to Crosstalk:
Mutual Inductance and Mutual Capacitance
Terminated Victim
Driven Line
Zo
Far End
Vinput LM CM A= + L C 4
TD
TD = X LC
B= Vinput X LC LM C M L C 2Tr
A B
Near End
Zo
ZO =
L C
Tr
~Tr
Tr
Source signal Far End of Source Signal Near-end X-talk Far-end X-talk
L /inch=
Trace Width Height Trace Separation Thickness Dk 13mil 10mil 7mil 2mil 3.55
C/inch=
ZO =
Tr ~Tr
Tr
Trace Spacing= 7, 12, 17, 22, 27mil As Length increases, Ifar accumulates As Trace Spacing increases, Inear decreases
Increase
Decrease
NE
FE
NE
FE
Electric Field
Electric Field
Near-End Probe
Near-End Probe
Far-End Probe
Total length of parallel via routing is 4% of the total length. Yet the Near-End Crosstalk only reduces by 24%. The Far-End Crosstalk only reduces by 8%
Near-End Probe
2008 Ansoft, LLC All rights reserved.
Far-End Probe
Signal Integrity
Power Integrity
Electromagnetic Interference
S.O.C. Database
CPM
Package Database
PCB Database
S-Parameters SIwave
Nexxim Designer
FrequencyDomain Voltages
Resonance Analysis Impedance Analysis Near field plots Far field plots
Ansoft, LLC Proprietary
Package has been merged onto board Coupling between the bondwires, leadframe, and board are simulated
2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary
CPM
VDD
I/O Interface
VDDQ
Chip Power Model
Package PCB
SIG
VSS
Terminations
Drive VDDs with CPM Capture coupled highfrequency noise Run Near/Far-Field Simulations using transient results
dBuV/m__
0.5
1
G H z
1.5
Baseline
1.27 V w/ Decap
1.1 V
Signal Integrity
Power Integrity
Electromagnetic Interference
Driver settings
27
2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary
Time
28
2008 Ansoft, LLC All rights reserved.
Frequency
Radiation
Ansoft, LLC Proprietary
SIwave
Original Driver
Ideal Driver
Pi Filter added to driver output to squelch higher harmonics of 13.56 MHz clock
Ideal Driver
Filtered Driver Signal integrity still OK but high frequency spectrum is reduced