Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks

AIM: The main aim of the project is to design Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks.

A!S"RAC"# In this paper we introduce a new flip-flop for use in a lowswing LC resonant clocking scheme. The proposed low-swing differential conditional capturing flipflop (LS- CC!!" operates with a low-swing sinusoidal clock through the utili#ation of reduced swing in$erters at the clock port. The functionalit% of the proposed flip-flop was $erified at e&treme corners through simulations with parasitics e&tracted from la%out. The LS- CC!! ena'les (.)* reduction in power compared to the fullswing flip-flop with +,* area o$erhead. In addition- a fre.uenc% dependent dela% associated with dri$ing pulsed flip-flops with a lowswing sinusoidal clock has 'een characteri#ed. The LS- CC!! has /01 ps longer data to output dela% as compared to the full-swing flip-flop at the same setup time for a +11 23# sinusoidal clock. The functionalit% of the proposed flip-flop was tested and $erified '% using the LS- CC!! in a dual-mode multipl% and accumulate (24C" unit fa'ricated in TS2C ,1-nm C25S technolog%. Lowswing resonant clocking achie$ed around )./* reduction in total power with ).0* area o$erhead for the 24C.
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$roposed Met%od: In this paper LS- CC!! was implemented using TS2C ,1 6nm further we can implement with lower technolog% li'rar%. !urther we can appl% low power techni.ues to reduce static power.

Ad&antage: The LS- CC!! ena'les (.)* reduction in power compared to the fullswing flipflop with +,* area o$erhead. The functionalit% of the proposed flip-flop was tested and $erified '% using the LS- CC!! in a dual-mode multipl% and accumulate (24C" unit fa'ricated in TS2C ,1-nm C25S technolog%. Low-swing resonant clocking achie$ed around )./* reduction in total power with ).0* area o$erhead for the 24C. !L'C( DIA)RAM:

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Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

!ig. + LS7 CC!!

!ig.8 modification to ena'le full- and low-swing flip-flop clocking

V.Mallikarjuna (Project manager)

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Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

"''LS9 hspice7$4-811/.1:- t-spice R*F*R*NC*: ;+< S. . =aff#iger and >. 3ammond- The implementation of the ne&tgeneration

(? ' Itanium@ microprocessor- in ig. Tech. Aapers- IBBB Int. Solid-State Circuits Conf.- 8118- pp. :??6?08. ;8< C. C. 4nderson- C. Aetro$ick- C. 2. Deat%- C. Earnock- >. =uss'aum- C. 2. Tendier- C. Carter- S. Chu- C. Cla'es- C. ilullo- A. udle%- A. 3ar$e%- F. DrauterC. LeFlanc- L. Aong-!ei- F. 2cCredie- >. Alum- A. C. Gestle- S. Gun%on- 2. Scheuermann- S. Schmidt- C. Eagoner- G. Eeiss- S. Eeit#el- and F. HoricAh%sical design of a fourth-generation A5EBG >3# microprocessor- in ig. Tech. Aapers- IBBB Int. SolidState Circuits Conf.- 811+- pp. 8:868::. ;:< I. !. Aa$lidis- I. Sa$idis- and B. >. !riedman- Clock distri'ution networks in :integrated s%stems-IBBB Trans. Ier% Large Scale Integr. (ILSI" S%st.+1.++1,JTILSI.81+1.810:08? . ;?< 4. C. rake- D. C. =owka- T. K. =gu%en- C. L. Furns- and G. F. Frown-

Gesonant clocking using distri'uted parasitic capacitance-IBBB C. Solid-State Circuits- $ol. :,- no. ,- pp. +)816+)8/- Sep. 811?. ;)< C. Dim and S. 2. Dang- 4 low-swing clock dou'le-edge triggered flip-flop- inAroc. S%mp. ILSI Circuits- 811+- pp. +/:6+/(.

V.Mallikarjuna (Project manager)

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Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &