VLSI implementation of Fast Addition using Quaternary Signed Digit Number System AIM: The main aim of the

project is to design VLSI implementation of Fast Addition using Quaternary Signed Digit Number System A!S"#A$": With the binary number system, the computation speed is limited by formation and propagation of carry especially as the number of bits increases. Using a quaternary Signed Digit number system one may perform carry free addition, borrow free subtraction and multiplication. Howe er the !SD number system requires a different set of prime modulo based logic elements for each arithmetic operation. " carry free arithmetic operation can be achie ed using a higher radi# number system such as !uaternary Signed Digit $!SD%. &n !SD, each digit can be represented by a number from '( to (. )arry free addition and other operations on a large number of digits such as *+, ,-., or more can be implemented with constant delay and less comple#ity. Design is simulated / synthesi0ed using 1odelsim*.2, 1icrowind and 3eonardo Spectrum.

V.Mallikarjuna (Project manager)

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Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

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4ig5 Data 4low of single digit !SD adder cell.

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V.Mallikarjuna (Project manager) Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

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6ilin# 7.-&S8, 1odelsim*.+c.

A((LI$A"I%N ADVAN"A')S: The design of !uaternary Signed Digit adder using 9"9D'9"9D implementation for single digit addition, the dynamic power dissipation is (*.-::uWat :;H0 frequency. These circuits consume less energy and less energy and power, and shows better performance. The delay of the proposed design is -ns. #)F)#)N$)S: ". " i0inis <signed digit number representation for fast parallel arithmetic=, &>8 Transactions on 8lec. )omp..?ol 8)',2,pp (.7'+22. ".".S. "wwal and @.U. "hmed, <fast carry free adder design using !SD number system ,=proceedings of the &888 ,77( national aerospace and electronic conference, ol -,pp ,2.:',272. Aehroo0 perhami <generali0ed signed digit number systems, a unifying frame worB for redundant number reperesentation <.&888 transactions on computers, ol (7,no.,,pp..7'7..
V.Mallikarjuna (Project manager) Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

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 C. &shi0uBa, ". Chta, D. Tannno, E. Tang, D. HandoBo, <?3S& design of a quaternary multiplier with direct generation of partial products,= Froceedings of the -Gth &nternational Symposium on 1ultiple'?alued 3ogic, pp. ,*7',G+. ".".S "wwal, Syed 1. 1unir, ".T.1. Shafiqul Dhalid, Howard 8. 1ichel and C. 9. ;arcia, <1ulti alued Cptical Farallel )omputation Using "n Cptical Frogrammable 3ogic "rray=, &nformatica, ol. -+, 9o. +, pp. +*G' +G(.

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &