FinFETs and Their Futures

N. Horiguchi, B. Parvais, T. Chiarella, N. Collaert, A. Veloso, R. Rooyackers, P. Verheyen, L. Witters, A. Redol, A. De Keersgieter, S. Brus, G. Zschaetzsch, M. Ercken, E. Altamirano, S. Locorotondo, M. Demand, M. Jurczak, W. Vandervorst, T. Hoffmann and S. Biesemans

Abstract FinFET is a promising device structure for scaled CMOS logic/memory applications in 22 nm technology and beyond, thanks to its good short channel effect (SCE) controllability and its small variability. Scaled SRAM and analog circuit are promising candidates for nFET applications and some demonstrations for them are already reported. On the other hand, for nFETs production, quite a lot of process challenges are required due to difcult n/gate patterning in the 3D structure, conformal doping to n and high access resistance in extremely thin body, etc. The n/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in nFETs. High access resistance is reduced by junction optimization and strain boaster technique.

1 Introduction
VLSI performance is improved by planar device scaling according to Moores law for past decades. However, for 22 nm technology and beyond, it is very difcult to meet ITRS targets, especially short channel effect (SCE) control and suppression

N. Horiguchi (&), B. Parvais, T. Chiarella, N. Collaert, A. Veloso, R. Rooyackers, P. Verheyen, L. Witters, A. Redol, A. De Keersgieter, S. Brus, M. Ercken, E. Altamirano, S. Locorotondo, M. Demand, M. Jurczak, T. Hoffmann and S. Biesemans IMEC VZW, Leuven, Belgium e-mail: horiguc@imec.be G. Zschaetzsch and W. Vandervorst Instituut voor Kern-en Stralingsfysica, K. U. Leuven, Leuven, Belgium

A. Nazarov et al. (eds.), Semiconductor-On-Insulator Materials for Nanoelectronics Applications, Engineering Materials, DOI: 10.1007/978-3-642-15868-1_7, Springer-Verlag Berlin Heidelberg 2011

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of device performance variability, by planar device scaling. Therefore, there is a strong interest in new device architectures. FinFET is one of the most promising device structures for scaled CMOS/memory applications thanks to its good SCE controllability and its small variability. However, the future of nFET is not so obvious due to difcult patterning (3D structure), difcult doping on n structure and high access resistance in extremely thin body, etc. This paper describes the nFET device characteristics, promising nFET applications and process challenges for the nFET future.

2 FinFET Device Characteristics

FinFET has a so-called double gate structure (Fig. 1). Thanks to the double gate structure, nFET has a good channel potential control by gate electrode [1].
Fig. 1 Device structure of nFET. FinFET has a double gate structure, which enables better SCE control

Fig. 2 Vt roll-off comparison between nFETs and planar FETs. FinFETs show better SCE control and comparable Vt at long gate length without hik capping such as LaO or AlO

FinFETs and Their Futures Fig. 3 Matching characteristics of planar FETs, SOI nFETs (FF) and bulk nFETs (BFF). SOI FF shows better matching thanks to low channel dopant concentration

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Fig. 4 Ion-Ioff in nFETs and planar FETs. Ion difference between nMOS and pMOS is smaller due to n sidewall crystal orientation

This enables better SCE control in nFET than that in single gate planar FET. This is a big advantage in nFET for the device scaling. Figure 2 shows the Vt roll-off comparison between nFET and planar FET [2, 3]. FinFETs show better SCE control as expected. Another advantage in nFET is the threshold voltage (Vt) control in high-k/metal gate stack. No high-k capping layer (La2O3 for nMOS or Al2O3 for pMOS) is necessary for nFETs to obtain comparable Vt at long gate length with planar FETs that use dual capping layers. This enables simpler process integration in nFETs. Thanks to the good channel potential control by the double gate structure, high channel dopant concentration is not necessary for nFET to suppress the SCE. The low channel dopant concentration makes the nFET device variability smaller than planar FET in scaled technology. This can be seen in the good matching

144 Fig. 5 Ring oscillator (RO) delay versus n number ratio between nnFET and pnFET. Minimum RO delay is achieved around the n number ratio of 1

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characteristics (Fig. 3). Once the channel dopant concentration is increase, the matching degradation can be seen clearly even in nFET device structures. In nFETs fabricated on conventional (100)/\110[ substrate, the Ion difference between nMOS and pMOS becomes smaller (Fig. 4) since the (110)/\110[ n sidewall orientation increases pMOS mobility signicantly and decreases nMOS mobility slightly [4]. The smaller Ion difference in nFET impacts directly on the optimum NMOS/PMOS ratio in a CMOS layout (Fig. 5) [5].

3 Promising Applications for nFETs 3.1 SRAM

Device variability is a big concern for further scaling of planar bulk 6T-SRAM. FinFET has a chance to break through the barrier by its good SCE controllability and its good matching. Superior Vt-matching, Vdd-scalability and read current improvement in nFET SRAMs are reported [6]. Sub 0.1 lm2 nFET 6T-SRAMs are demonstrated already (Figs. 6, 7) [79].

3.2 Analog
The good SCE control in nFETs is benecial not only for digital but also for analog applications. By optimizing the process, nFETs show higher voltage gain and higher transconductance than planar FETs (Fig. 8) [2]. Several analog circuits, such as operational ampliers, comparators and VCOs [10], have been demonstrated.

FinFETs and Their Futures Fig. 6 SEM picture of 0.089 lm2 nFET 6T-SRAM

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Fig. 7 Buttery curves in 0.089 lm2 SRAM cell using nFETs

1.2 1 0.8

Vout (V)

0.6 0.4 0.2 0 0 0.2 0.4 0.6 0.8 1 1.2

Vin (V)

4 Process Challenges for nFET Future 4.1 Fin Patterning

Although nFETs have an intrinsically small variability due to the good channel potential control by the double gate structure and the low channel dopant concentration, their variability is dramatically inuenced by n/gate patterning. And the patterning becomes more difcult in the dens nFET structures such as scaled SRAMs. Therefore, the precise n/patterning control is a key for nFET future. Figure 9 shows n patterning improvement in nFET 6 transistor (6T)-SRAM by using thinner BARC/photo resist/hard mask stack and a new etch chemistry/ sequence [11]. The thinner resist/hard mask reduces the aspect ratio (Total thickness of n, hard mask and BARC/photo resist/n width or n space) for the n patterning. This improves the n cd/prole control.

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Fig. 8 Voltage gain (Av) versus transconductance (gm) in planar FETs and nFETs. Optimized nFETs show higher Av and higher gm

Fig. 9 Fin patterning optimization for dense SRAM. Thinner photo resist/hard mask and new etch chemistry improve n cd/line edge roughness (LER) control

In addition to that, the etch by-product control is important for n cd/prole control. Generally speaking, if too much non-volatile by-product is created during n etch and deposited n side wall, the narrow n cd control becomes very difcult. This has to be taken into account when the etch chemistry is chosen.

FinFETs and Their Futures Fig. 10 Possible mechanism for n prole degradation by carbon containing etch byproduct. If a-C is exposed to the etch chemistry, a carbon containing etch by-product is created. The by-product attached to n foot. This causes the n footing. To avoid the n footing, precise hard mask thickness control during n etch is necessary

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To get a straight n prole in the narrow n, the remaining hard mask thickness control during n etch is important. Figure 10 shows the n prole degradation by carbon containing etch by-product. If a-C hard mask is exposed to the etch chemistry (after full consumption of SiOC hard mask), the carbon containing byproduct is created and deposited at n foot. This causes the n footing. On the other hand, if the remaining SiOC hard mask is too thick, n cd loss during SiOC hard mask removal becomes signicant. This makes the n cd control difcult, especially in dense n patterns. To avoid these problems, the remaining SiOC hard mask thickness has to be controlled precisely during n etch. Figure 11 shows the comparison between optimized and non-optimized n etch from the remaining SiOC hard mask thickness control view point. The optimized n etch gives better n prole. The line edge roughness (LER)/line width roughness (LWR) improvements in the n by using a spacer dened patterning are reported [12, 13].

4.2 Gate Patterning

In the gate etch in nFETs, both the gate cd control and the gate end of line control are important, especially dense nFET patterns such as 6T-SRAM. The standard single mask/single etch approach for the gate patterning can make the gate cd on target but it suffers from the end of line shortening (Fig. 12). The end of line control is improved by introducing a double mask/double exposure (gate line and gate cut) (Fig. 12) [11]. Further end of line control becomes possible to introduce double mask/double exposure and double etch scheme (so-called double patterning

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Fig. 11 Fin prole comparison between optimized and non-optimized carbon containing etch by-product control during n etch. In optimized n etch, SiOC hard mask is fully consumed at the end of n etch. Therefore, a-C is not exposed to the etch chemical and the carbon containing by-product is not created

Fig. 12 Gate patterning optimization. Gate/n overlap control (circles in non-optimized pictures) is improved by double mask/double exposure

scheme). For the double patterning, SiN hard mask is introduced and BARC/resist thickness is optimized (Fig. 13). In the double gate patterning scheme, gate line patterns are printed and transferred to SiN hard mask by gate line etch. Then the gate cut patterns are printed and etched (Fig. 14). Figure 15 shows the gate double patterning results in a sub-0.1 lm2 nFET 6T-SRAM. The end of line gap and shape control becomes more robust. The spacer dened patterning shows better LER/LWR also in the gate [12, 13].

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Fig. 13 Gate stacks for the single gate patterning and the double gate patterning. The SiN hard mask is introduced for the double patterning and the BARC/photo resist thickness is optimized

Fig. 14 Gate double patterning scheme

4.3 Conformal Doping

For planar devices, the junction depth and the sheet resistance are the gure of merit for junction. For nFETs, due to their 3D structure, conformality is added as a new gure of merit for junction. It is very difcult to make the conformal doping prole with the conventional ion implantation, since only a small angle implant (*10) is acceptable for dense nFET structures and the small angle implant causes low ion-incorporation efciency on n sidewalls due to reection,

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self-sputtering and/or the geometry effect, etc. [14]. Several alternative doping techniques are investigated to improve the conformality (plasma doping and vapor phase doping). By using BF3 plasma doping, a good conformal p-doping is reported (Fig. 16) [15]. The advantage of conformal doping in pMOS nFET extension is demonstrated (Fig. 17) [15]. On the other hand, n-doping for nFET suffers from less conformality or low dopant activation (high sheet resistance). The improvement of n conformal doping is a key for nFET future.

Fig. 15 Top view and tilted view SEM pictures of gate double patterning in sub 0.1 lm2 nFET 6T-SRAM

Fig. 16 Conformal junction in nFET by using BF3 plasma doping

Fig. 17 pFinFET ion improvement by BF3 plasma doping. (Open ion implantation reference, lled BF3 plasma doping)

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4.4 Strain Engineering

The mobility enhancement on nFETs is a key technology to meet the high drive current requirement. Several strain engineering techniques have been reported, such as SSOI and tCESL (Fig. 18) [16], SiGe SD SEG (Figs. 19 and 20) [1719] and SiC SD SEG. Recently good drive current is reported by combining junction optimization and SiGe SD SEG [19]. Limited performance gain due to small substrate volume is an issue in nFETs.

Fig. 18 nFinFET performance boast by SSOI and tCESL. 35% performance improvement is achieved

Fig. 19 Schematic and topview SEM picture of SiGe SD epi on pFin FET

152 Fig. 20 FinFET performance improvement by SiGe SD epi. 25% performance improvement is achieved thanks to access resistance reduction and mobility enhancement by SiGe SD epi

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5 Summary
FinFETs show clear advantages in SCE control and device variability as compared to planar FETs. Thanks to the advantages, scaled SRAM and analog circuit are promising for nFET applications. Several sub-0.1 mm2 6T SRAMs are demonstrated with reasonable SNM already. Both better voltage gain and better transconductance are reported by optimized nFETs. On the other hand, for nFETs production, quite a lot of process challenges are required due to difcult n/gate patterning in the 3D structure, conformal doping to n and high access resistance in extremely thin body, etc. The n/gate patterning can be improved by optimization of patterning stack, patterning scheme and etch chemistry. Alternative doping techniques show good conformal doping in 3D structure in nFETs. High access resistance is reduced by junction optimization and strain boaster technique.

References
1. Wong, H.S.P., Frank, D.J., Solomon, P.M., et al.: Device design considerations for doublegate, ground-plane, and single-gated ultra-thin SOI MOSFETs at the 25 nm channel length generation. Int. Electron Dev. Meeting Tech. Digest. 407410 (1998) 2. Parvais, B., Mercha, A., Collaert, N., et al.: The device architecture dilemma for CMOS technologies: opportunities & challenges of Finfet over planar mosfet. In: International Symposium on VLSI Technology, Systems and Applications, pp. 8081 (2009) 3. Chiarella, T., Witters, L., Mercha, A., et al.: Migrating from planar to FinFET for further cmos scaling: SOI or bulk? In: ESSDERC Conference Proceedings, pp. 8588 (2009) 4. Rudenko, T., Kilchytska, V., Collaert, N., et al.: Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities. IEEE Trans. Electron Dev. 55, 35323541 (2008) 5. Collaert, N., von Arnim, K., Rooyackers, R., et al.: Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, n widths down to 10 nm and 30 nm gate length. In: International Conference on IC Design and Technology, pp. 5962 (2008)

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6. Merelle, T., Curatola, G., Nackaerts, A., et al.: First observation of FinFET specic mismatch behavior and optimization guidelines for SRAM scaling. In: International Electron Devices Meeting Technical Digest, pp. 241244 (2008) 7. Veloso, A., Demuynck, S., Ercken, M., et al.: Demonstration of scaled 0.099 lm2 FinFET 6T-SRAM cell using full-eld EUV lithography for (Sub-)22 nm node single-patterning technology. In: International Electron Devices Meeting Technical Digest, pp. 301304 (2009) 8. Guillorn, M., Chang, J., Pyzyna, A., et al.: Trigate 6T SRAM scaling to 0.06 lm2. In: International Electron Devices Meeting Technical Digest, pp. 961963 (2009) 9. Horiguchi, N., Demuynck, S., Ercken, M., et al.: High yield sub-0.1 lm2 6T-SRAM cells, featuring High-k/Metal-Gate, Finfet devices, double gate patterning, a novel n etch strategy, full-eld EUV lithography and optimized junction design & layout. In: Symposium on VLSI Technology, pp. 2324 (2010) 10. Wambacq, P., Mercha, A., Scheir, K., et al.: Advanced planar bulk and multigate CMOS technology: analog-circuit benchmarking up to mm-wave frequencies. In: International Solid-State Circuits Conference, pp. 528529 (2008) 11. Ercken, M., Altamirano-Sanchez, E., Baerts, C., et al.: Challenges in using optical lithography for the building of a 22 nm node 6T-SRAM cell. Microelectronic Eng. 87, 993996 (2010) 12. Choi, Y.K., Lindert, N., Xuan, P., et al.: Sub-20 nm CMOS FinFET technologies. In: International Electron Devices Meeting Technical Digest, pp. 421424 (2001) 13. Rooyackers, R., et al.: (2006) Doubling or quadrupling MuGFET n integration scheme with higher pattern delity, lower CD variation and higher layout efciency. In: International Electron Devices Meeting Technical Digest, pp. 168171 (2001) 14. Mody, J., Duffy, R., Eyben, P., et al.: Experimental studies of dose retention and activation in n eld-effect-transistor-based structures. J. Vac. Sci. Technol. B 28, 1 (2010) 15. Lenoble, D., Anil, K.G., De Keersgieter, A., et al.: Enhanced performance of PMOS MUGFET via integration of conformal plasma-doped source/drain extensions. In: Symposium on VLSI Technology, pp. 168169 (2006) 16. Collaert, N., Rooyackers, R., Clemente, F., et al.: Performance enhancement of MUGFET devices using super critical strained-SOI (SC-SSOI) and CESL. In: Symposium on VLSI Technology, pp. 176177 (2006) 17. Verheyen, P., Collaert, N., Rooyackers, R., et al.: 25% Drive current improvement for p-type multiple gate FET (MuGFET) devices by the introduction of recessed Si0.8Ge0.2 in the source and drain regions. In: Symposium on VLSI Technology, pp. 194195 (2005) 18. Kavalieros, J., Doyle, B., Datta, S., et al.: Tri-gate transistor architecture with high-k Gate dielectrics, metal gates and strain engineering. In: Symposium on VLSI Technology, pp. 6263 (2006) 19. Chang, C.Y., Lee, T.L., Wann, C., et al.: A 25-nm gate-length FinFET transistor module for 32 nm node. In: International Electron Devices Meeting Technical Digest, pp. 293296 (2009)