CHAPTER 2 MOS TRANSISTOR THEORY Introduction Logic design deals with the creation of a digital network that performs

a particular task. In terms of Boolean logic, this is equivalent to implementing a particular function. Combinational logic deals with network that use logic gates to combine the input variables as needed to produce logic functions. In a combinational circuit, the value of output is determined by the current value of the input. If any of the inputs are changed, then the value of the output may change as specified by the function. There is no intentional connection from outputs back to inputs !ig.".#$. The common design metrics by which a gate is evaluated are area, speed, energy and power. !or e%ample, the switching speed of digital circuits is the primary metric in a high&performance processor, while in a battery operated circuit, it is energy dissipation. 'ecently, power dissipation also has become an important concern and considerable emphasis is placed on understanding the sources of power and approaches to dealing with power. In addition to these metrics, robustness to noise and reliability are also very important considerations. (e will see that certain logic styles can significantly improve performance, but they usually are more sensitive to noise.

!ig.".# Combinational logic circuit

Static CMOS design The most widely used logic is static complementary C)*+. The primary

advantage of the C)*+ structure is robustness i.e., low sensitivity to noise$, good performance, and low power consumption with no static power dissipation. )ost of those properties are carried over to large fan&in logic gates implemented using a similar circuit topology. In this section, we address the design of various static circuits including complementary C)*+, ratioed logic pseudo&n)*+ and ,C-+L$, and pass&transistor logic. Complementary CMOS . static C)*+ gate is a combination of two networks / the pull&up network 012$ and the pull&down network 0,2$ as in !ig.".3. The function of the 012 is to provide a connection between the output and -,, anytime the output of the logic gate is meant to be # based on the inputs$. +imilarly, the function of the 0,2 is to connect the output to -++ when the output of the logic gate is meant to be 4. The 012 and 0,2 networks are constructed in a mutually e%clusive fashion such that one and only one of the networks is conducting in steady state.

!ig.".3 Complementary logic gate as a combination of pull&down and pull&up networks In constructing the 0,2 and 012 networks, the following points should be noted5 . transistor can be thought of as a switch controlled by its gate signal. .n n)*+ switch assumes positive logic and p)*+ switch assumes negative logic for their operation. The 0,2 is constructed using n)*+ devices while p)*+ transistors are used in the 012. This is due to the fact that n)*+ transistors produce 6strong 7eros8 and p)*+ devices generate 6strong ones9. Consider the e%amples shown in !ig.".:. In !ig.".:a, the output capacitance is initially charged to -,,. .n n)*+ device pulls the output down to ;2, all the way, while a p)*+ lowers the output no further than -T0 / the p)*+ turns off at that point and stops contributing discharge current. The n)*+ transistors are thus preferred in the 0,2. In !ig.".:b, the output is initially at ;2,. . p)*+ switch succeeds in charging the output all the way to -,,, while the n)*+ device fails to raise the output above - ,,/ -Tn. Thus, p)*+ transistors are preferably used in a 012.

!ig.".: Illustrations of n)*+ switches in 0,2 and a p)*+ switch in 012 . set of rules can be derived to construct logic function. connected in parallel represent an *' function. +imilarly, a series connection of p)*+ represents a 2*' function whereas p)*+ transistors in parallel implement a 2.2, function. The pull&up and pull&down networks of a complementary C)*+ structure are dual networks. This means that a parallel connection of transistors in the pull&up network corresponds to a series connection of the corresponding devices in the pull&down network, and vice versa. The complementary gate is naturally inverting, implementing only functions such as 2.2,, 2*' and <2*'. The reali7ation of a non&inverting Boolean function 2)*+ devices

connected in series correspond to an .2, function, while n)*+ transistors

such as .2,, *' or <*'$ in a single stage is not possible, and requires the addition of an e%tra inverter stage. The number of transistors required to implement an 2&input logic gate is 32.

Static properties o complementary CMOS !ates They e%hibit rails&to&rail swing with -*= > -,, and -*L > ;2,. The circuits have no static power dissipation, since the circuits are designed such that the pull&down and pull&up networks are mutually e%clusive. The analysis of the ,C voltage transfer characteristics and the noise margins is more complicated than for the inverter, as these parameters depend upon the data input patterns applied to the gate. Propagation delay o Complementary CMOS gates !or the delay analysis, each transistor is modeled as a resistor in series with an ideal switch. The value of the resistance is dependent on the power supply voltage and an equivalent large signal resistance, scaled by the ratio of device width over length, must be used. The logic is transformed into an equivalent 'C network that includes the effect of internal node capacitances. !ig.".? shows the two&input 2.2, gate and its equivalent 'C switch level model.

!ig.".? @quivalent 'C model for a two&input 2.2, gate The internal node capacitance Cint / attributable to the sourceAdrain regions and the gate overlap capacitance of )3 and )# / is included. The propagation delay depends on the input patterns. If both inputs . and B are driven low, the two p)*+ devices are *2. The delay in this case is 4.BC '0A3$ CL, since the two resistors are in parallel. The worst&case low& to&high transition occurs when only one device turns *2, and is given by 4.BC' 0 CL. !or the pull&down path, the output is discharged only if both . and B are switched high, and the delay is given by 4.BC '0A3$CL. In other words, adding devices in series slows down the circuit, and devices must be made wider to avoid a performance penalty. Consider a four&input 2.2, gate as in !ig.".D, which shows the equivalent 'C model of the gate, including the internal node capacitances.

!ig.".D !our&input 2.2, gate as its 'C model The propagation delay can be computed by using the @lmore delay model, tp=L > 4.BC '#C# E '#E'3$C3E '#E'3E':$C3 E '#E'3E':E'?$CL$ .ssuming that all n)*+ devices have an equal si7e, @q. ".#$ simplifies to tp=L > 4.BC4 '2 C#E3C3E:C:E?CL$ ".3$ ".#$

The main advantage of complementary C)*+ is that it is a very robust and simple approach for implementing logic gates. Two maFor problems associated with using this style as the comple%ity of the gate i.e., fan&in$ increases are5 #$ The number of transistors required to implement an 2 fan&in gate is 32. This can result in a significantly large implementation area. 3$ The propagation delay of a complementary C)*+ gate deteriorates rapidly as a function of the fan&in.

"esign tec#ni$ues or large %an&in The designer has a number of techniques to reduce the delay of large fan&in circuits. Transistor si'ing The most obvious solution is to increase the transistor si7es. This lowers the resistance of devices in series and lowers the time constants. Progressi(e Transistor Si'ing .n alternate approach to uniform si7ing is to use progressive transistor si7ing. This approach reduces the dominant resistance, while keeping the increase in capacitance within bounds. Input Reordering +ome signals in comple% combinational logic blocks might be more critical than others. .n input signal to a gate is called critical if it is the last signal of all inputs to assume a stable value. The path through the logic which determines the ultimate speed of the structure is called the critical path. 0utting the critical path transistors closer to the output of the gate can result in a speed up. )ogic Restructuring )anipulating the logic equations can reduce the fan&in requirements and thus reduces the gate delay. Po*er consumption in CMOS )ogic gates The power dissipation is a strong function of transistor si7ing which affects physical capacitance$, input and output rise&fall times which determine the short circuit power$, device thresholds and temperature which impact leakage power$ and switching activity. The dynamic power dissipation is given by C L-3,,f. )aking a gate more comple% mostly affects the switching activity, which consists of two components5 a static component that is only a function of the topology of the logic network, and a dynamic one that results from the timing behavior of the circuit. The latter factor is also called glitching. The C)*+ logic described is highly robust and scalable with technology, but requires 32 transistors to implement an 2&input logic gate. .lso, the load capacitance is

significant, since each gate drives two devices a p)*+ and an n)*+$ per fan&out. This has opened the door for alternative logic families that either are simpler or faster. T#e %ull Adder+ Circuit "esign Considerations Static Adder Circuit

!ig.#4.: Inverting property of the full adder The circles indicate inverters$ *ne way to implement the full adder circuit is to take the logic equations of @q. #4.#$ and translate them directly into complementary C)*+ circuitry. +ome logic manipulations can help to reduce the transistor count. !or instance, it is advantageous to share some logic between the sum& and carry& generation sub circuits, as long as this does not slow down the carry generation, which is the most critical part as stated preciously. The following is an e%ample of such a reorgani7ed equation set5 Co > .B E BCi E .Ci and + > .BCi E Co .EBECi$ #4.B$ The equivalence with the original equation is easily verified. The corresponding adder design, using complementary static C)*+ is shown in !ig.#4.? and requires 3" transistors. In addition to consuming a large area this circuit is slow5 Tall p)*+ transistor stacks are present in both carry and sum generation circuits. The intrinsic load capacitance of the Co signal is large and consists of two diffusion and si% gate capacitances plus the wiring capacitance.

The signal propagates through two inverting stages in the carry generation circuit. .s mentioned earlier, minimi7ing the carry&path delay is the prime goal of the designer of high&speed adder circuits. ;iven the small load fan&out $ at the output of the carry chain, having two logic stages is too high a number and leads to e%tra delay.

The sum generation requires one e%tra logic stage, but that is not that important since a factor appears only once in the propagation delay of the ripple&carry adder of @q. #4.?$. .lthough slow, the circuit includes some smart design tricks. 2otice that the first

gate of the carry&generation circuit is designed with the Ci signal on the smaller p)*+ stack, lowering its logical effort to 3. .lso, the n)*+ and p)*+ transistors connected to Ci are placed as close as possible to the output of the gate. This is a direct application of a circuit&optimi7ation technique / transistors on the critical path should be placed as close as possible to the output of the gate. !or instance, in stage k of the adder, signals .k and Bk are available and stable long before Ci,k > C4,k&#$ arrives after rippling through the previous stages. In this way, the capacitances of the internal nodes in the transistor chain are precharged or discharged in advance. *n arrival of Ci,.k only the capacitance of node < has to be dis$charged. 0utting the Ci,k transistors closer to -,, and ;2, would require not only the dis$charging of the capacitance of node <, but also of the internal capacitances.

!ig.#4.? Complementary static C)*+ implementation of full adder The speed of this circuit can now be improved gradually by using some of the adder properties discussed in the previous section. !irst, the number of inverting stages in the carry path can be reduced by e%ploiting the inverting property / inverting all the inputs of a full&adder cell also inverts all the outputs. This rule allows us to eliminate an inverter in a carry chain as demonstrated in !ig.#4.D.

!ig.#4.D Inverter elimination in carry path !.9 stands for a full adder without the inverter in the carry path$

Introduction to stic, "iagram The programmable logic devices 0L,s$ are used in many applications to replace ++I and )+I circuits. They save space and reduce the actual number and cost of devices in a given design. . 0L, consists of a large array of .2, gates and *' gates that can be programmed to achieve specified logic functions. The four types of devices that are classified as 0L,s are the programmable read only memory 0'*)$, the programmable logic array 0L.$, the programmable array logic 0.L$ and the generic array logic ;.L$. In addition, there are much larger programmable logic devices, called comple% 0L,s C0L,s$ and field programmable gate arrays !0;.s$. .ll 0L,s consist of programmable arrays. . programmable array is essentially a grid of conductors that form rows and columns with a fusible link at each cross point. .rrays can be either fi%ed or programmable. The 0'*) consists of a set of fi%ed nonprogrammable$ .2, gates connected as a decoder and a programmable *' array. The 0L. is a 0L, that consists of a programmable .2, array and a programmable *' array. The 0L. can overcome some of the limitations imposed by the 0'*). The 0.L is a 0L,, consisting of a programmable .2, array and a fi%ed *' array with output logic. It was developed to overcome certain disadvantages of the 0L., such as longer delays due to the additional fusible links that result from using two programmable arrays and more circuit comple%ity. . more recent development in 0L,s is the ;.L. It has a programmable .2, array and a fi%ed *' array with programmable output logic. The differences between ;.L and 0.L devices are that the ;.L is reprogrammable and it has programmable output configurations. C0L,s are essentially much larger versions of simple 0L,s, with a centrali7ed internal interconnect matri% to connect the device macrocells together. !0;.s, on the other hand, consist of a large array of simple logic cells with interconnecting hori7ontal and vertical routing channels. In this chapter, the programmable logic devices such as C0L, and !0;. are discussed in detail.

nMOS P)As The basic 0L. structure consists of an .2, plane driving an *' plane as

shown in !ig.##.#. The terminology corresponds to a sum of products +*0$ reali7ation of the desired function. The +*0 reali7ation converts directly into a 2.2,&2.2, implementation. (hen a product of sums 0*+$ reali7ation is desired, it can be implemented in *'&.2, or 2*'&2*' logic. In either case, the first array is referred to as the .2, plane, and the second array as the *' plane. The line connecting the .2, plane to the *' .2, plane plane are called the *' plane product lines.

'egister G#

'egister G3

In puts

*utputs

!ig.##.# The Basic 0L. structure The *' plane matri% is identical in form to the .2, plane matri%, but its layout is rotated C4 degrees with respect to the .2, plane. The input and output registers need not be identical, but they are also repetitive structures. The overall

si7e of a 0L. is a function of the number of inputs, the number of product terms, the number of outputs, and the value of the parameter lambda. The 0L. must be programmed by appropriately locating transistors on the array.
nMOS P)A layouts

The n)*+ 0L. can be reali7ed in either 2.2,&2.2, logic or 2*'& 2*' logic. The 2.2, implementation is much smaller because it needs no metal contacts in the matri% of the .2, or *' plane and is more compact. But, the 2.2, structure is much slower than the 2*' implementation due to the series pass transistor structure. . 2.2, 0L. with 2 control transistors in series is about 2%2 times slower than the 2*' reali7ation, while the 2.2, implementation is typically smaller in area than the 2*' reali7ation by a factor of about three to one. Consider the 0L. with : inputs I4, I#, I3. It is programmed to reali7e four product lines with three output lines. The product lines are indicated by 0 4, 0#, 03, and 0:. The outputs reali7ed by this 0L. are denoted by H4, H#, and H3. The product terms are5 04 > I4 I# 0# > I4 I# 03 > I4 I# I3 0: > I4 I3 The outputs are5 H4 > 0# H# > 04E03E0: H3 > 0#E03
NOR&NOR Reali'ation o nMOS P)A

##.#$

##.3$

The 2*'/2*' reali7ation of n)*+ 0L. for the above e%ample is obtained in the following way. It includes input and output buffers and two&phase clocking. !irst, the personality matri%,I of the 0L. is developed. In the .2, plane, element qiF>4 if a !@T is to connect product line pi to input line IF. The element qiF ># if a !@T is to connect product line p i to input line Ii. The element qiF is a don9tcare <$ if neither input is to be connected to product line p i. In the *' plane, qiF># if product line pi connects to output HF, and 4 otherwise. The personality matri% for the above e%ample is given below5 # # 4 4 # 4 4 % % % # 4 4 # 4 4 # 4 # # 4 # # 4

I>

##.:$

The procedure for laying out a 2*'&2*' 0L. is as follows5

.2, 0lane !or each logic # in the input columns of the personality matri%, run a diffusion& path from the appropriate product&term line, under the corresponding invested input line in the 0L. .2, plane to ground. The transistor thus created is controlled by the inverted input line. (henever the controlling line crossing the .2, plane is high, the product& term line will be low. !or each logic 4 in the input columns of the personality matri%, run a diffusion path from the appropriate product&term line, under the corresponding non&inverted input line in the 0L. .2, plane. The transistor thus created is controlled by the non&inverted input line. (henever that controlling line crossing the .2, plane is high, the product term line will be low. ,on9t care terms are connected to neither the true nor the complemented input lines.

*' 0lane

!or each logic # in the output columns of the personality matri%, run a diffusion path from the ne%t&state output line in the 0L. *' plane, under the corresponding

product term line, to ground. This creates a transistor controlled by the product/term line. Then, if that controlling product&term line is high, the path to the output inverter will be low, and the output will be high. The output is low unless atleast one product line controlling it is high. . 2*'&2*' reali7ation of )*+ 0L. for the above e%ample with enhancement mode pull&down devices is shown in !ig.##.3, including input and output buffers and two phase chocking # and 3 $. The pull&up device is depletion&mode n)*+ device.
-,,

;2,

;2, ;2,

-,,

;2, -,,

J3

J3

J# I4 I# I3

J# H4 H# H3

!ig.##.3 . stick drawing of an n)*+ 2*'&2*' 0L. reali7ation

NAN"&NAN" Reali'ation o nMOS P)A The procedure for laying out a 2.2,&2.2, 0L. is described below5 .2, 0L.2@

!or each logic # in the input columns of the personality matri%, place an ion implant under the appropriate product line where it intersects the noninverted input line

in the 0L. .2, plane. The transistor thus created is always *2 and the non&inverted input line has no control over&that product line. (henever all the controlling input lines in the .2, plane are high, the product line will be low. !or each logic 4 in the input columns of the personality matri%, place an ion implant under the appropriate product line where it intersects the inverted&input line in the 0L. .2, plane. The transistor thus created is always *2 and the inverted input line has no control over that product line. (henever all the controlling input lines are high, the product line will be low. . don9t care requires ion implants for both the true and complemented input signals.
*' 0L.2@

!or each logic 4 in the output columns of the personality matri%, place an ion implant under the product line where it intersects the output line in the 0L. *' plane. The transistor thus created is always *2 and that product line has no control over the output line. (henever the controlling product lines are high, the non&inverted output will be low. . 2.2,&2.2, reali7ation of n)*+ 0L. for the above e%ample in @qns. ##.# K ##.3 is shown in !ig.##.:. The pull/up device is a depletion&mode n)*+ device.
-,, ;2, ;2, 04 0# 03 0: ;2, -,, -,, -,, ;2,

J#

J#

J3

J3

!ig.##.: . stick drawing of an n)*+ 2.2,&2.2, 0L. reali7ation

I4 I# I3 H4 H# H3

--.2.-./ T#e prec#arged nMOS P)A ,epletion/mode pull/up devices are slow and precharging the output lines of both the .2, plane and the *' plane avoids the slow depletion&mode pull&up. ,uring phase I, each product line and each output line can be precharged to - ,,, while phase II isolates the ground and prevents the 0L. from evaluating the logic. ,uring phase II, the 0L. will determine which input lines remain charged and which input lines will be discharged, while the product lines determine which output lines will be pulled low. !ig ##.? and !ig.##.D show possible layouts of the 2*'&2*' and 2.2,&2.2, 0L. structures given in !ig.##.3 and !ig.##.: respectively augmented with clock lines for precharging and evaluating the 0L.s.

-,,

J#

J3

;2,

-,, ;2,

J3

J#

J3

J3
J#

I4
-,,

I#

I3

H4

H#

H3
;2,

!ig.##.? . precharged n)*+ 2*'&2*' 0L.

T#e CMOS P)A The basic C)*+ 0L. is obtained by providing a well and replacing the pull&up devices in the 2.2,&2.2, array or in the 2*'& 2*' array with enhancement mode p)*+ devices. The C)*+ array can be precharged or not, and can be clocked with the same two& phase clocking scheme as used for the )*+ 0L.. C)*+ 0L. design offers many more varieties of layout than does n)*+. Ot#er programma0le logic de(ices There are several close relative structures of the basic 0L.. . digital, application specific IC family, widely used in -L+I design, is the programmable logic device. The

;2,

J3

J#
-,,

J# I4
;2,

J3 I# I3 J#
-,,

H4

H#

H3

!ig.##.D . precharged )*+ 2*'&2*' 0L.

H H H 3

J3

.2,/*' structure of the 0L. is the core of all 0L,s, since this structure can be used to implement any two&level boolean function. )ultilevel logic can be reali7ed with (einberger arrays or gate matrices. T#e ield programma0le logic array 1%P)A2 The field/programmable logic array !0L.$ shown in !ig.##.B has an address decoder the .2, array$ and a data matri% the *' array$. In the !0L., both the address decoder and the data matri% are programmable. This is shown by placing hollow diamonds at all the cross point sites. . cross point is the intersection of a row and a column of the 0L.. (hen programming the 0L., the appropriate cross points can be filled in to indicate connections. @ach .2, gate can have don9t care inputs, which implies that multiple inputs can select the same word. .lso, since multiple .2, outputs can be *2 simultaneously,
04 0# 03 0: 0? 0D 0B 0L J3 J# I4 I# I3 H4 H# H3 H:

J#

J3

!ig.##.B The clocked !0L. structure multiple words in the *' array can be selected at the same time, thus allowing a function to be divided among multiple !0L.s.

There are two special cases of !0L.5 the programmed read&only memory or 0'*), the programmed array logic or 0.L. In 0'*), the *' matri% is programmable and the .2, matri% is fi%ed. In 0.L, the .2, matri% is programmable and the *' matri% is fi%ed. The 0'*) configuration is shown in !ig.##.L with the .2, plane cross point connections darkened. . 0'*) is useful for creating simple logic devices such as memory& adder decoders, but the fi%ed .2, array limits its use in more comple% applications where multiple adrenals might be needed for the same word. Programma0le array logic 1PA)2 In the 0.L structure, the *' plane has been preprogrammed. +ince it has a programmable .2, array, multiple addresses can select the same word, and multiple words in the array can be selected simultaneously !ig.##."$.

.2, 0L.2@

*' 0L.2@

04 0# 03 0: 0? 0D 0B 0L

J3 J# I4 I# I3 H4 H# H3 H:
+

J3

!ig.##.L The clocked 0'*) structure

0.Ls and !0L.s overcome one of the maFor inefficiencies of 0'*)s by allowing only as many inputs as necessary for a specific implementation. +ome 0.Ls do not have the fuses or the programming and testing circuitry required by the *' arrays of !0L.s, they are typically about #DM faster than !0L.s for the same power consumption. 0.Ls used to be limited to control logic and IA* applications but recent improvements in performance make 0.Ls suitable for date&path logic also. The 0.L shown in !ig.##." has 3&input *' gates in the *' plane. Commercial devices typically have "&input *' gates, and reali7e an "&wide .2,&*' structure.