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Dierence Equations and Implementation

Dierence Equations and Implementation

Dierence Equations and Implementation


Professor Deepa Kundur
University of Toronto

Reference: Section 2.4 and 2.5 of John G. Proakis and Dimitris G. Manolakis, Digital Signal Processing: Principles, Algorithms, and Applications, 4th edition, 2007.

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Dierence Equations and Implementation

2.4 Dierence Equations

Dierence Equations and Implementation

2.4 Dierence Equations

Finite vs. Innite Impulse Response


For causal LTI systems, h(n) = 0 for n < 0. Finite impulse response (FIR):
M 1

Finite vs. Innite Impulse Response


Implementation: Two classes Finite impulse response (FIR):

y (n) =
k =0

h(k )x (n k ) y (n) =

M 1

h(k )x (n k )
k =0

nonrecursive systems

Innite impulse response (IIR):

Innite impulse response (IIR): h(k )x (n k )

y (n) =
k =0

y (n ) =
k =0

h(k )x (n k )

recursive systems

How would one realize these systems?


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Dierence Equations and Implementation

2.4 Dierence Equations

Dierence Equations and Implementation

2.4 Dierence Equations

System Realization
There is a practical and computationally ecient means of implementing all FIR and a family of IIR systems that makes use of ... . . . dierence equations.
All systems All LTI systems

System Realization
There is a practical and computationally ecient means of implementing all FIR and a family of IIR systems that makes use of ... . . . dierence equations.
All systems All LTI systems

All LTI FIR systems

All LTI IIR systems

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Dierence Equations and Implementation

2.4 Dierence Equations

Dierence Equations and Implementation

2.4 Dierence Equations

System Realization
There is a practical and computationally ecient means of implementing all FIR and a family of IIR systems that makes use of ... . . . dierence equations.
All systems All LTI systems

System Realization
General expression for N th-order LCCDE:
N M

ak y (nk ) =
k =0 k =0

bk x (nk )

a0

Initial conditions: y (1), y (2), y (3), . . . , y (N ).


Systems Described by LCCDEs

Need: (1) constant scale, (2) addition, (3) delay elements.


All LTI FIR systems All LTI IIR systems

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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Building Block Elements

FIR System Realization

Adder:

Unit delay:

Finite Impulse Response Systems and Nonrecursive Implementation


Constant multiplier: Unit advance: Signal multiplier:

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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

FIR System Realization: Example


Consider a 5-point local averager: 1 y (n) = x (k ) n = 0, 1, 2, . . . 5 k =n 4 The impulse response is given by: 1 h (n ) = (k ) 5 k =n4 = 1 1 1 (n 4) + (n 3) + (n 2) + 5 5 5 1 1 (n 1) + (n) 5 5
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FIR System Realization: Example


Consider a 5-point local averager: 1 y (n) = x (k ) n = 0, 1, 2, . . . 5 k =n 4
n

h[n]
1/5
0 1 2 3 4

n
Indeed FIR!

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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

FIR System Realization: Example


Consider a 5-point local averager: 1 y (n) = x (k ) n = 0, 1, 2, . . . 5 k =n 4
n

FIR System Realization: Example


y (n) = 1 5
n n

x (k ) =
k =n4 k =n4

1 x (k ) 5

y (n) =

1 1 1 x (n 4) + x (n 3) + x (n 2) + 5 5 5 1 1 x (n 1) + x (n) 5 5

Memory requirements stay constant; only need to store 5 values (4 last + present). xed number of adders required
1/5
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+

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+ +

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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

FIR System Realization: General


M 1

FIR System Realization

y (n) =
k =0

bk x (n k )
Adder:
+

...
+ + +

Unit delay: Innite Impulse Response Systems and Recursive Implementation


+ +

...

Constant multiplier: Unit advance: Signal multiplier:


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Requires: M multiplications M 1 additions M 1 memory elements


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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

IIR System Realization: Example


Consider an accumulator:
n

IIR System Realization: Example


Consider an accumulator:
n

y (n ) =
k =0

x (k ) n = 0, 1, 2, . . .

for y (1) = 0.

y (n ) =
k =0

x (k ) n = 0, 1, 2, . . .

for y (1) = 0.

The impulse response is given by:


n

IIR memory requirements seem to grow with increasing n!

h (n ) =
k =0

(k ) = (n) + (n 1) + (n 2) + 1 n0 0 n<0

h[n]
1
0 1 2 3 4

... n
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Professor Deepa Kundur (University of Toronto) Dierence Equations and Implementation

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

IIR System Realization: Example

Direct Form I vs. Direct Form II Realizations


N M

y (n) = x (k )
k =1

ak y (n k ) +
k =0

bk x (n k )

y (n) =
k =0 n1

is equivalent to the cascade of the following systems:


M

=
k =0

x (k ) + x (n) v (n) recursive implementation output 1 y (n) output 2 =

bk x (n k )
k =0 N

nonrecursive

= y (n 1) + x (n) y (n) = y (n 1) + x (n)

input 1 ak y (n k ) + v (n) recursive

=
k =1

input 2

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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Direct Form I IIR Filter Implementation


+

Direct Form II IIR Filter Implementation


+ +

v(n)

...

...

...

...

...

...

...

LTI All-zero system

LTI All-pole system

LTI All-pole system

LTI All-zero system

Requires: M + N + 1 multiplications, M + N additions, M + N memory locations


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Requires: M + N + 1 multiplications, M + N additions, M + N memory locations


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Dierence Equations and Implementation

2.5 Implementation of Discrete-time Systems

Direct Form II IIR Filter Implementation


Adder:
+
+ + +

Adder:

Unit delay:
+

Unit delay: Constant multiplier: Unit advance: Signal multiplier:

Constant multiplier: +
+

Unit advance:
+

...

Signal multiplier:

...

For N>M

Requires: M + N + 1 multiplications, M + N additions, max(M , N ) memory locations


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...

...

...
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