11/2/2011 Anirudh Radhakrishnan 1

1HL ARM71DMI 1HL ARM71DMI

Introduction And Architecture Introduction And Architecture
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IN1RODUC1ION 1O ARM IN1RODUC1ION 1O ARM
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History of ARM History of ARM
Acron started in 1983 Acron started in 1983
By 1985 design o irst commercial RISC By 1985 design o irst commercial RISC
machine called Acron RISC Machine ,ARM,. machine called Acron RISC Machine ,ARM,.
In 1990 there were 12 engineers and 1 CLO, In 1990 there were 12 engineers and 1 CLO,
with no customers and a little money. with no customers and a little money.
In 1990`s 1I incorporated ARM or mobile In 1990`s 1I incorporated ARM or mobile
phones phones
By 1998 there were 13 millionaires in company. By 1998 there were 13 millionaires in company.
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Origin Of the Name ARM71DMI Origin Of the Name ARM71DMI
ARM ARM -- cron cron ##isc isc achine , achine ,Now Now A Adanced danced RRisc isc M Machine achine,,
1 1 -- 1he 1humb 16 bit instruction set. 1he 1humb 16 bit instruction set.
D D -- On chip Debug support. On chip Debug support.
M M -- Lnhanced Multiplier Lnhanced Multiplier
I I -- Lmbedded ICL hardware to gie break point Lmbedded ICL hardware to gie break point
and watch point support. and watch point support.
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ARM Ieatures ARM Ieatures
RISC RISC
32 bit 2 bit general purpose processor processor
ligh perormance , low power consumption and ligh perormance , low power consumption and
small size small size
Large , regular Register lile Large , regular Register lile
toaa,.tore toaa,.tore architecture architecture
!ipelining !ipelining
Uniorm and ixed Uniorm and ixed--length,32 bit, instruction length,32 bit, instruction--,ARM, ,ARM,
33--address instruction address instruction
Simple addressing modes Simple addressing modes
contd contd--
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Conditional execution o the instructions Conditional execution o the instructions
Control oer both ALU and Shiter in eery data Control oer both ALU and Shiter in eery data
processing instruction processing instruction
Multiple load,store register instructions Multiple load,store register instructions
Ability to perorm 1clk cycle general shit & Ability to perorm 1clk cycle general shit &
ALU operation in 1 instruction ALU operation in 1 instruction
Coprocessor instruction interacing Coprocessor instruction interacing
1lUMB architecture 1lUMB architecture--,dense 16 ,dense 16--bit compressed bit compressed
instruction set, instruction set,
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1HUMB Instruction Set (1 variant) 1HUMB Instruction Set (1 variant)
re re--encoded subset o ARM instruction encoded subset o ARM instruction
lal the size o ARM instructions,16 bit, lal the size o ARM instructions,16 bit,
Greater code density Greater code density
On execution 16 bit thumb transparently decompressed On execution 16 bit thumb transparently decompressed
to ull 32 bit ARM without loss o perormance to ull 32 bit ARM without loss o perormance
las all the adantages o 32 bit core las all the adantages o 32 bit core
Low perormance in time Low perormance in time--critical code critical code
Doesn`t include some instruction needed or exception Doesn`t include some instruction needed or exception
handling handling
contd contd--
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0 more instructions than ARM code 0 more instructions than ARM code
30 less external memory power than ARM code 30 less external memory power than ARM code
\ith 32 bit memory \ith 32 bit memory
--ARM code 0 aster than 1humb code ARM code 0 aster than 1humb code
\ith 16 bit memory \ith 16 bit memory
--1humb code 5 aster than Arm code 1humb code 5 aster than Arm code
lor best perormance lor best perormance
--use 32 bit memory and ARM code use 32 bit memory and ARM code
lor best cost and power eiciency lor best cost and power eiciency
--use 16 bit memory and thumb code use 16 bit memory and thumb code
In typical embedded system In typical embedded system
--Use ARM code in 32 bit on Use ARM code in 32 bit on--chip memory or small speed chip memory or small speed--
critical routines critical routines
--Use 1humb code in 16 bit o Use 1humb code in 16 bit o--chip memory or large non chip memory or large non--
critical routines critical routines
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ARM state ARM state
All instructions are 32 bit in length All instructions are 32 bit in length
All instructions must be word aligned All instructions must be word aligned
!C alue stored in bits|31:2| and bits |1:0| equal !C alue stored in bits|31:2| and bits |1:0| equal
to zero to zero
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1HUMB state 1HUMB state
Instructions 16 bit in length Instructions 16 bit in length
Instructions hal Instructions hal--word aligned word aligned
!C alue stored in bits|31:1| and bit |0| equal to !C alue stored in bits|31:1| and bit |0| equal to
zero zero
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Introduction to RISC And CISC Introduction to RISC And CISC
\hat is CISC \hat is CISC
C Complex omplex IInstruction nstruction S Set et C Computers. omputers.
Aimed at reducing the gap between instruction set Aimed at reducing the gap between instruction set
and high leel language. and high leel language.
1hese instructions perorm complex sequence o 1hese instructions perorm complex sequence o
operations oer many cycles. operations oer many cycles.
Large and powerul range o instruction Large and powerul range o instruction
Less lexible to implement Less lexible to implement
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RISC RISC
RISC stands or Reduced Instruction Set RISC stands or Reduced Instruction Set
Computer. Computer.
Optimizing the instruction set and improing Optimizing the instruction set and improing
the speed o the processor. the speed o the processor.
1he memory access instructions are those which 1he memory access instructions are those which
make a computer slow. Arithmetic instructions make a computer slow. Arithmetic instructions
hae less eect on speed o processor. hae less eect on speed o processor.
Around 5 o C!U usage is or Data transer. Around 5 o C!U usage is or Data transer.
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RISC Architecture RISC Architecture
lixed instruction size with ew ormats. lixed instruction size with ew ormats.
Memory access instructions are separated rom Memory access instructions are separated rom
instructions that process data. instructions that process data.
A large register bank o 32 registers each o size A large register bank o 32 registers each o size
32 bits. 32 bits.
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RISC Ieatures RISC Ieatures
lard wired instruction decode logic. lard wired instruction decode logic.
!ipelined instruction execution !ipelined instruction execution
Large number o registers Large number o registers
Register independence Register independence
Smaller die size Smaller die size
Low power Low power
Simpler to program Simpler to program
Comparatiely less expensie Comparatiely less expensie
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Advantages Of RISC Advantages Of RISC
Reduction in the size o processor. Reduction in the size o processor.
ligh instruction throughput. ligh instruction throughput.
Lxcellent response or interrupt. Lxcellent response or interrupt.
Licient usage o C!U time. Licient usage o C!U time.
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!ipelines !ipelines
Usually instructions are executed in three stages. Usually instructions are executed in three stages.
letch letch
Decode Decode
Lxecute Lxecute
Can we concurrently use the processor to Can we concurrently use the processor to
perorm seeral operations perorm seeral operations
\es, this is what is known as !I!LLINING. \es, this is what is known as !I!LLINING.
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!ipelines !ipelines
Clearly, portion o the hardware which does Clearly, portion o the hardware which does
etching job will be idle during decode and etching job will be idle during decode and
execute phase. execute phase.
1his led to idea that next instruction can be 1his led to idea that next instruction can be
started beore the current one has inished. started beore the current one has inished.
letch the II instruction during decoding o II letch the II instruction during decoding o II
instruction, decode the II instruction during instruction, decode the II instruction during
execution o I instruction and so on. execution o I instruction and so on.
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!ipelining !ipelining
!ipe lining !ipe lining
lL1Cl
DLCODL
LXLCU1L
III INS1RUC1ION lL1ClLD
II INS1RUC1ION DLCODLD
I INS1RUC1ION LXLCU1LD
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!ipeline Stages !ipeline Stages
letch letch
o o instruction is etched rom memory and placed in instruction instruction is etched rom memory and placed in instruction
pipeline pipeline
Decode Decode
o o instruction is decoded instruction is decoded
o o data data--path control signals prepared or next cycle path control signals prepared or next cycle
o o in data transer instructions ,ALU holds address in data transer instructions ,ALU holds address
components to compute auto indexing modiication i components to compute auto indexing modiication i
required required
Lxecute Lxecute
o o register bank is read register bank is read
o o ALU result generated ALU result generated
o o result written back into destination register result written back into destination register
o o in control low instructions ,pipeline reilling is done in control low instructions ,pipeline reilling is done
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!rocessor Modes !rocessor Modes
ARM has operating modes ARM has operating modes
User User
,unpriileged mode under which most tasks run, ,unpriileged mode under which most tasks run,
Iast Interrupt Request Mode IIQ Iast Interrupt Request Mode IIQ
,to handle high priority interrupt , ,to handle high priority interrupt ,
Interrupt Mode IRQ Interrupt Mode IRQ
,entered when a low priority interrupt is raised , ,entered when a low priority interrupt is raised ,
Supervisor Mode SVC Supervisor Mode SVC
,entered on reset or a sotware interrupt , ,entered on reset or a sotware interrupt ,
Abort Mode AB1 Abort Mode AB1
,used to handle memory access iolation, ,used to handle memory access iolation,
Undefined Mode UND Undefined Mode UND
,used to handle undeined instruction, ,used to handle undeined instruction,
System Mode SYS System Mode SYS
,uses same registers as user mode .added at ersion , ,uses same registers as user mode .added at ersion ,
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MODLS MODLS
Most application program run in User Mode Most application program run in User Mode
A program in user mode is unable to access some A program in user mode is unable to access some
protected system resources or to change mode , other protected system resources or to change mode , other
than by causing exception than by causing exception
Mode change can be by Mode change can be by
--Sotware control Sotware control
--Lxternal interrupts Lxternal interrupts
--Lxception processing Lxception processing
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MODLS MODLS
Modes other than user mode are called Modes other than user mode are called 5riritegea voae. 5riritegea voae.
!riileged modes has ull access to the system !riileged modes has ull access to the system
resources resources
lie o them are called exception modes lie o them are called exception modes
IIQ IIQ
IRQ IRQ
SVC SVC
AB1 AB1
UND UND
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MODLS MODLS
!rocessor enters into !riileged modes under !rocessor enters into !riileged modes under
speciic exception condition speciic exception condition
All the exception Modes uses some additional All the exception Modes uses some additional
registers ,to aoid corrupting the user state registers ,to aoid corrupting the user state
when exception occurs when exception occurs
S\S uses the same no: o registers as the User S\S uses the same no: o registers as the User
Mode Mode
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DA1A 1Y!LS DA1A 1Y!LS
Byte , 8 bit , : placed on any byte boundary Byte , 8 bit , : placed on any byte boundary
lal lal--\ord , 16 bit, : aligned to 2 byte boundaries \ord , 16 bit, : aligned to 2 byte boundaries
\ord , 32 bit , : aligned to byte boundaries \ord , 32 bit , : aligned to byte boundaries
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Data 1ypes Data 1ypes
\hen any o the type is deined as \hen any o the type is deined as :3.ig3ea :3.ig3ea ,the N bit ,the N bit
alue represents a non alue represents a non--negatie integer in the range negatie integer in the range 00 to to
2`^ 2`^ 11
when deined as when deined as .ig3ea .ig3ea the N bit alue represents an the N bit alue represents an
integer in the range integer in the range 2`;^ 2`;^ 1)to 2`;^ 1)to 2`;^ 1) 1) 11
All data operations a perormed on word quantities All data operations a perormed on word quantities
Load and store operations can transer all the data types Load and store operations can transer all the data types
rom and to the memory ,automatically zero extending rom and to the memory ,automatically zero extending
or sign extending bytes or hal or sign extending bytes or hal--words as they are loaded words as they are loaded
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RLGIS1LRS RLGIS1LRS
ARM has ARM has 32 bit long registers 32 bit long registers
30 general purpose registers 30 general purpose registers
5 dedicated 5 dedicated $$aed aed ! !rogram rogram $$tatus tatus ##egisters egisters
1 dedicated 1 dedicated urrent urrent ! !rogram rogram $$tatus tatus ##egister egister
1 dedicated program counter 1 dedicated program counter
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General !urpose Registers General !urpose Registers
0 0 32 bit registers 32 bit registers
15 general purpose registers are isible at one 15 general purpose registers are isible at one
time , depending on the current processor mode time , depending on the current processor mode
,as ,as r0,r1,r2 .r1,r11 r0,r1,r2 .r1,r11
r1 r1 conentionally used as stack pointer conentionally used as stack pointer
r11 r11 --conentionally used as link register to store conentionally used as link register to store
the return address or exception, sub the return address or exception, sub--routine routine
call call
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!rogram Counter !rogram Counter
!C is accessed as r15 !C is accessed as r15
Incremented by bytes or ARM state and 2 Incremented by bytes or ARM state and 2
bytes or 1lUMB state bytes or 1lUMB state
Branch instruction loads destination address into Branch instruction loads destination address into
the !C the !C
Can also be loaded using data operation Can also be loaded using data operation
instruction instruction
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!rogram Counter !rogram Counter
Due to pipelining , address o currently Due to pipelining , address o currently
executing instruction is typically !C executing instruction is typically !C--8 or ARM 8 or ARM
and !C and !C-- or 1lUMB or 1lUMB
lor ARM state bits 1 & 0 are always zero or lor ARM state bits 1 & 0 are always zero or
ignored ignored
lor 1lUMB state bit 0 is always zero or lor 1lUMB state bit 0 is always zero or
ignored ignored
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C!SR C!SR urrent urrent ! !rogram rogram $$tatus tatus ##egister egister
C!SR holds C!SR holds
Copies o ALU status lags Copies o ALU status lags
1he current processor mode 1he current processor mode
Interrupt disable lag Interrupt disable lag
ALU status lags are used to determine whether ALU status lags are used to determine whether
conditional instructions are executed or not conditional instructions are executed or not
On 1lUMB capable processors ,the C!SR On 1lUMB capable processors ,the C!SR
holds the current processor state holds the current processor state
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ILAGS ILAGS
Condition code flags Condition code flags
N(3J) N(3J) set to bit 31 o the result o the instruction set to bit 31 o the result o the instruction
N~0 i positie N~0 i positie
N~1 i negatie N~1 i negatie
(30) (30) ~1 i result is zero ~1 i result is zero
~0 i not zero ~0 i not zero
C(29) C(29) or addition ,set to 1 i carry occurs & 0 otherwise or addition ,set to 1 i carry occurs & 0 otherwise
or subtraction ,set to 0 i borrow occurs & 1 or subtraction ,set to 0 i borrow occurs & 1
otherwise otherwise
or shit operations , C contains the last bit shited or shit operations , C contains the last bit shited
VV (28) (28) or addition and subtraction V set to 1 i signed oerlow or addition and subtraction V set to 1 i signed oerlow
occurs occurs
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ILAGS ILAGS
Control bits Control bits
I(7) I(7) -- when set disables IRQ interrupt when set disables IRQ interrupt
I(6) I(6) - - when set disables lIQ interrupt when set disables lIQ interrupt
1(S) 1(S) - - on 1 ariants o 5 on 1 ariants o 5
1~0 ,indicates ARM execution 1~0 ,indicates ARM execution
1~1 ,indicates 1lUMB execution 1~1 ,indicates 1lUMB execution
on non on non--1 ariants 1 ariants
1~0,indicates ARM execution 1~0,indicates ARM execution
1~1,causes the next instruction executed 1~1,causes the next instruction executed
to cause UND to cause UND
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ILAGS ILAGS
MODL BI1S ,:0, MODL BI1S ,:0,
M(4:0) M(4:0) Mode Mode
10000 10000 User User
10001 10001 lIQ lIQ
10010 10010 IRQ IRQ
10011 10011 Superisor Superisor
10111 10111 Abort Abort
11011 11011 UND UND
11111 11111 S\S S\S
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S!SR S!SR $$aved aved ! !rogram rogram $$tatus tatus ##egister egister
Used to store C!SR when an exception is taken Used to store C!SR when an exception is taken
One S!RS is accessible in each o the exception One S!RS is accessible in each o the exception
handling mode handling mode
User Mode and System Mode doesn`t hae User Mode and System Mode doesn`t hae
S!RS as they don`t handle exceptions S!RS as they don`t handle exceptions
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General !urpose Registers General !urpose Registers
Can be diided into three groups Can be diided into three groups
Un Un--banked r0 banked r0--r r
Banked r8 Banked r8--r1 r1
!C r15 !C r15
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Un Un banked Registers banked Registers
Registers Registers r0 r0 to to r r
Lach o these registers address the same physical Lach o these registers address the same physical
registers or all the modes registers or all the modes
Completely general purpose registers , with no Completely general purpose registers , with no
uses implied by the architecture uses implied by the architecture
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Banked Registers Banked Registers
Registers Registers r r to to r11 r11
physical registers reerred to by each o them physical registers reerred to by each o them
depends on the mode o operation depends on the mode o operation
Banked register contents are presered across Banked register contents are presered across
operating mode changes operating mode changes
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Banked Registers Banked Registers
r8 to r12 r8 to r12
two banked physical registers each two banked physical registers each
one or lIQ and other or all other modes one or lIQ and other or all other modes
reerred to as r8_usr to r12_usr & r8_iq to r12_iq reerred to as r8_usr to r12_usr & r8_iq to r12_iq
r13 & r1 r13 & r1
has six banked registers each has six banked registers each
one in USLR & S\S and rest ie in each exception modes one in USLR & S\S and rest ie in each exception modes
reerred to as r13_mode,r1_mode reerred to as r13_mode,r1_mode,or exception modes, ,or exception modes,
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ARM RLGIS1LRS ARM RLGIS1LRS
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ARM RLGIS1LRS ARM RLGIS1LRS
r0
r1
r2
r3
r
r5
r6
r
r8
r9
r10
r11
r12
r13
r1
r15,!C,
C!SR
r0
r1
r2
r3
r
r5
r6
r
r8_iq
r9_iq
r10_iq
r11_iq
r12_iq
r13_iq
r1_iq
r15,!C,
C!SR
S!SR_iq
r0
r1
r2
r3
r
r5
r6
r
r8
r9
r10
r11
r12
r13_sc
r1_sc
r15,!C,
C!SR
S!SR_sc
r0
r1
r2
r3
r
r5
r6
r
r8
r9
r10
r11
r12
r13_abt
r1_abt
r15,!C,
C!SR
S!SR_abt
r0
r1
r2
r3
r
r5
r6
r
r8
r9
r10
r11
r12
r13_irq
r1_irq
r15,!C,
C!SR
S!SR_irq
r0
r1
r2
r3
r
r5
r6
r
r8
r9
r10
r11
r12
r13_und
r1_und
r15,!C,
C!SR
S!SR_und
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1humb State Register Set 1humb State Register Set
Is a subset o ARM set Is a subset o ARM set
1he programmer has access to 1he programmer has access to
8 general register r0 to r 8 general register r0 to r
!C !C
S! S!
LR LR
C!SR C!SR
S!SR, or exception modes, S!SR, or exception modes,
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Mapping of 1humb State registers to Mapping of 1humb State registers to
ARM State registers ARM State registers
r0
r1
r2
r3
r
r5
r6
r
r8
r9
r10
r11
r12
r13
r1
r15
C!SR
S!SR
r0
r1
r2
r3
r
r5
r6
r
S!
!C
C!SR
S!SR
LR
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Lxceptions & Interrupts Lxceptions & Interrupts
By deault the system is in User Mode By deault the system is in User Mode
Lnters exceptions modes when unexpected eents occur Lnters exceptions modes when unexpected eents occur
1here are 3 di types o exceptions ,some are called interrupts, 1here are 3 di types o exceptions ,some are called interrupts,
11as a direct result o executing an instruction as a direct result o executing an instruction
software interrupt request (SWI) software interrupt request (SWI)
undefined illegal instruction undefined illegal instruction
memory error during fetching an instruction memory error during fetching an instruction
22side side--eects o an instruction eects o an instruction
memory error during read/write from memory memory error during read/write from memory
arithmetic error arithmetic error
33result o external hardware signals result o external hardware signals
reset reset
fast interrupt fast interrupt
normal interrupt normal interrupt
contd contd
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Lxceptions & Interrupt Lxceptions & Interrupt
As the processor enters an exception mode As the processor enters an exception mode
,some new registers are automatically switched ,some new registers are automatically switched
in depending on the type o mode in depending on the type o mode
1his ensures that task state is not corrupted by 1his ensures that task state is not corrupted by
occurrence o an exception occurrence o an exception
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What happens when exception occurs What happens when exception occurs
ARM completes the current instruction as best ARM completes the current instruction as best
as it can as it can
Departs rom current instruction to handle the Departs rom current instruction to handle the
exception through ollowing steps exception through ollowing steps
1) 1) .are. tbe c:rre3t ! i3 r11 .are. tbe c:rre3t ! i3 r11 corresponding to the new corresponding to the new
mode mode
2) 2) .are. !$# .are. !$# i3 i3 corresponding corresponding $!#$ $!#$ o new mode o new mode
) ) cba3ge. tbe o5erati3g voae cba3ge. tbe o5erati3g voae corresponding to an corresponding to an
exception exception
contd contd--
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, , ai.abte. ece5tio3. of torer 5riorit, ai.abte. ece5tio3. of torer 5riorit,
5, 5, force. ! to a 3er rat:e force. ! to a 3er rat:e corresponding to exception. corresponding to exception.
Lectiely orce jumps the instruction stream to Lectiely orce jumps the instruction stream to
ce5tio3 a3ater ce5tio3 a3ater or or 3terr:5t $errice #o:ti3e.. 3terr:5t $errice #o:ti3e..
a a :3iq:e aaare.. :3iq:e aaare.. is predeined or each is predeined or each
exception handler exception handler
address to which the processor is orced to address to which the processor is orced to
branch is called branch is called ece5tio3,i3terr:5t rector ece5tio3,i3terr:5t rector
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Lxception/Interrupt Vector Lxception/Interrupt Vector
Lach ector ,except lIQ, is bytes long Lach ector ,except lIQ, is bytes long
Branch instruction is put at this address Branch instruction is put at this address
Undeined Instruction Undeined 0x0000000 0xllll000
Sotware Interrupt Superisor 0x00000008 0xllll0008
!re-etch Abort Abort 0x0000000C 0xllll000C
Data Abort Abort 0x00000010 0xllll0010
IRQ ,interrupt, IRQ 0x00000018 0xllll0018
lIQ ,ast interrupt, lIQ 0x0000001C 0xllll001C
Reset Superisor 0x00000000 0xllll0000
Lxception type Mode Vector add: ligh Vector add:
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Lxception Return Lxception Return
Once the exception has been handled ,by the exception handler,
,the user task is resumed.
1he handler program ,or Interrupt Serice Routine, must
restore the user state exactly as it was beore the exception
occurred:
1. Any modiied user registers must be restored rom the handler
stack
2. 1he C!SR must be restored rom the appropriate S!SR
3. !C must be changed back to the instruction address in the user
instruction stream
Steps 1 and 3 are done by user, step 2 by the processor
Restoring registers rom the stack would be the same as in the
case o subroutines
Restoring !C alue is more complicated. 1he exact way to do it
depends on which exception you are returning rom.
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Lxception Return Lxception Return
\e assume that the return address was saed in r1 beore
entering the exception handler.
1,1o return rom a S\I or undeined instruction trap, use:
MOVS pc, r1
2,1o return rom an IRQ, lIQ or pre-etch abort, use.
SUBS pc, r1, 4
3,1o return rom a data abort to retry the data access, use:
SUBS pc, r1, 48
1hree methods are because !C alue can be 1 or 2 instructions
ahead due to pipelining
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Interrupt !riority Interrupt !riority
Since exceptions can arise at the same time, a priority
order has to be clearly deined. lor the ARM processor
this is:
1, Reset ,highest priority,
2, Data abort ,i.e. Memory ault in read,write data,
3, last Interrupt Request ,lIQ,
, Normal Interrupt Request ,IRQ,
5, !re-etch abort
6, Sotware Interrupt ,S\I,, undeined instruction
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ARM71DMI Core ARM71DMI Core
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Internal organization of ARM Internal organization of ARM
1wo main blocks: data-path and decoder
Register bank ,r0 to r15,
1wo read ports to A-bus,B-bus
One write port rom ALU-bus
Additional read,write ports or program counter r15
Barrel shiter - shit,rotate 2
nd
operand by any number o bits
ALU perorms arithmetic,logic unctions
Address registers,incrementer holds either !C address ,with
increment, or operand address
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Internal organization of ARM Internal organization of ARM
Data register holds read,write data rom,to memory
Instruction decoder decodes machine code instructions
to produce control signals to data-path
In single-cycle data processing instructions, data alues
are read on the A-bus & B-bus, the results rom ALU is
written back into register bank
!C alue in address register is incremented and copied
back to r15 and the address register - this allows
etching new instructions ahead o time ,instruction
pre-etch,
In case o branching ,next pre-etch address is taken
rom ALU rather than the address incrementer .1he
instruction pipeline is illed beore any urther
execution takes place.
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Datapath activity during data processing
instruction
Subtract instruction - one
operand is a constant
Constant 128 encoded in
instruction passes through
barrel shiter to produce 1288
ALU operates on the operands
and writes
the result back to register r0
!C alue in address register is
incremented and coped back to
r15 and the address register
SUB r0, r1, 4128 LSL 43 , r0 :~ r1 - 1288
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Memory Memory Address Space Address Space
ARM uses single lat address space o 2`32 ARM uses single lat address space o 2`32 bytes bytes
Byte address are treated as unsigned ,running rom 0 Byte address are treated as unsigned ,running rom 0
to 2`31 to 2`31--11
1he address space is regarded as consisting o 2`30 1he address space is regarded as consisting o 2`30
32 bit words,each o whose addresses is word aligned 32 bit words,each o whose addresses is word aligned
\ord ,whose word aligned address is A` ,consists o \ord ,whose word aligned address is A` ,consists o
our bytes with address A , A-1 , A-2 , A-3 our bytes with address A , A-1 , A-2 , A-3
lrom and aboe address space is also considered lrom and aboe address space is also considered
as 2`31 16 as 2`31 16--bit halwords bit halwords
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Lndianness Lndianness
Memory system uses one o the 2 mapping schemes to Memory system uses one o the 2 mapping schemes to
map between word ,hal map between word ,hal--word & byte word & byte
1, 1, tittte tittte e3aia3 .,.tev: e3aia3 .,.tev:
==a byte or halword at a word a byte or halword at a word--aligned address is the least aligned address is the least
signiicant byte or halword within the word at that address signiicant byte or halword within the word at that address
==a byte at a halword a byte at a halword--aligned address is least signiicant byte aligned address is least signiicant byte within within
the hal word at that address the hal word at that address
\ord at address A \ord at address A
lalword at add: lalword at add: A-1 A-1 lalword at add: lalword at add: A A
Byte at A-3 Byte at A-3 Byte at A-2 Byte at A-2 Byte at A-1 Byte at A-1 Byte at A Byte at A
11/2/2011 57
2, 2, big big e3aia3 .,.tev: e3aia3 .,.tev:
==a byte or halword at a word aligned address is the most a byte or halword at a word aligned address is the most
signiicant byte or halword within the word at that address signiicant byte or halword within the word at that address
==a byte at a halword aligned address is most signiicant a byte at a halword aligned address is most signiicant byte byte
within the hal word at that address within the hal word at that address
ARM instruction set doesn`t contain any instruction that can ARM instruction set doesn`t contain any instruction that can
directly select the endianness .Instead a hardware input is used to directly select the endianness .Instead a hardware input is used to
conigure an ARM implementation to the memory system conigure an ARM implementation to the memory system
\ord at address A \ord at address A
lalword at add: lalword at add: A A lalword at add: lalword at add: A-1 A-1
Byte at A Byte at A Byte at A-1 Byte at A-1 Byte at A-2 Byte at A-2 Byte at A-3 Byte at A-3
11/2/2011 58
Memory mapped I/O Memory mapped I/O
Standard way to perorm I,O unctions on Standard way to perorm I,O unctions on
ARM systems is by the use o memory mapped ARM systems is by the use o memory mapped
I,O I,O
1his uses special memory addresses which 1his uses special memory addresses which
supply I,O unctions when they are loaded supply I,O unctions when they are loaded
rom or stored to rom or stored to
Loading rom memory mapped I,O address is Loading rom memory mapped I,O address is
used or input ,and storing to memory mapped used or input ,and storing to memory mapped
I,O address is or output I,O address is or output
11/2/2011 59
Instruction fetches from memory mapped I/O Instruction fetches from memory mapped I/O
Behaior o memory mapped I,O usually ary Behaior o memory mapped I,O usually ary
rom that expected o a normal memory rom that expected o a normal memory
location location
lro eg: ,two successie loads rom same location lro eg: ,two successie loads rom same location
may not yield the same result ,as expected rom may not yield the same result ,as expected rom
a normal memory. a normal memory.
As a result ,it is recommended that memory As a result ,it is recommended that memory
mapped I,O not be used or instruction etch mapped I,O not be used or instruction etch
11/2/2011 60
Data access to memory mapped I/O Data access to memory mapped I/O
I memory words ,halwords or bytes accessed by the I memory words ,halwords or bytes accessed by the
code sequence are memory mapped I,O locations, one code sequence are memory mapped I,O locations, one
access can generate a side eect which changes the access can generate a side eect which changes the
results o a subsequent access to a dierent location results o a subsequent access to a dierent location
I this happens the time order o indiidual accesses I this happens the time order o indiidual accesses
makes a dierence to the inal result o the code makes a dierence to the inal result o the code
sequence sequence
It is also important that data size o the memory access It is also important that data size o the memory access
be maintained ,when accessing memory mapped I,O be maintained ,when accessing memory mapped I,O
lor eg: a code sequence that speciies our byte reads lor eg: a code sequence that speciies our byte reads
rom our subsequent address must not be merged into rom our subsequent address must not be merged into
a single word read a single word read
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Data access to memory mapped I/O Data access to memory mapped I/O
1ypical requirements includes 1ypical requirements includes
Constraints on memory attributes o the memory mapped Constraints on memory attributes o the memory mapped
I,O .lor eg: ,in the standard memory system architecture I,O .lor eg: ,in the standard memory system architecture
,memory locations must be uncachable and unbuerable ,memory locations must be uncachable and unbuerable
Constraints on the sizes or alignments o the access to the Constraints on the sizes or alignments o the access to the
memory mapped I,O locations. lor eg: i an ARM memory mapped I,O locations. lor eg: i an ARM
implementation has a 16 implementation has a 16--bit external bus ,it might the use o bit external bus ,it might the use o
32 32--bit access to the memory mapped I,O locations since they bit access to the memory mapped I,O locations since they
cant be perormed in a single bus cycle cant be perormed in a single bus cycle
A requirement or additional hardware .lor eg: ,an A requirement or additional hardware .lor eg: ,an
alternatie possibility or an ARM implementation with a 16 alternatie possibility or an ARM implementation with a 16
bit external bus is to allow 32 bit external bus is to allow 32--bit access to memory ,but bit access to memory ,but
require external hardware to reassemble the two 16 require external hardware to reassemble the two 16- -bit bit
accesses into a single 32 accesses into a single 32--bit access to the I,O deice. bit access to the I,O deice.
11/2/2011 62
ARM 7 ARM9 ARM 7 ARM9
Core has Von Neumann Core has Von Neumann
architecture ,with single 32bit architecture ,with single 32bit
data bus carrying both data bus carrying both
instruction and data instruction and data
C!I ~1.9 C!I ~1.9
Uses 3 stage pipeline Uses 3 stage pipeline
letch letch
Decode Decode
Lxecute Lxecute
Implements Implements BASL U!DA1LD BASL U!DA1LD
DA1A ABOR1 MODLL DA1A ABOR1 MODLL
Doesn`t implement extension Doesn`t implement extension
spaces as spaces as UNDLIINLD UNDLIINLD
Core has larard Core has larard
architecture, with separate architecture, with separate
buses or data and instruction buses or data and instruction
C!I~1.5 C!I~1.5
Uses 5 stage pipeline Uses 5 stage pipeline
Instruction etch Instruction etch
Instruction decode Instruction decode
Lxecute Lxecute
Data memory access Data memory access
Register write Register write
Implements Implements BASL RLS1ORLD BASL RLS1ORLD
DA1A ABOR1 MODLL DA1A ABOR1 MODLL
Implements all the Implements all the
instruction set extension instruction set extension
spaces as spaces as UNDLIINLD UNDLIINLD
11/2/2011 SHANKAR NARAYAN P.S 63
ARM ASSLMBLY LANGUAGL ARM ASSLMBLY LANGUAGL
!ROGRAMING !ROGRAMING
An Introduction to Instruction Set. An Introduction to Instruction Set.
11/2/2011 64
ARM Instruction 1ypes ARM Instruction 1ypes
32 bit ARM Instruction set. 32 bit ARM Instruction set.
16 bit 1humb instruction set. 16 bit 1humb instruction set.
Can be urther diided in to ollowing types. Can be urther diided in to ollowing types.
Data processing instructions. Data processing instructions.
Data transer instructions. Data transer instructions.
Control low instructions. Control low instructions.
Coprocessor instructions. Coprocessor instructions.
Breakpoint instructions. Breakpoint instructions.
11/2/2011 65
ARM Instruction format ARM Instruction format
U U -- Up the stack. Up the stack.
S S -- Set condition code bit. 1his says whether the Set condition code bit. 1his says whether the
data processing instruction should aect the data processing instruction should aect the
lags or not. lags or not.
\ \ -- write back. write back.
L L -- Load,Store. Load,Store.
N N -- Data size. Data size.
11/2/2011 66
11/2/2011 67
ARM Instruction format ARM Instruction format
Rn, Rs, Rm Rn, Rs, Rm - - Used or sourse registers. Used or sourse registers.
Rd Rd -- Destination registers. Destination registers.
Rdli Rdli -- Most signiicant 32 bits o destination Most signiicant 32 bits o destination
register. register.
RdLo RdLo -- Least signiicant 32 bits o destination Least signiicant 32 bits o destination
register. register.
11/2/2011 68
About the condition field. About the condition field.
Ordinary instruction set allow branches to be Ordinary instruction set allow branches to be
executed conditionally. executed conditionally.
Arm instructions contain a condition ield Arm instructions contain a condition ield
within itsel which determines whether the cpu within itsel which determines whether the cpu
is going to execute them or not. is going to execute them or not.
1he time penalty o not executing seeral 1he time penalty o not executing seeral
conditional instructions is usually less than the conditional instructions is usually less than the
oerhead o branch that would be otherwise oerhead o branch that would be otherwise
needed. 1he branch instructions usually stall the needed. 1he branch instructions usually stall the
pipeline which is remoed ,3 cycles to reill,. pipeline which is remoed ,3 cycles to reill,.
11/2/2011 69
Condition Iield Condition Iield
1he Last bits o the opcode constitute the 1he Last bits o the opcode constitute the
condition ield. 1hey represent the ollowing. condition ield. 1hey represent the ollowing.
11/2/2011 70
Condition Iield Condition Iield
11/2/2011 71
Data !rocessing Instructions Data !rocessing Instructions
Contains Contains
Arithmetic operations Arithmetic operations
Comparisons Comparisons
Logical operations Logical operations
Data Moement between Registers. Data Moement between Registers.
Important thing to note is that these instructions Important thing to note is that these instructions
ca33ot ror/ o3 vevor, ca33ot ror/ o3 vevor, they they ror/ o3t, o3 #egi.ter. ror/ o3t, o3 #egi.ter.
since ARM incorporates LOAD,S1ORL since ARM incorporates LOAD,S1ORL
Architecture. Architecture.
11/2/2011 72
Arithmetic Operations Arithmetic Operations
Syntax Syntax
operationcond}S} Rd, Rn, operand2 operationcond}S} Rd, Rn, operand2
Operations are Operations are
ADD ADD -- operand1 - operand2 operand1 - operand2
ADC ADC -- operand1 - operand2 - carry operand1 - operand2 - carry
SUB SUB -- operand1 operand1 -- operand2 operand2
SBC SBC -- operand1 operand1 -- operand2 - carry operand2 - carry -- 11
RSB RSB -- operand2 operand2 -- operand1 operand1
RSC RSC -- operand2 operand2 -- operand1 - carry operand1 - carry -- 1 1
Reerse subtraction is required because operand1 Reerse subtraction is required because operand1
is always a register is always a register
11/2/2011 73
With Immediate Operands With Immediate Operands
Syntax Syntax
operationcond}S} Rd, Rn, 4immediate al operationcond}S} Rd, Rn, 4immediate al
Operations are Operations are
ADD ADD -- operand1 - immediate alue operand1 - immediate alue
ADC ADC -- operand1 - immediate alue - carry operand1 - immediate alue - carry
SUB SUB -- operand1 operand1 -- immediate alue immediate alue
SBC SBC -- operand1 operand1 -- immediate alue - carry immediate alue - carry -- 11
Note : Only 12 bits are aailable to store the Note : Only 12 bits are aailable to store the
immediate operand. immediate operand.
11/2/2011 74
Immediate Operands Immediate Operands
1hen how do we put a 32 bit immediate operand 1hen how do we put a 32 bit immediate operand
1he most important thing to be taken care while 1he most important thing to be taken care while
writing the 32 bit immediate operand is that it writing the 32 bit immediate operand is that it
should be a Legitimate one. should be a Legitimate one.
\hat are these legitimate immediate alues \hat are these legitimate immediate alues
Any 32 bit or lesser alue which can be expressed as an Any 32 bit or lesser alue which can be expressed as an
8 bit alue and a our bit shit. 8 bit alue and a our bit shit.
1his shit alue is multiplied by 2 beore actually 1his shit alue is multiplied by 2 beore actually
perorming the shit. perorming the shit.
11/2/2011 75
Immediate Operands Immediate Operands
Lxample MOV r0, 4096 Lxample MOV r0, 4096
Uses 0x0 as 8 bit operand and shits RIGl1 by 26. Uses 0x0 as 8 bit operand and shits RIGl1 by 26.
Beore storing this 26 is stored as 26,2 ~ 13 ~ 0xD. Beore storing this 26 is stored as 26,2 ~ 13 ~ 0xD.
1he instruction as MOV r0, 4096 is stored as, 1he instruction as MOV r0, 4096 is stored as,
So the operand speciied must hae a property that So the operand speciied must hae a property that
it can be expressed as it can be expressed as
8 bit al rotated right by an LVLN amount. 8 bit al rotated right by an LVLN amount.
20 bits for opcode and Register 20 bits for opcode and Register 0x40D 0x40D
11/2/2011 76
Immediate Operands Immediate Operands
So the alues that cannot be generated this way So the alues that cannot be generated this way
will cause an error will cause an error
Let us see this example Let us see this example
ADD r1, r2, 40x0000 , Note that the alue is lex,. ADD r1, r2, 40x0000 , Note that the alue is lex,.
Uses 0x ROR 16 Uses 0x ROR 16
So processor stores it as, So processor stores it as,
20 bits for opcode and Register 20 bits for opcode and Register 0xff8 0xff8
11/2/2011 77
Logical Operations Logical Operations
Syntax Syntax
operationcond}S} Rd, Rn, operand2 operationcond}S} Rd, Rn, operand2
Operations are Operations are
AND AND -- operand1 AND operand2 operand1 AND operand2
LOR LOR -- operand1 LOR operand2 operand1 LOR operand2
ORR ORR -- operand1 OR operand2 operand1 OR operand2
BIC BIC -- operand1 AND NO1 operand2 | can be Bit clear| operand1 AND NO1 operand2 | can be Bit clear|
11/2/2011 78
Comparisons Comparisons
Only eect is to update the condition lags thus Only eect is to update the condition lags thus
no need to set S bit. 1hey don`t write the result. no need to set S bit. 1hey don`t write the result.
Syntax Syntax
operationcond}Rn, operand2 operationcond}Rn, operand2
Operations are Operations are
CM! CM! -- operand1 operand1 -- operand2 operand2
CMN CMN -- operand1 - operand2 operand1 - operand2
1S1 1S1 -- operand1 AND operand2 operand1 AND operand2
1LQ 1LQ -- operand1 LOR operand2 operand1 LOR operand2
11/2/2011 79
Branch Instructions Branch Instructions
1ype1 1ype1 -- Branch to a label Branch to a label
Syntax Syntax -- Bcond} Label Bcond} Label
Oset or the branch is calculated by the Oset or the branch is calculated by the
assembler in ollowing way once a branch assembler in ollowing way once a branch
instruction is encountered. instruction is encountered.
Oset ~ addr o branch inst Oset ~ addr o branch inst -- |target addr |target addr -- 8| 8|
--8 is to account or the pipeline which !C handles. 8 is to account or the pipeline which !C handles.
1he oset can be up to 26 bits. 1his oset is always 1he oset can be up to 26 bits. 1his oset is always
obtained with bottom 2 bits 0. 1hus 26 bit oset is obtained with bottom 2 bits 0. 1hus 26 bit oset is
right shited by 2 and stored in instruction encoding. right shited by 2 and stored in instruction encoding.
1he Range is 1he Range is 32 MB. 32 MB.
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Branch Instructions Branch Instructions
1ype2 1ype2 -- Branch to a subroutine ,Called Branch Branch to a subroutine ,Called Branch
with Link, with Link,
Syntax Syntax -- BLcond} Sub_routine_label. BLcond} Sub_routine_label.
BL is identiied using the link bit in the opcode. BL is identiied using the link bit in the opcode.
Implements a subroutine call by writing !C Implements a subroutine call by writing !C --
to Link Register ,lr, o the current bank. to Link Register ,lr, o the current bank.
Note that this will put the address o the next Note that this will put the address o the next
instruction ollowing the branch, since !C is ahead instruction ollowing the branch, since !C is ahead
by 3 instructions by 3 instructions..
1o return rom the subroutine we simply need 1o return rom the subroutine we simply need
to restore !C rom LR. ,Mo pc, lr, to restore !C rom LR. ,Mo pc, lr,
11/2/2011 81
1he Barrel Shifter 1he Barrel Shifter
ARM does not support independent shit ARM does not support independent shit
instructions. Instead it supports a Barrel Shiter instructions. Instead it supports a Barrel Shiter
which can proide shits as a part o other which can proide shits as a part o other
instructions. instructions.
Barrel Shiter supports seeral actions like Barrel Shiter supports seeral actions like
Let shit Let shit
Right shits Right shits
Rotations Rotations
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Barrel Shifter Barrel Shifter Left Shift Left Shift
Shits the II operand in the instruction to its let, Shits the II operand in the instruction to its let,
by speciied amount. by speciied amount.
Syntax Syntax
data processing instruction, LSL immediate No. data processing instruction, LSL immediate No.
data processing instruction, LSL register data processing instruction, LSL register
Lxample Lxample
ADD r0, r1, r1, LSL 42 ADD r0, r1, r1, LSL 42
Means r0 ~ r1 - r1 Means r0 ~ r1 - r1
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Barrel Shifter Right Shifts Barrel Shifter Right Shifts
Logical shit right ,LSR, Logical shit right ,LSR,
Diides by power o two Diides by power o two
Used with other instructions as in case o LSL Used with other instructions as in case o LSL
Diides by power o two Diides by power o two
Lxample Lxample
LSR 45 is diiding by 32 LSR 45 is diiding by 32
Syntax similar to let shit. Syntax similar to let shit.
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Barrel Shifter Right Shifts Barrel Shifter Right Shifts
Arithmetic shit right ,ASR,. Arithmetic shit right ,ASR,.
Shits right, and preseres the sign bit or 2`s Shits right, and preseres the sign bit or 2`s
complement operations. complement operations.
i.e. it copies the last bit to the remaining bits. i.e. it copies the last bit to the remaining bits.
Used with other instructions as in case o LSR Used with other instructions as in case o LSR
11/2/2011 85
Barrel Shifter Barrel Shifter Rotations Rotations
Rotate Right ,ROR,. Rotate Right ,ROR,.
Similar to LSR but the bits which leaes the LSB o Similar to LSR but the bits which leaes the LSB o
the register appear as the MSB o the register. the register appear as the MSB o the register.
1he bit which leaes the LSB is also copied to the 1he bit which leaes the LSB is also copied to the
Cl Cl
Used with other instructions similar to the shit Used with other instructions similar to the shit
instructions. instructions.
Rotate Right Lxtended ,RRX,. Rotate Right Lxtended ,RRX,.
Similar to rotate right but uses the carry as the 33 Similar to rotate right but uses the carry as the 33
rd rd
bit. bit.
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Barrel Shifter Barrel Shifter
LSL LSL
LSR LSR
RLGIS1LR
Cl
0
RLGIS1LR
0
Cl
11/2/2011 87
Barrel Shifter Barrel Shifter
ASR ASR
ROR ROR
RLGIS1LR Cl
RLGIS1LR Cl
11/2/2011 88
Barrel Shifter Barrel Shifter
RRX RRX
,Rotate Right through Carry, ,Rotate Right through Carry,
RLGIS1LR Cl
11/2/2011 89
Multiplication Instructions Multiplication Instructions
1here are two multiplication instructions. 1here are two multiplication instructions.
Multiply Multiply
Syntax : MUL cond}S} Rd, Rm, Rs Syntax : MUL cond}S} Rd, Rm, Rs
Rd ~ Rm Rs Rd ~ Rm Rs
Multiply and accumulate Multiply and accumulate
Does addition along with multiplication with the third Does addition along with multiplication with the third
register operand speciied, and stores the end result in the register operand speciied, and stores the end result in the
destination. destination.
Syntax : MLAcond}S} Rd, Rm, Rs, Rn Syntax : MLAcond}S} Rd, Rm, Rs, Rn
Rd ~ ,Rm Rs, - Rn Rd ~ ,Rm Rs, - Rn
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Limitations of MUL Limitations of MUL
Rd and Rm cannot be the same register. Rd and Rm cannot be the same register.
Cannot use program counter. Cannot use program counter.
Operands can be considered signed or unsigned, Operands can be considered signed or unsigned,
the user should interpret correctly the user should interpret correctly
11/2/2011 91
Data Movement Data Movement
1he MOV instruction 1he MOV instruction
Syntax : MOVcond}S} Rd, operand2 Syntax : MOVcond}S} Rd, operand2
Moes operand 2 into destination register. Moes operand 2 into destination register.
Note that there is no use o operand1 which means Note that there is no use o operand1 which means
that there can be an immediate data. that there can be an immediate data.
1he MVN instruction 1he MVN instruction
Syntax same as the MOV instruction Syntax same as the MOV instruction
Moes NO1 operand2 into destination register. Moes NO1 operand2 into destination register.
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Load Store Instructions Load Store Instructions
1he ARM is a load store architecture 1he ARM is a load store architecture
Does not support memory to memory data processing Does not support memory to memory data processing
Must moe to registers beore using them. Must moe to registers beore using them.
!rocess becomes much aster due to register access to !rocess becomes much aster due to register access to
process data. process data.
1here are three sets o instructions which can 1here are three sets o instructions which can
interact with main memory, they are interact with main memory, they are
Single register data transer Single register data transer
Block data transer Block data transer
Single data swap Single data swap
11/2/2011 93
Single Register Data 1ransfer Single Register Data 1ransfer
Load or store a word ,LDR,S1R, Load or store a word ,LDR,S1R,
Syntax : LDR,S1Rcond} Rd,Rs, address Syntax : LDR,S1Rcond} Rd,Rs, address
lor LDR Rd and or S1R Rs as a case may be lor LDR Rd and or S1R Rs as a case may be
address o the memory can be expressed in many address o the memory can be expressed in many
addressing modes which will be discussed shortly. addressing modes which will be discussed shortly.
Load or store a byte Load or store a byte
Syntax : LDR,S1Rcond}B} Rd,Rs,address Syntax : LDR,S1Rcond}B} Rd,Rs,address
Note that B is to be attached ater condition i any. Note that B is to be attached ater condition i any.
11/2/2011 94
Single Register Data 1ransfer Single Register Data 1ransfer
ARM architecture ersion also adds support or ARM architecture ersion also adds support or
hal words. hal words.
Syntax : LDR,S1Rcond}l} Rd,Rs,address Syntax : LDR,S1Rcond}l} Rd,Rs,address
11/2/2011 95
Addressing Modes Addressing Modes
Register Indirect addressing mode Register Indirect addressing mode
Address o the source Memory location ,or Load, Address o the source Memory location ,or Load,
or the destination memory location ,or Store, as a or the destination memory location ,or Store, as a
case may be, is gien by the contents o an internal case may be, is gien by the contents o an internal
register. register.
Lxamples: Lxamples:
S1R ro, |r1| S1R ro, |r1|
LDR r2, |r1| LDR r2, |r1|
11/2/2011 96
Addressing Modes Addressing Modes
S1R r0, |r1| works this way. S1R r0, |r1| works this way.
..
..
..
0x5 0x5
..
..
..
..
..
0xJ00
0xS
0xJ00
Ro
RJ
11/2/2011 97
Indexed Addressing Indexed Addressing
Instructions in ARM are capable o accessing a Instructions in ARM are capable o accessing a
location oset rom the base address speciied. location oset rom the base address speciied.
1his oset can be 1his oset can be
An unsigned 12 bit immediate alue. An unsigned 12 bit immediate alue.
A register, optionally shited using barrel shit. A register, optionally shited using barrel shit.
Added or subtracted rom the base register. Added or subtracted rom the base register.
Applied beore transer : !re Applied beore transer : !re -- indexed Addressing. indexed Addressing.
Applied ater transer : !ost Applied ater transer : !ost -- indexed Addressing. indexed Addressing.
11/2/2011 98
!re !re Indexed Addressing Indexed Addressing
Lxample : LDR r0,|r1, 412| Lxample : LDR r0,|r1, 412|
Oset addition |r1| - 12 is done beore transer Oset addition |r1| - 12 is done beore transer
1ranser to r0 is made rom the 1ranser to r0 is made rom the newly available newly available address. address.
, aefa:tt tbe ba.e regi.ter r1 i. 3ot :5aatea. , aefa:tt tbe ba.e regi.ter r1 i. 3ot :5aatea.
1o update the base register, use LDR r0, |r1,412|! 1o update the base register, use LDR r0, |r1,412|!
LDR r0, |r1,r3| can be used i r3 contains 12. LDR r0, |r1,r3| can be used i r3 contains 12.
LDR r0, |r1,r3,LSL 42| can be used i r3 contains 3. LDR r0, |r1,r3,LSL 42| can be used i r3 contains 3.
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!re !re Indexed Addressing Indexed Addressing
low LDR r0,|r1, 412| works low LDR r0,|r1, 412| works
..
..
..
0x5 0x5
..
..
..
..
..
0xJ00
0xS
0xJ0C
Ro
RJ
J2
offset
+
RJ
11/2/2011 100
!ost !ost Indexed Addressing Indexed Addressing
Lxample : LDR r0,|r1|, 412 Lxample : LDR r0,|r1|, 412
Oset addition |r1| - 12 is done ater transer Oset addition |r1| - 12 is done ater transer
1ranser to r0 is made rom the 1ranser to r0 is made rom the current current address. address.
, aefa:tt tbe ba.e regi.ter r1 i. :5aatea. , aefa:tt tbe ba.e regi.ter r1 i. :5aatea.
Makes sense only when there is updating. Makes sense only when there is updating.
LDR r0, |r1|, 4 LDR r0, |r1|, 4--12 can be used to go to 0x. 12 can be used to go to 0x.
LDR r0, |r1,r3,LSL 42| can be used i r3 contains 3. LDR r0, |r1,r3,LSL 42| can be used i r3 contains 3.
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!ost !ost Indexed Addressing Indexed Addressing
low LDR r0,|r1|, 412 works low LDR r0,|r1|, 412 works
..
..
..
0x5 0x5
..
..
..
..
..
0xJ00
0xS
0xJ00 Ro
RJ
J2
offset
+
0xJ0C
RJ
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Block Data 1ransfer Block Data 1ransfer
1he Load or Store Multiple instructions allow us to 1he Load or Store Multiple instructions allow us to
transer data rom or into registers b,w 1 and 16. transer data rom or into registers b,w 1 and 16.
1ranserred registers can be either 1ranserred registers can be either
Subset o current bank Subset o current bank
Any subset o user mode registers when in a priileged Any subset o user mode registers when in a priileged
mode. mode.
1hey are ery eicient or saing and restoring context. 1hey are ery eicient or saing and restoring context.
Moing large blocks o data around memory Moing large blocks o data around memory
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Block Data 1ransfer Block Data 1ransfer
1hese are ew instructions used. 1hese are ew instructions used.
LDMIA,S1MIA : ,LDMultiple,S1Multiple, LDMIA,S1MIA : ,LDMultiple,S1Multiple,
Increment Ater ,Load,Store,. Increment Ater ,Load,Store,.
Lxamples: Lxamples:
LDMIA r0,r2 LDMIA r0,r2 --r9} r9}
Means Means
Load registers r2 to r9 with data present in 8 Load registers r2 to r9 with data present in 8
successie locations whose I address ,Base successie locations whose I address ,Base
address, is in r0. Increment r0 ater load. ro is not address, is in r0. Increment r0 ater load. ro is not
updated updated
Arm supports many o these kind which will Arm supports many o these kind which will
be listed out shortly. be listed out shortly.
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Stacks Stacks
Stack is an area o the memory which works on Stack is an area o the memory which works on
the LIlO algorithm. the LIlO algorithm.
1wo pointers deine the current limits o the 1wo pointers deine the current limits o the
stack. stack.
1he base pointer which points to the bottom o the 1he base pointer which points to the bottom o the
stack stack
1he stack pointer which points to current 1O! o 1he stack pointer which points to current 1O! o
the stack. the stack.
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Stacks Stacks
!USl ~ I Decrement and then push. !USl ~ I Decrement and then push.
!O! ~ I !O! and then Increment. !O! ~ I !O! and then Increment.
33
22
11
S!
S!
INI1IAL After !USH {J,2,3]
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Stacks Stacks
1he !O! operation 1he !O! operation
33
22
11
S!
INI1IAL
22
11
S!
After !O! 3
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Stacks Stacks
Usual procedure is that the stack grows in size as Usual procedure is that the stack grows in size as
what is already seen. ARM readily supports this. what is already seen. ARM readily supports this.
In addition to this ARM supports the ollowing In addition to this ARM supports the ollowing
types o stack. types o stack.
lull Descending stack lull Descending stack
lull Ascending stack lull Ascending stack
Lmpty Descending stack Lmpty Descending stack
Lmpty Ascending stack Lmpty Ascending stack
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Stack Lxamples Stack Lxamples
33
22
11
33
22
11
0xJ06
0xJ0S
0xJ00
.
.
.
.
.
.
.
.
Initial S!
S!
Initial S!
S!
IULL DLSCLNDING
LM!1Y DLSCNDING
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Stack Lxamples Stack Lxamples
11
22
33
11
22
33
0xJ06
0xJ0S
0xJ00
.
.
.
.
.
.
.
.
S!
Initial S!
S!
Initial S!
LM!1Y DLSCLNDING
IULL ASCLNDING
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Stacks Stacks
1he multiple Load,Store instructions can also 1he multiple Load,Store instructions can also
be used to transer the data rom or to the stack. be used to transer the data rom or to the stack.
Depending on the type o stack we hae the Depending on the type o stack we hae the
ollowing orms. ollowing orms.
S1MlD,LDMlD S1MlD,LDMlD
S1MlA,LDMlA S1MlA,LDMlA
S1MLD,LDMLD S1MLD,LDMLD
S1MLA,LDMLA S1MLA,LDMLA
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Block Data 1ransfer Block Data 1ransfer
!utting it all together we hae. !utting it all together we hae.
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Block Data 1ransfer Block Data 1ransfer
lew tips while using block data transer. lew tips while using block data transer.
1he base register in the instruction can be updated 1he base register in the instruction can be updated
each time using ! Symbol each time using ! Symbol
Lxample : S1MlD sp!, r0 Lxample : S1MlD sp!, r0 -- r12} r12}
1he destination register set need not be continuous 1he destination register set need not be continuous
one. \e can speciy dierent registers using , one. \e can speciy dierent registers using ,
Lxample : LDMIA r0, r1,r,r6} Lxample : LDMIA r0, r1,r,r6}
Lxample : LDMA r0, r1, r3 Lxample : LDMA r0, r1, r3 -- r5} r5}
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Control Ilow Instructions Control Ilow Instructions
1he ollowing are to be discussed. 1he ollowing are to be discussed.
Branch Instructions Branch Instructions
Conditional branch instructions. Conditional branch instructions.
Branch and link instructions Branch and link instructions
Subroutines. Subroutines.
Superisor calls Superisor calls
Jump calls. Jump calls.
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Control Ilow Instructions Control Ilow Instructions
1he unconditional branch 1he unconditional branch
B Label : Branch unconditionally to the speciied B Label : Branch unconditionally to the speciied
label. label.
1he conditional branch instruction. 1he conditional branch instruction.
Bcondition Label. Bcondition Label.
Branches to speciied label depending on the Branches to speciied label depending on the
condition speciied. condition speciied.
Conditions are same as listed in irst 1able. Conditions are same as listed in irst 1able.
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Control Ilow Instructions Control Ilow Instructions
1he BL instruction. 1he BL instruction.
Stores the current return address in r1 ,Link register, Stores the current return address in r1 ,Link register,
and then shits the control to the subroutine as already and then shits the control to the subroutine as already
seen. seen.
I there is a call to a subroutine within another I there is a call to a subroutine within another
subroutine then the original address is pushed on to subroutine then the original address is pushed on to
the stack and current return address is stored in r1. the stack and current return address is stored in r1.
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Supervisor calls Supervisor calls
\heneer there is a need or input and an \heneer there is a need or input and an
output then it has to be done using superisor output then it has to be done using superisor
calls, which calls special subroutines using a calls, which calls special subroutines using a
special interrupt called S\I which stands or special interrupt called S\I which stands or
the Sotware Interrupt. the Sotware Interrupt.
Some useul S\I. Some useul S\I.
S\I S\I_writeC S\I S\I_writeC
S\I S\I_Lxit S\I S\I_Lxit
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ump 1ables ump 1ables
1he Idea o a jump table is that a programmer 1he Idea o a jump table is that a programmer
sometime wants to call one among a set o sometime wants to call one among a set o
subroutines depending on a alue computed. subroutines depending on a alue computed.
Lxample Lxample
BL jumptable BL jumptable
...... ......
Jumptable Jumptable
CM! r0,40 CM! r0,40
BLQ un1 BLQ un1
CM! r0,41 CM! r0,41
BLQ un2 BLQ un2
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Swap Swap
1he ARM instruction set has two swap 1he ARM instruction set has two swap
instructions. instructions.
Swap ,S\!, Swap ,S\!,
Swap Byte ,S\!B, Swap Byte ,S\!B,
Syntax : S\!cond}B} Rd, Rm, |Rn| Syntax : S\!cond}B} Rd, Rm, |Rn|
Lxample : Lxample :
S\! r12, r10, |r9| means S\! r12, r10, |r9| means
Load r12 rom address r9 and store r10 to address r9 Load r12 rom address r9 and store r10 to address r9
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Swap Swap
I we use the same instruction on a single I we use the same instruction on a single
register as shown then swap is achieed register as shown then swap is achieed
S\! r1, r1, |r2| S\! r1, r1, |r2|
Lxchanges alue in r1 and memory whose address is Lxchanges alue in r1 and memory whose address is
in r2 in r2
Byte exchange works on similar lines. Byte exchange works on similar lines.
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1he 1humb Instruction Set 1he 1humb Instruction Set
1he 16 bit instruction set 1he 16 bit instruction set
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1humb Instruction Set 1humb Instruction Set
It is a re It is a re--encoded subset o ARM instruction set. encoded subset o ARM instruction set.
Designed to increase the perormance o the Designed to increase the perormance o the
ARM implementations, which use a 16 bit or ARM implementations, which use a 16 bit or
narrower memory data bus and allow better narrower memory data bus and allow better
code density than ARM. code density than ARM.
1humb execution is lagged by 1 Bit ,bit|5|, in 1humb execution is lagged by 1 Bit ,bit|5|, in
the C!SR. the C!SR.
1~~0 ARM mode. 1~~0 ARM mode.
1~~1 1humb Mode. 1~~1 1humb Mode.
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A Glance at C!SR A Glance at C!SR
1he C!SR holds 1he C!SR holds
Copies o ALU status lags. Copies o ALU status lags.
Current processor state. Current processor state.
Interrupt disable lags Interrupt disable lags..
NN C C V V Unused Unused I I ll 11 Mode Mode
3J 30 29 28 27 8 7 6 S 4 0
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Lntering 1humb State Lntering 1humb State
1humb execution is entered by executing an 1humb execution is entered by executing an
ARM BX instruction ,Branch and Lxchange, ARM BX instruction ,Branch and Lxchange,
1his instruction branches to the address held in a 1his instruction branches to the address held in a
general purpose register and i the bit|0| o that general purpose register and i the bit|0| o that
register is a 1 1humb execution begins at the register is a 1 1humb execution begins at the
branch target address. branch target address.
I bit|0| is a 0 ARM execution continues rom a I bit|0| is a 0 ARM execution continues rom a
branch target address. branch target address.
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1humb Model 1humb Model
1humb instruction set gies ull access to the 1humb instruction set gies ull access to the
eight Lo` general purpose registers r0 to r and eight Lo` general purpose registers r0 to r and
makes use o the rest as ollows. makes use o the rest as ollows.
r13 is used as stack pointer. r13 is used as stack pointer.
r1 is the link register. r1 is the link register.
r15 is used as !C. r15 is used as !C.
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1humb ARM Differences 1humb ARM Differences
Most 1humb instructions are executed un Most 1humb instructions are executed un--
conditionally where as condition can be ixed to conditionally where as condition can be ixed to
all the arm instructions. all the arm instructions.
Many data processing instructions are in the two Many data processing instructions are in the two
address ormat, i.e. one o the source register address ormat, i.e. one o the source register
also acts as the destination register. also acts as the destination register.
Better code density than arm. Better code density than arm.
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Data !rocessing Instructions Data !rocessing Instructions
Data processing instructions on the Lo registers. Data processing instructions on the Lo registers.
i.e. registers r0 to r. i.e. registers r0 to r.
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1he Data !rocessing Instruction 1he Data !rocessing Instruction
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1he Compares 1he Compares
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Logical Instructions Logical Instructions
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Load Instructions Load Instructions
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Store Instructions. Store Instructions.
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Store Instructions Store Instructions