147351 (DIGITAL ELECTRONICS ) LAB MANUAL

SYLLABUS
1. Design and implementation of Adders and Subtractors using logic gates. 2. Design and implementation of code converters using logic gates (i) BCD to excess- code and voice versa (ii) Binar! to gra! and vice-versa . Design and implementation of " bit binar! Adder# subtractor and BCD adder using $C %"& ". Design and implementation of 2Bit 'agnitude Comparator using logic gates & Bit 'agnitude Comparator using $C %"&( 5. Design and implementation of 1) bit odd#even parit! c*ec+er #generator using $C%"1&,. ). Design and implementation of 'ultiplexer and De-multiplexer using logic gates and stud! of $C%"1(, and $C %"1(" %. Design and implementation of encoder and decoder using logic gates and stud! of $C%""( and $C%"1"% &. Construction and verification of " bit ripple counter and 'od-1, # 'od-12 -ipple counters .. Design and implementation of -bit s!nc*ronous up#do/n counter 1,. $mplementation of S$S01 S$201 2$S0 and 2$20 s*ift registers using 3lip- flops. 11. Design of expts 11)1&11, using 4erilog 5D6.

LIST OF EXPERIMENTS
1. Stud! of logic gates. 2. Design and implementation of adders and subtractors using logic gates. . Design and implementation of code converters using logic gates. ". Design and implementation of "-bit binar! adder#subtractor and BCD adder using $C %"& . (. Design and implementation of 2-bit magnitude comparator using logic gates1 &-bit magnitude comparator using $C %"&(. 6. Design and implementation of 1)-bit odd#even parit! c*ec+er# generator using $C %"1&,. %. Design and implementation of multiplexer and demultiplexer using logic gates and stud! of $C %"1(, and $C %"1(". &. Design and implementation of encoder and decoder using logic gates and stud! of $C %""( and $C %"1"%. .. Construction and verification of "-bit ripple counter and 'od1,#'od-12 ripple counter. 1,. 11. Design and implementation of -bit s!nc*ronous up#do/n counter. $mplementation of S$S01 S$201 2$S0 and 2$20 s*ift registers using flip-flops.

INDEX

INDEX

XP. NO

DATE

NAME OF THE EXPERIMENT

PAGE NO

MARKS

SIGNATURE

EXPT NO. : DATE :

STUDY OF LOGIC GATES

AIM: To study about logic gates and verify their truth tables. APPARATUS REQUIRED: '( !o. CO)*O!E!T /. !" 0 TE 5. OR 0 TE 6. !OT 0 TE 2. ! !" 0 TE 5 +7* 5. !OR 0 TE 6. #$OR 0 TE 1. ! !" 0 TE 6 +7* 4. +C TR +!ER 8+T 9. * TC: COR" '*EC+,+C T+O! -T. +C 1234 / +C 1265 / +C 1232 / +C 1233 / +C 1235 / +C 1246 / +C 12/3 / $ / $ /2

T EORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, !" and !OT are basic gates. ! !", !OR and #$OR are kno%n as universal gates. &asic gates form these gates.

AND GATE: The !" gate performs a logical multiplication commonly kno%n as !" function. The output is high %hen both the inputs are high. The output is lo% level %hen any one of the inputs is lo%.

OR GATE: The OR gate performs a logical addition commonly kno%n as OR function. The output is high %hen any one of the inputs is high. The output is lo% level %hen both the inputs are lo%. NOT GATE: The !OT gate is called an inverter. The output is high %hen the input is lo%. The output is lo% %hen the input is high. NAND GATE: The ! !" gate is a contraction of level %hen both inputs are high. NOR GATE: The !OR gate is a contraction of OR$!OT. The output is high %hen both inputs are lo%. The output is lo% %hen one or both inputs are high. X!OR GATE: !"$!OT. The output is high

%hen both inputs are lo% and any one of the input is lo% .The output is lo%

"

The output is high %hen any one of the inputs is high. The output is lo% %hen both the inputs are lo% and both the inputs are high. PROCEDURE: ;i< Connections are given as per circuit diagram. ;ii< ;iii<
AND GATE: SYMBOL: PIN DIAGRAM:

(ogical inputs are given as per circuit diagram. Observe the output and verify the truth table.

OR GATE:

NOT GATE: SYMBOL: PIN DIAGRAM:

X!OR GATE :

SYMBOL :

PIN DIAGRAM :

2!INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

3!INPUT NAND GATE :

NOR GATE:

1%

RESULT:

EXPT NO. :
DATE :

DESIGN OF ADDER AND SUBTRACTOR

AIM: To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates. APPARATUS REQUIRED: 'l.!o. /. 5. 6. 2. 6. 2. CO)*O!E!T !" 0 TE #$OR 0 TE !OT 0 TE OR 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 1234 / +C 1246 / +C 1232 / +C 1265 / $ / $ 56

11

T EORY: ALF ADDER: half adder has t%o inputs for the t%o bits to be added and t%o outputs one from the sum = '> and other from the carry = c> into the higher adder position. !" gate. bove circuit is called as a carry signal from the addition of the less significant bits sum from the #$OR 0ate the carry out from the

FULL ADDER: full adder is a combinational circuit that forms the arithmetic sum of input? it consists of three inputs and t%o outputs. full adder is useful to add three bits at a time but a half adder cannot do so. +n full adder sum output %ill be taken from #$OR 0ate, carry output %ill be taken from OR 0ate. ALF SUBTRACTOR: The half subtractor is constructed using #$OR and !" 0ate. The

half subtractor has t%o input and t%o outputs. The outputs are difference and borro%. The difference can be applied using #$OR 0ate, borro% output can be implemented using an !" 0ate and an inverter. FULL SUBTRACTOR:

12

The full subtractor is a combination of #$OR,

!", OR, !OT 0ates.

+n a full subtractor the logic circuit should have three inputs and t%o outputs. The t%o half subtractor put together gives a full subtractor .The first half subtractor %ill be C and subtractor. The e@pression OR. &. The output %ill be difference output of full & assembles the borro% output of the half

subtractor and the second term is the inverted difference output of first #$

LOGIC DIAGRAM: ALF ADDER

TRUT

TABLE: A % % 1 1 B % 1 % 1 CARRY % % % 1 SUM % 1 1 %

13

&!M'( )*+ SUM:

&!M'( )*+ CARRY:

SUM , A-B . AB-

CARRY , AB

LOGIC DIAGRAM: FULL ADDER FULL ADDER USING T/O

ALF ADDER

TRUT

TABLE: A % % % B % % 1 C % 1 % CARRY % % % SUM % 1 1

14

% 1 1 1 1

1 % % 1 1

1 % 1 % 1

1 % 1 1 1

% 1 % % 1

&!M'( )*+ SUM:

SUM , A-B-C . A-BC- . ABC- . ABC &!M'( )*+ CARRY:

CARRY , AB . BC . AC LOGIC DIAGRAM: ALF SUBTRACTOR

15

TRUT

TABLE: A % % 1 1 B % 1 % 1 BORRO/ DIFFERENCE % 1 % % % 1 1 %

&!M'( )*+ DIFFERENCE:

DIFFERENCE , A-B . AB&!M'( )*+ BORRO/:

BORRO/ , A-B

1"

LOGIC DIAGRAM: FULL SUBTRACTOR

FULL SUBTRACTOR USING T/O

ALF SUBTRACTOR:

TRUT

TABLE: A % % %

B % % 1

C % 1 %

BORRO/ DIFFERENCE % 1 1 % 1 1

17

% 1 1 1 1

1 % % 1 1

1 % 1 % 1

1 % % % 1

% 1 % % 1

&!M'( )*+ D0))1+1231:

D0))1+1231 , A-B-C . A-BC- . AB-C- . ABC

&!M'( )*+ B*++*4:

B*++*4 , A-B . BC . A-C PROCEEDURE: ;i< Connections are given as per circuit diagram. ;ii< (ogical inputs are given as per circuit diagram.

1#

;iii<

Observe the output and verify the truth table.

RESULT:

EXPT NO. :
DATE :

DESIGN AND IMPLEMENTATION OF CODE CON5ERTOR AIM: To design and implement 2$bit ;i< &inary to gray code converter ;ii< 0ray to binary code converter ;iii< &C" to e@cess$6 code converter ;iv< E@cess$6 to &C" code converter APPARATUS REQUIRED: 'l.!o. CO)*O!E!T /. #$OR 0 TE 5. !" 0 TE 6. OR 0 TE

'*EC+,+C T+O! -T.. +C 1246 / +C 1234 / +C 1265 /

1$

2. 5. 6.

!OT 0 TE +C TR +!ER 8+T * TC: COR"'

+C 1232 $ $

/ / 65

T EORY: The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. conversion circuit must be inserted bet%een the t%o systems if each uses different codes for same information. Thus, code converter is a circuit that makes the t%o systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. 'ince each code uses four bits to represent a decimal digit. There are four inputs and four outputs. 0ray code is a non$%eighted code. The input variable are designated as &6, &5, &/, &3 and the output variables are designated as C6, C5, C/, Co. from the truth table, combinational circuit is designed. The &oolean functions are obtained from 8$)ap for each output variable. code converter is a circuit that makes the t%o systems compatible even though each uses a different binary code. To convert from binary code to E@cess$6 code, the input lines must supply the bit combination of elements as specified by code and the output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function of the four input variables. t%o$level logic diagram may be obtained directly from the &oolean e@pressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. !o% the OR gate %hose output is CA" has been used to implement partially each of three outputs.
2%

LOGIC DIAGRAM: BINARY TO GRAY CODE CON5ERTOR

&!M'( )*+ G3:

G3 , B3 &!M'( )*+ G2:

21

&!M'( )*+ G1:

&!M'( )*+ G%:

22

TRUT TABLE: 6 B02'+7 02(89 B3 % % % % % % % % 1 1 1 1 1 1 1 1 B2 % % % % 1 1 1 1 % % % % 1 1 1 1 B1 % % 1 1 % % 1 1 % % 1 1 % % 1 1 B% % 1 % 1 % 1 % 1 % 1 % 1 % 1 % 1

6 G3 % % % % % % % % 1 1 1 1 1 1 1 1

G+'7 3*:1 *89(89 G2 % % % % 1 1 1 1 1 1 1 1 % % % % G1 % % 1 1 1 1 % % % % 1 1 1 1 % % G% % 1 1 % % 1 1 % % 1 1 % % 1 1 %

LOGIC DIAGRAM: GRAY CODE TO BINARY CON5ERTOR

23

&!M'( )*+ B3:

B3 , G3 &!M'( )*+ B2:

24

&!M'( )*+ B1:

&!M'( )*+ B%:

25

TRUT 6 G3 % % % % % % % % 1 1 1 1 1 1 1 1

TABLE: 6 G1 % % 1 1 1 1 % % % % 1 1 1 1 % % G% % 1 1 % % 1 1 % % 1 1 % % 1 1 % B3 % % % % % % % % 1 1 1 1 1 1 1 1 B02'+7 C*:1 B2 % % % % 1 1 1 1 % % % % 1 1 1 1 B1 % % 1 1 % % 1 1 % % 1 1 % % 1 1 B% % 1 % 1 % 1 % 1 % 1 % 1 % 1 % 1 6

G+'7 C*:1 G2 % % % % 1 1 1 1 1 1 1 1 % % % %

2"

LOGIC DIAGRAM: BCD TO EXCESS!3 CON5ERTOR

&!M'( )*+ E3:

E3 , B3 . B2 (B% . B1)

27

&!M'( )*+ E2:

&!M'( )*+ E1:

2#

&!M'( )*+ E%:

TRUT TABLE: 6 BCD 02(89 B3 B2 % % % % % % % % 1 1 1 1 1 1 1 1 % % % % 1 1 1 1 % % % % 1 1 1 1

6 B1 % % 1 1 % % 1 1 % % 1 1 % % 1 1 B% % 1 % 1 % 1 % 1 % 1 % 1 % 1 % 1

E;31<< = 3 *89(89 G3 G2 G1 % % % % % 1 1 1 1 1 ; ; ; ; ; ; % 1 1 1 1 % % % % 1 ; ; ; ; ; ; 1 % % 1 1 % % 1 1 % ; ; ; ; ; ;

6 G% 1 % 1 % 1 % 1 % 1 % ; ; ; ; ; ;

2$

LOGIC DIAGRAM: EXCESS!3 TO BCD CON5ERTOR

3%

&!M'( )*+ A:

A , X1 X2 . X3 X4 X1 &!M'( )*+ B:

31

&!M'( )*+ C:

&!M'( )*+ D:
32

TRUT 6 B3 % % % % % 1 1 1 1 1

TABLE: 6 B% 1 % 1 % 1 % 1 % 1 % BCD O89(89 G3 % % % % % % % % 1 1 G2 % % % % 1 1 1 1 % % G1 % % 1 1 % % 1 1 % % G% % 1 % 1 % 1 % 1 % 1 6

E;31<< = 3 I2(89 B2 % 1 1 1 1 % % % % 1 B1 1 % % 1 1 % % 1 1 %

PROCEDURE:

33

;i< ;ii< ;iii<

Connections %ere given as per circuit diagram. (ogical inputs %ere given as per truth table Observe the logical output and verify %ith the truth tables.

RESULT:

EXPT NO. : DATE :

DESIGN OF 4!BIT ADDER AND SUBTRACTOR

34

AIM: To design and implement 2$bit adder and subtractor using +C 1246. APPARATUS REQUIRED: 'l.!o. CO)*O!E!T '*EC+,+C T+O! -T.. /. +C +C 1246 / 5. E#$OR 0 TE +C 1246 / 6. !OT 0 TE +C 1232 / 6. +C TR +!ER 8+T $ / 2. * TC: COR"' $ 23 T EORY: 4 BIT BINARY ADDER: binary adder is a digital circuit that produces the arithmetic sum of t%o binary numbers. +t can be constructed %ith full adders connected in cascade, %ith the output carry from each full adder connected to the input carry of ne@t full adder in chain. The augends bits of = > and the addend bits of =&> are designated by subscript numbers from right to left, %ith subscript 3 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C 3 and it ripples through the full adder to the output carry C2. 4 BIT BINARY SUBTRACTOR: The circuit for subtracting $& consists of an adder %ith inverters, placed bet%een each data input =&> and the corresponding input of full adder. The input carry C3 must be eBual to / %hen performing subtraction. 4 BIT BINARY ADDER>SUBTRACTOR:

35

The addition and subtraction operation can be combined into one circuit %ith one common binary adder. The mode input ) controls the operation. Chen )D3, the circuit is adder circuit. Chen )D/, it becomes subtractor. 4 BIT BCD ADDER: Consider the arithmetic addition of t%o decimal digits in &C", together %ith an input carry from a previous stage. 'ince each input digit does not e@ceed 9, the output sum cannot be greater than /9, the / in the sum being an input carry. The output of t%o decimal digits must be represented in &C" and should appear in the form listed in the columns. &C" adder that adds 5 &C" digits and produce a sum digit in &C". The 5 decimal digits, together %ith the input carry, are first added in the top 2 bit adder to produce the binary sum. PIN DIAGRAM FOR IC 74#3:

3"

LOGIC DIAGRAM: 4!BIT BINARY ADDER

37

LOGIC DIAGRAM: 4!BIT BINARY SUBTRACTOR

3#

LOGIC DIAGRAM: 4!BIT BINARY ADDER>SUBTRACTOR

3$

TRUT

TABLE:
I2(89 D'9' B C % 1 % % 1 1 1 A::090*2 S4 S3 S2 S1 1 % 1 1 % 1 % % % % % % % 1 1 % 1 % 1 1 1 % % % % % % 1 B 1 1 % % % % % S8?9+'390*2 D4 D3 D2 D1 % % 1 1 1 1 1 1 % % % 1 1 1 1 % 1 1 1 1 % % % % % 1 1 1

I2(89 D'9' A

A4 A3 A2 A1 B4 B3 B2 B1 1 1 % % 1 1 1 % % % % % 1 % % % 1 % 1 1 1 % % % 1 % % % % 1 1 % 1 1 1 % % % 1 % 1 1 1 % % 1 1 1 % % % % 1 1 1 1

4%

LOGIC DIAGRAM: BCD ADDER

& MAP

Y , S4 (S3 . S2)

41

TRUT

TABLE:
S4 % % % % % % % % 1 1 1 1 1 1 1 1 BCD SUM S3 S2 % % % % % 1 % 1 1 % 1 % 1 1 1 1 % % % % % 1 % 1 1 % 1 % 1 1 1 1 S1 % 1 % 1 % 1 % 1 % 1 % 1 % 1 % 1 CARRY C % % % % % % % % % % 1 1 1 1 1 1

PROCEDURE: ;i< ;ii< ;iii< RESULT: Connections %ere given as per circuit diagram. (ogical inputs %ere given as per truth table Observe the logical output and verify %ith the truth tables.

42

EXPT NO. : DATE : DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR AIM: To design and implement ;i< ;ii< 5 E bit magnitude comparator using basic gates. 4 E bit magnitude comparator using +C 1245.

APPARATUS REQUIRED: 'l.!o. /. 5. 6. 2. 5. 6. 1. CO)*O!E!T !" 0 TE #$OR 0 TE OR 0 TE !OT 0 TE 2$&+T ) 0!+TF"E CO)* R TOR +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! +C 1234 +C 1246 +C 1265 +C 1232 +C 1245 $ $ -T.. 5 / / / 5 / 63

T EORY: The comparison of t%o numbers is an operator that determine one number is greater than, less than ;or< eBual to the other number. magnitude comparator is a combinational circuit that compares t%o numbers and & and determine their relative magnitude. The outcome of the comparator is specified by three binary variables that indicate %hether D& ;or< H&.
43

G&,

& D &6 &5 &/ &3 The eBuality of the t%o numbers and & is displayed in a combinational circuit designated by the symbol ; D&<. This indicates that of & is 3. Ce have H&, the seBuential comparison can be e@panded as G& D 6&6/ A #6 H& D
/ 6

greater than &, then inspect the relative magnitude of is 3 and

pairs of significant digits starting from most significant position.

5 5

&5/ A #6#5 &5 A #6#5

&// A #6#5#/ &/ A #6#5#/

3 3

&3/
/

&6 A #6

/ /

&3

The same circuit can be used to compare the relative magnitude of t%o &C" digits. Chere, D&D; D & is e@panded as, A &6< ; @6 A &5< ; @5 A &/< ; @/ A &3< @3

44

LOGIC DIAGRAM: 2 BIT MAGNITUDE COMPARATOR

45

& MAP

4"

TRUT

TABLE

47

A1 A% B1 B% % % % % % % % 1 % % 1 % % % 1 1 % 1 % % % 1 % 1 % 1 1 % % 1 1 1 1 % % % 1 % % 1 1 % 1 % 1 % 1 1 1 1 % % 1 1 % 1 1 1 1 % 1 1 1 1

A@B % % % % 1 % % % 1 1 % % 1 1 1 %

A,B 1 % % % % 1 % % % % 1 % % % % 1

AAB % 1 1 1 % % 1 1 % % % 1 % % % %

PIN DIAGRAM FOR IC 74#5:

4#

LOGIC DIAGRAM: # BIT MAGNITUDE COMPARATOR

4$

TRUT

TABLE:

A %%%% %%%1 %%%% %%%% %%%1 %%%% %%%% %%%% %%%1

B %%%% %%%% %%%1

A@B % 1 %

A,B 1 % %

AAB % % 1

PROCEDURE: ;i< ;ii< Connections are given as per circuit diagram. (ogical inputs are given as per circuit diagram.
5%

;iii<

Observe the output and verify the truth table.

RESULT:

EXPT NO. : DATE : 1" BIT ODD>E5EN PARITY C EC&ER >GENERATOR AIM: To design and implement /6 bit odd7even parity checker generator using +C 12/43.

51

APPARATUS REQUIRED: 'l.!o. /. /. 5. 6. CO)*O!E!T !OT 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 1232 / +C 12/43 5 $ / $ 63

T EORY: parity bit is used for detecting errors during transmission of binary information. parity bit is an e@tra bit included %ith a binary message to n error is make the number is either even or odd. The message including the parity bit is transmitted and then checked at the receiver ends for errors. detected if the checked parity bit doesn>t correspond to the one transmitted. The circuit that generates the parity bit in the transmitter is called a =parity generator> and the circuit that checks the parity in the receiver is called a =parity checker>. +n even parity, the added parity bit %ill make the total number is even amount. +n odd parity, the added parity bit %ill make the total number is odd amount. The parity checker circuit checks for possible errors in the transmission. +f the information is passed in even parity, then the bits reBuired must have an even number of />s. one bit has changed in value during transmission. PIN DIAGRAM FOR IC 741#%: n error occur during transmission, if the received bits have an odd number of />s indicating that

52

FUNCTION TABLE: INPUTS N8B?1+ *) 0CD D'9' I2(89< (I% = I7) E5EN ODD E5EN ODD X X LOGIC DIAGRAM:

PE 1 1 % % 1 %

PO % % 1 1 1 %

OUTPUTS EE IO 1 % % 1 % 1 % 1 1 % % 1

1" BIT ODD>E5EN PARITY C EC&ER

53

TRUT

TABLE:

I7 I" I5 I4 I3 I2 I1 I% I7-I"-I5-I4-I3-I2-11- I%- A390F1 % % % % % % % 1 % % % % % % % % 1 % % % % % 1 1 % % % % % % 1 1 % % % % % % % 1 1 % % % % % % 1 1 % 1

EE 1 1 %

EO % % 1

LOGIC DIAGRAM: 1" BIT ODD>E5EN PARITY GENERATOR

54

TRUT

TABLE: I7 I" I5 I4 I3 I2 I1 I% A390F1 1 1 % % % % % % 1 1 1 % % % % % % % % 1 % % % % % % % EE 1 % 1 EO % 1 %

I7 I" I5 I4 I3 I2 I1 I% 1 1 % % % % % % 1 1 % % % % % % 1 1 % % % % % %

PROCEDURE: ;i< ;ii< Connections are given as per circuit diagram. (ogical inputs are given as per circuit diagram.
55

;iii<

Observe the output and verify the truth table.

RESULT:

EXPT NO. : DATE :

DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER AIM:

5"

To design and implement multiple@er and demultiple@er using logic gates and study of +C 12/53 and +C 12/52. APPARATUS REQUIRED: 'l.!o. /. 5. 6. 5. 6. CO)*O!E!T 6 +7* !" 0 TE OR 0 TE !OT 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 12// 5 +C 1265 / +C 1232 / $ / $ 65

T EORY: MULTIPLEXER: )ultiple@er means transmitting a large number of information units over a smaller number of channels or lines. digital multiple@er is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. !ormally there are 5n input line and n selection lines %hose bit combination determine %hich input is selected. DEMULTIPLEXER: The function of "emultiple@er is in contrast to multiple@er function. +t takes information from one line and distributes it to a given number of output lines. ,or this reason, the demultiple@er is also kno%n as a data distributor. "ecoder can also be used as demultiple@er. +n the /J 2 demultiple@er circuit, the data input line goes to all of the !" gates. The data select lines enable only one gate at a time and the data on the data input line %ill pass through the selected gate to the associated data output line.

57

BLOC& DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:

S1 % % 1 1

S% % 1 % 1

INPUTS Y D% G D% S1- S%D1 G D1 S1- S% D2 G D2 S1 S%D3 G D3 S1 S%

Y , D% S1- S%- . D1 S1- S% . D2 S1 S%- . D3 S1 S% CIRCUIT DIAGRAM FOR MULTIPLEXER:

5#

TRUT

TABLE: S1 % % 1 1 S% % 1 % 1 Y , OUTPUT D% D1 D2 D3

BLOC& DIAGRAM FOR 1:4 DEMULTIPLEXER:

5$

FUNCTION TABLE:

S1 % % 1 1

S% % 1 % 1

INPUT X G D% , X S1- S%X G D1 , X S1- S% X G D2 , X S1 S%X G D3 , X S1 S%

Y , X S1- S%- . X S1- S% . X S1 S%- . X S1 S%

LOGIC DIAGRAM FOR DEMULTIPLEXER:

"%

TRUT S1

TABLE: INPUT S% I>P D% OUTPUT D1 D2 D3

"1

% % % % 1 1 1 1

% % 1 1 % % 1 1

% 1 % 1 % 1 % 1

% 1 % % % % % %

% % % 1 % % % %

% % % % % 1 % %

% % % % % % % 1

PIN DIAGRAM FOR IC 7415%:

PIN DIAGRAM FOR IC 74154:

"2

PROCEDURE: ;i< Connections are given as per circuit diagram. ;ii< ;iii< RESULT: (ogical inputs are given as per circuit diagram. Observe the output and verify the truth table.

"3

EXPT NO. : DATE :

DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER

AIM: To design and implement encoder and decoder using logic gates and study of +C 1225 and +C 12/21. APPARATUS REQUIRED: 'l.!o. /. 5. 6. 5. 6. CO)*O!E!T 6 +7* ! !" 0 TE OR 0 TE !OT 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 12/3 5 +C 1265 6 +C 1232 / $ / $ 51

T EORY: ENCODER: n encoder is a digital circuit that perform inverse operation of a decoder. n encoder has 5n input lines and n output lines. +n encoder the output lines generates the binary code corresponding to the input value. +n octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. +n encoder it is assumed that only one input has a value of one at any given time other%ise the circuit is meaningless. +t has an ambiguila that %hen all inputs are Kero the outputs are Kero. The Kero outputs can also be generated %hen "3 D /. DECODER:
"4

decoder is a multiple input multiple output logic circuit %hich converts coded input into coded output %here input and output codes are different. The input code generally has fe%er bits than the output code. Each input code %ord produces a different output code %ord i.e there is one to one mapping can be e@pressed in truth table. +n the block diagram of decoder circuit the encoded information is present as n input producing 5n possible outputs. 5n output values are from 3 through out 5n E /.

PIN DIAGRAM FOR IC 7445: BCD TO DECIMAL DECODER:

PIN DIAGRAM FOR IC 74147:

"5

LOGIC DIAGRAM FOR ENCODER:

""

TRUT Y1 1 % % % % % %

TABLE: Y2 % 1 % % % % % Y3 % % 1 % % % % INPUT Y4 Y5 % % % % % % 1 % % 1 % % % % Y" % % % % % 1 % Y7 % % % % % % 1 A % % % 1 1 1 1 OUTPUT B % 1 1 % % 1 1 C 1 % 1 % 1 % 1

LOGIC DIAGRAM FOR DECODER:

"7

TRUT

TABLE: INPUT A % % % 1 1 OUTPUT D1 D2 1 1 1 1 % 1 1 % 1 1

E 1 % % % %

B % % 1 % 1

D% 1 % 1 1 1

D3 1 1 1 1 %

PROCEDURE: ;i< Connections are given as per circuit diagram.

"#

;ii< ;iii<

(ogical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

EXPT NO. : DATE : CONSTRUCTION AND 5ERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 1%>MOD 12 RIPPLE COUNTER AIM:
"$

To design and verify 2 bit ripple counter mod /37 mod /5 ripple counter. APPARATUS REQUIRED: 'l.!o. /. 5. 6. 2. CO)*O!E!T L8 ,(+* ,(O* ! !" 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 1216 5 +C 1233 / $ / $ 63

T EORY: counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. specified seBuence of states appears as counter output. This is the main difference bet%een a register and a counter. There are t%o types of counter, synchronous and asynchronous. +n synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by e@ternal pulse and then each successive flip flop is clocked by - or - output of previous stage. soon the clock of second stage is triggered by output of first stage. &ecause of inherent propagation delay time all flip flops are not activated at same time %hich results in asynchronous operation. PIN DIAGRAM FOR IC 747":

7%

LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:

71

TRUT

TABLE: CL& % 1 2 3 4 5 " 7 # $ 1% QA % 1 % 1 % 1 % 1 % 1 % QB % % 1 1 % % 1 1 % % 1 QC % % % % 1 1 1 1 % % % QD % % % % % % % % 1 1 1

72

11 12 13 14 15

1 % 1 % 1

1 % % 1 1

% 1 1 1 1

1 1 1 1 1

LOGIC DIAGRAM FOR MOD ! 1% RIPPLE COUNTER:

TRUT

TABLE: CL& % 1 2 3 QA % 1 % 1 QB % % 1 1 QC % % % % QD % % % %
73

4 5 " 7 # $ 1%

% 1 % 1 % 1 %

% % 1 1 % % %

1 1 1 1 % % %

% % % % 1 1 %

LOGIC DIAGRAM FOR MOD ! 12 RIPPLE COUNTER:

TRUT

TABLE: CL& % 1 2 3 4 5 " 7 # $ 1% 11 12 QA % 1 % 1 % 1 % 1 % 1 % 1 % QB % % 1 1 % % 1 1 % % 1 1 % QC % % % % 1 1 1 1 % % % % % QD % % % % % % % % 1 1 1 1 %

74

PROCEDURE: ;i< ;ii< ;iii< Connections are given as per circuit diagram. (ogical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

75

EXPT NO. : DATE : DESIGN AND IMPLEMENTATION OF 3 BIT SYNC RONOUS UP>DO/N COUNTER AIM: To design and implement 6 bit synchronous up7do%n counter. APPARATUS REQUIRED: 'l.!o. /. 5. 6. 2. 5. 6. 1. CO)*O!E!T L8 ,(+* ,(O* 6 +7* !" 0 TE OR 0 TE #OR 0 TE !OT 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 1216 5 +C 12// / +C 1265 / +C 1246 / +C 1232 / $ / $ 65

T EORY: counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. n up7do%n counter is one that is capable of progressing in increasing order or decreasing order through a certain seBuence. n up7do%n counter is also called bidirectional counter. Fsually up7do%n operation of the counter is controlled by up7do%n signal. Chen this signal is high counter goes through up seBuence and %hen up7do%n signal is lo% counter follo%s reverse seBuence. & MAP
7"

STATE DIAGRAM:

77

C ARACTERISTICS TABLE: Q % % 1 1 Q9.1 % 1 % 1 H % 1 X X & X X 1 %

LOGIC DIAGRAM:

TRUT

TABLE:

7#

I2(89 P+1<129 S9'91 U(>D*42 QA QB QC % % % % % 1 1 1 % 1 1 % % 1 % 1 % 1 % % % % 1 1 % % 1 % % % % 1 1 % % % 1 % % 1 1 % 1 % 1 % 1 1 1 1 % % 1 1 % 1 1 1 1 % 1 1 1 1

N1;9 S9'91 QA.1 Q B.1 QC.1 1 1 1 1 1 % 1 % 1 1 % % % 1 1 % 1 % % % 1 % % % % % 1 % 1 % % 1 1 1 % % 1 % 1 1 1 % 1 1 1 % % %

A HA 1 X X X X % % % % % % 1 X X X X &A X % % % 1 X X X X X X X % % % 1 HB 1 X X % 1 X X % % 1 X X % 1 X X

B &B X % 1 X X % 1 X X X % 1 X X % 1 HC 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X

C &C X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1

PROCEDURE: ;i< Connections are given as per circuit diagram. ;ii< ;iii< RESULT: (ogical inputs are given as per circuit diagram. Observe the output and verify the truth table.

EXPT NO. : DATE : DESIGN AND IMPLEMENTATION OF S IFT REGISTER AIM:

7$

To design and implement ;i< 'erial in serial out ;ii< 'erial in parallel out ;iii< *arallel in serial out ;iv< *arallel in parallel out APPARATUS REQUIRED: 'l.!o. /. 5. 6. 2. CO)*O!E!T " ,(+* ,(O* OR 0 TE +C TR +!ER 8+T * TC: COR"' '*EC+,+C T+O! -T.. +C 1212 5 +C 1265 / $ / $ 65

T EORY: register is capable of shifting its binary information in one or both directions is kno%n as shift register. The logical configuration of shift register consist of a "$,lip flop cascaded %ith output of one flip flop connected to input of ne@t flip flop. ll flip flops receive common clock The simplest pulses %hich causes the shift in the output of the flip flop.

possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of ne@t flip flop of the register. Each clock pulse shifts the content of register one bit position to right. PIN DIAGRAM:

#%

LOGIC DIAGRAM: SERIAL IN SERIAL OUT:

TRUT

TABLE:

#1

S1+0'I 02 CL& 1 2 3 4 5 " 7 1 % % 1 X X X

S1+0'I *89

% % % 1 % % 1

LOGIC DIAGRAM: SERIAL IN PARALLEL OUT:

TRUT

TABLE: QA 1 % % 1 OUTPUT QB QC % 1 % % % % 1 % QD % % 1 1

CL& DATA 1 1 2 % 3 % 4 1 LOGIC DIAGRAM:

PARALLEL IN SERIAL OUT:

#2

TRUT

TABLE: CL& % 1 2 3 Q3 1 % % % Q2 % % % % Q1 % % % % Q% 1 % % % O>P 1 % % 1

LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT:

TRUT CL&

TABLE: DA DATA INPUT DB DC DD QA OUTPUT QB QC QD

#3

1 2

1 1

% %

% 1

1 %

1 1

% %

% 1

1 %

PROCEDURE: ;i< ;ii< ;iii< Connections are given as per circuit diagram. (ogical inputs are given as per circuit diagram. Observe the output and verify the truth table.

RESULT:

PREPARATORY EXERCISE 1. Study of lo !" #t$%

#4

&. D$%! ' #'d !()l$($'t#t!o' of #dd$*% #'d %u+t*#"to*% u%!' lo !" #t$%

#5

,. D$%! ' #'d !()l$($'t#t!o' of "od$ "o'-$*t$*% u%!' lo !" #t$%

#"

.. D$%! ' #'d !()l$($'t#t!o' of ./+!t +!'#*y #dd$*0%u+t*#"to* #'d BCD #dd$* u%!' IC 1.2,

#7

3. D$%! ' #'d !()l$($'t#t!o' of &/+!t (# '!tud$ "o()#*#to* u%!' lo !" u%!' IC 1.23 #t$%4 2/+!t (# '!tud$ "o()#*#to*

##

5. D$%! ' #'d !()l$($'t#t!o' of 15/+!t odd0$-$' )#*!ty "6$"7$* $'$*#to* u%!' IC 1.128

#$

1. D$%! ' #'d !()l$($'t#t!o' of (ult!)l$9$* #'d d$(ult!)l$9$* u%!' IC 1.13. lo !" #t$% #'d %tudy of IC 1.138 #'d

$%

2. D$%! ' #'d !()l$($'t#t!o' of $'"od$* #'d d$"od$* u%!' lo !" #t$% #'d %tudy of IC 1..3 #'d IC 1.1.1

$1

:. Co'%t*u"t!o' #'d -$*!f!"#t!o' of ./+!t *!))l$ "ou't$* #'d Mod/180Mod/1& *!))l$ "ou't$*

$2

18. D$%! ' #'d !()l$($'t#t!o' of ,/+!t %y'"6*o'ou% u)0do;' "ou't$*

$3

11. I()l$($'t#t!o' of SISO4 SIPO4 PISO #'d PIPO %6!ft *$ !%t$*% u%!' fl!)/flo)%

$4

$5