Core I7 900 Ee and Desktop Processor Series 32nm Datasheet Vol 1

Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series
on 32-nm Process
Datasheet, Volume 1
June 2011
Document # 323252-003
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Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/processor_number for details.
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technologyenabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For more information including details on which processors support HT Technology, see http://www.intel.com/products/ht/hyperthreading_more.htm Intel 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See www.intel.com/info/em64t for more information including details on which processors support Intel 64 or consult with your system vendor for more information. Intel Virtualization Technology requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software, enabled for it. Functionality, performance or other benefit will vary depending on hardware and software configurations. Intel Virtualization Technology-enabled VMM applications are currently in development. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. Enhanced Intel SpeedStep Technology. See the Processor Spec Finder or contact your Intel representative for more information. Intel Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost Technology performance varies depending on hardware, software and overall system configuration. Check with your PC manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see www.intel.com. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Intel SpeedStep, Intel Core, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright 20102011 Intel Corporation.
Datasheet, Volume 1
Contents
1 Introduction .............................................................................................................. 9 1.1 Terminology ..................................................................................................... 10 1.2 References ....................................................................................................... 11 Electrical Specifications ........................................................................................... 13 2.1 Intel QuickPath Interconnect (Intel QPI) Differential Signaling............................. 13 2.2 Power and Ground Lands.................................................................................... 13 2.3 Decoupling Guidelines ........................................................................................ 13 2.3.1 VCC, VTTA, VTTD, VDDQ Decoupling ............................................................. 14 2.4 Processor Clocking (BCLK_DP, BCLK_DN) ............................................................. 14 2.4.1 PLL Power Supply ................................................................................... 14 2.5 Voltage Identification (VID) ................................................................................ 15 2.6 Reserved or Unused Signals................................................................................ 18 2.7 Signal Groups ................................................................................................... 19 2.8 Test Access Port (TAP) Connection....................................................................... 20 2.9 Platform Environmental Control Interface (PECI) DC Specifications........................... 21 2.9.1 DC Characteristics .................................................................................. 21 2.9.2 Input Device Hysteresis .......................................................................... 22 2.10 Absolute Maximum and Minimum Ratings ............................................................. 22 2.11 Processor DC Specifications ................................................................................ 23 2.11.1 DC Voltage and Current Specification ........................................................ 24 2.11.2 VCC Overshoot Specification ..................................................................... 31 2.11.3 Die Voltage Validation ............................................................................. 31 2.12 Intel QuickPath Interconnect (Intel QPI) Specifications....................................... 32 Package Mechanical Specifications .......................................................................... 35 3.1 Package Mechanical Drawing............................................................................... 35 3.2 Processor Component Keep-Out Zones ................................................................. 38 3.3 Package Loading Specifications ........................................................................... 38 3.4 Package Handling Guidelines............................................................................... 38 3.5 Package Insertion Specifications.......................................................................... 38 3.6 Processor Mass Specification ............................................................................... 39 3.7 Processor Materials............................................................................................ 39 3.8 Processor Markings............................................................................................ 39 3.9 Processor Land Coordinates ................................................................................ 40 Land Listing ............................................................................................................. 41 Signal Descriptions .................................................................................................. 71 Thermal Specifications ............................................................................................ 75 6.1 Package Thermal Specifications ........................................................................... 75 6.1.1 Thermal Specifications ............................................................................ 75 6.1.1.1 Specification for Operation Where Digital Thermal Sensor Exceeds TCONTROL ..................................................................... 79 6.1.2 Thermal Metrology ................................................................................. 80 6.2 Processor Thermal Features ................................................................................ 81 6.2.1 Processor Temperature ........................................................................... 81 6.2.2 Adaptive Thermal Monitor........................................................................ 81 6.2.2.1 Frequency/VID Control .............................................................. 82 6.2.2.2 Clock Modulation ...................................................................... 83 6.2.2.3 Immediate Transiton to combined TM1 and TM2 ........................... 83 6.2.2.4 Critical Temperature Flag ........................................................... 83 6.2.2.5 PROCHOT# Signal..................................................................... 83 6.2.3 THERMTRIP# Signal ............................................................................... 84
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6.3
6.4 7
Platform Environment Control Interface (PECI) ......................................................84 6.3.1 Introduction ...........................................................................................84 6.3.1.1 Fan Speed Control with Digital Thermal Sensor .............................85 6.3.1.2 Processor Thermal Data Sample Rate and Filtering.........................85 6.3.2 PECI Specifications .................................................................................86 6.3.2.1 PECI Device Address..................................................................86 6.3.2.2 PECI Command Support .............................................................86 6.3.2.3 PECI Fault Handling Requirements ...............................................86 6.3.2.4 PECI GetTemp0() Error Code Support ..........................................86 Storage Conditions Specifications.........................................................................87
Features ..................................................................................................................89 7.1 Power-On Configuration (POC).............................................................................89 7.2 Clock Control and Low Power States .....................................................................89 7.2.1 Thread and Core Power State Descriptions .................................................90 7.2.1.1 C0 State ..................................................................................90 7.2.1.2 C1/C1E State............................................................................90 7.2.1.3 C3 State ..................................................................................91 7.2.1.4 C6 State ..................................................................................91 7.2.2 Package Power State Descriptions .............................................................91 7.2.2.1 Package C0 State ......................................................................91 7.2.2.2 Package C1/C1E State ...............................................................91 7.2.2.3 Package C3 State ......................................................................91 7.2.2.4 Package C6 State ......................................................................92 7.3 Sleep States .....................................................................................................92 7.4 ACPI P-States (Intel Turbo Boost Technology) .....................................................92 7.5 Enhanced Intel SpeedStep Technology ...............................................................93 Boxed Processor Specifications ................................................................................95 8.1 Introduction ......................................................................................................95 8.2 Mechanical Specifications ....................................................................................96 8.2.1 Boxed Processor Cooling Solution Dimensions.............................................96 8.2.2 Boxed Processor Fan Heatsink Weight .......................................................98 8.2.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....98 8.3 Electrical Requirements ......................................................................................98 8.3.1 Fan Heatsink Power Supply ......................................................................98 8.4 Thermal Specifications........................................................................................99 8.4.1 Boxed Processor Cooling Requirements......................................................99 8.4.2 Variable Speed Fan ............................................................................... 101
Datasheet, Volume 1
Figures
1-1 2-1 2-2 2-3 2-4 2-5 3-1 3-2 3-3 3-4 3-5 6-1 6-2 6-3 6-4 7-1 8-1 8-2 8-3 8-4 8-5 8-6 8-7 8-8 8-9 High-Level View of Processor Interfaces ................................................................. 9 Active ODT for a Differential Link Example ............................................................ 13 Input Device Hysteresis ..................................................................................... 22 VCC Static and Transient Tolerance Load Lines....................................................... 26 VTT Static and Transient Tolerance Load Line ........................................................ 28 VCC Overshoot Example Waveform ...................................................................... 31 Processor Package Assembly Sketch .................................................................... 35 Processor Package Drawing (Sheet 1 of 2) ............................................................ 36 Processor Package Drawing (Sheet 2 of 2) ............................................................ 37 Processor Top-side Markings ............................................................................... 39 Processor Land Coordinates and Quadrants, Top View ............................................ 40 Intel Core i7-900 Desktop Processor Extreme Edition Series Thermal Profile ......... 77 Intel Core i7-900 Desktop Processor Series Thermal Profile ................................ 78 Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location ........... 80 Frequency and Voltage Ordering.......................................................................... 82 Power State...................................................................................................... 90 Mechanical Representation of the Boxed Processor................................................. 95 Space Requirements for the Boxed Processor (side view)........................................ 96 Space Requirements for the Boxed Processor (top view) ......................................... 97 Space Requirements for the Boxed Processor (overall view) .................................... 97 Boxed Processor Fan Heatsink Power Cable Connector Description ........................... 98 Baseboard Power Header Placement Relative to Processor Socket ............................ 99 Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view) .............. 100 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view) ............. 100 Boxed Processor Fan Heatsink Set Points ............................................................ 101
Datasheet, Volume 1
Tables
1-1 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 3-1 3-2 3-3 4-1 4-2 5-1 6-1 6-2 6-3 6-4 6-5 6-6 6-7 7-1 7-2 7-3 8-1 8-2 References........................................................................................................11 Voltage Identification Definition ...........................................................................16 Market Segment Selection Truth Table for MS_ID[2:0] ...........................................18 Signal Groups ...................................................................................................19 Signals with ODT ...............................................................................................20 PECI DC Electrical Limits.....................................................................................21 Processor Absolute Minimum and Maximum Ratings ...............................................23 Voltage and Current Specifications .......................................................................24 VCC Static and Transient Tolerance.......................................................................25 VTT Voltage Identification (VID) Definition .............................................................26 VTT Static and Transient Tolerance ......................................................................27 DDR3 Signal Group DC Specifications ...................................................................28 RESET# Signal DC Specifications .........................................................................29 TAP Signal Group DC Specifications ......................................................................29 PWRGOOD Signal Group DC Specifications ............................................................30 Control Sideband Signal Group DC Specifications ...................................................30 VCC Overshoot Specifications ..............................................................................31 Intel QuickPath Interconnect (Intel QPI) Specifications .........................................32 Parameter Values for Intel QuickPath Interconnect (Intel QPI) Channel at 6.4 GT/s ..33 Processor Loading Specifications ..........................................................................38 Package Handling Guidelines ...............................................................................38 Processor Materials ............................................................................................39 Land Listing by Land Name .................................................................................41 Land Listing by Land Number ..............................................................................56 Signal Definitions...............................................................................................71 Processor Thermal Specifications ........................................................................76 Intel Core i7-900 Desktop Processor Extreme Edition Series Thermal Profile .........77 Intel Core i7-900 Desktop Processor Series Thermal Profile ................................78 Thermal Solution Performance above TCONTROL ......................................................79 Supported PECI Command Functions and Codes ....................................................86 GetTemp0() Error Codes.....................................................................................86 Storage Condition Ratings...................................................................................87 Power On Configuration Signal Options .................................................................89 Coordination of Thread Power States at the Core Level ...........................................90 Processor S-States.............................................................................................92 Fan Heatsink Power and Signal Specifications ........................................................99 Fan Heatsink Power and Signal Specifications ...................................................... 101
Datasheet, Volume 1
Revision History
Revision Number 001 002 003 Initial release Added Intel Core i7-970 desktop processor series Added Intel Core i7-990X desktop processor Extreme Edition Added Intel Core i7-980 desktop processor
Description
Date March 2010 July 2010 June 2011
Datasheet, Volume 1
Datasheet, Volume 1
Introduction
Introduction
The Intel Core i7-900 desktop processor Extreme Edition series and Intel Core i7-900 desktop processor series on 32-nm process processor is intended for high performance, high-end desktop systems. Several architectural and microarchitectural enhancements have been added to this processor including six processor cores in the processor package and increased shared cache. The Intel Core i7-900 desktop processor Extreme Edition series and and Intel Core i7-970 desktop processor series on 32-nm process is a desktop multi-core processor with these key technologies: Integrated memory controller Point-to-point link interface based on Intel QuickPath Interconnect (Intel QPI) Figure 1-1 shows the interfaces used with these new technologies.
Figure 1-1.
High-Level View of Processor Interfaces

CH 0
Processor
CH 1 CH 2
System Memory (DDR3)
Intel QuickPath Interconnect (Intel QPI)
Note: Note: Note:
In this document the Intel Core i7-900 desktop processor Extreme Edition series on 32-nm process will be referred to as the processor. The Intel Core i7-900 desktop processor Extreme Edition series on 32-nm process refers to the Intel Core i7-980X and i7-990X desktop processor Extreme Edition. The Intel Core i7-900 desktop processor series on 32-nm process refers to the Intel Core i7-980 and i7-970 desktop processors. The processor is optimized for performance with the power efficiency of a low-power microarchitecture. This document provides DC electrical specifications, differential signaling specifications, pinout and signal definitions, package mechanical specifications and thermal requirements, and additional features pertinent to the implementation and operation of the processor. The processor is a multi-core processor built on the 32-nm process technology, that uses up to 130 W thermal design power (TDP). The processor features an Intel QPI point-to-point link capable of up to 6.4 GT/s, 12 MB Level 3 cache, and an integrated memory controller.
Datasheet, Volume 1
Introduction
The processor supports all the existing Streaming SIMD Extensions 2 (SSE2), Streaming SIMD Extensions 3 (SSE3) and Streaming SIMD Extensions 4 (SSE4). The processor supports several Advanced Technologies: Intel 64 Technology (Intel 64), Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT), Turbo Boost Technology, and Hyper-Threading Technology.
1.1
Terminology
A # symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when VTTPWRGOOD is high, the VTT power rail is stable. _N and _P after a signal name refers to a differential pair. Commonly used terms are explained here for clarification: Intel Core i7-900 desktop processor Extreme Edition series and Intel Core i7-900 desktop processor series on 32-nm process The entire product, including processor substrate and integrated heat spreader (IHS). 1366-land LGA package The processor is available in a Flip-Chip Land Grid Array (FC-LGA) package, consisting of the processor mounted on a land grid array substrate with an integrated heat spreader (IHS). LGA1366 Socket The processor (in the LGA 1366 package) mates with the system board through this surface mount, 1366-contact socket. DDR3 Double Data Rate 3 Synchronous Dynamic Random Access Memory (SDRAM) is the name of the new DDR memory standard that is being developed as the successor to DDR2 SRDRAM. Intel QuickPath Interconnect (Intel QPI) Intel QPI is a cache-coherent, point-to-point link-based electrical interconnect specification for Intel processors and chipsets. Intel QuickPath Technology Memory Controller A memory controller that is integrated into the processor die. Integrated Heat Spreader (IHS) A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. Functional Operation Refers to the normal operating conditions in which all processor specifications, including DC, AC, signal quality, mechanical, and thermal, are satisfied. Enhanced Intel SpeedStep Technology Enhanced Intel SpeedStep Technology allows the operating system to reduce power consumption when performance is not needed. Execute Disable Bit Execute Disable allows memory to be marked as executable or non-executable when combined with a supporting operating system. If code attempts to run in non-executable memory, the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the Intel Architecture Software Developer's Manual for more detailed information. Refer to http://developer.intel.com/ for future reference on up to date nomenclatures. Intel 64 Architecture An enhancement to the Intel IA-32 architecture, allowing the processor to execute operating systems and applications written to
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Datasheet, Volume 1
Introduction
take advantage of Intel 64. Further details on the Intel 64 architecture and programming model can be found at http://developer.intel.com/technology/intel64/. Intel Virtualization Technology (Intel VT) A set of hardware enhancements to Intel server and client platforms that can improve virtualization solutions. Intel VT provides a foundation for widely-deployed virtualization solutions and enables a more robust hardware assisted virtualization solution. More information can be found at: http://www.intel.com/technology/virtualization/ Unit Interval (UI) Signaling convention that is binary and unidirectional. In this binary signaling, one bit is sent for every edge of the forwarded clock, whether it is a rising edge or a falling edge. If a number of edges are collected at instances t1, t2, tn,...., tk then the UI at instance n is defined as:
UI
n
=t
n 1
Jitter Any timing variation of a transition edge or edges from the defined Unit Interval. Storage Conditions Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. OEM Original Equipment Manufacturer.
1.2
References
Material and concepts available in the following documents may be beneficial when reading this document.
Table 1-1.
References
Document Intel Intel Core i7-900 Desktop Processor Extreme Edition Series and Core i7-900 Desktop Processor Series on 32-nm Process Specification Update Intel Core i7-900 Desktop Processor Extreme Edition Series on 32-nm Process Datasheet, Volume 2 Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series and LGA1366 Socket Thermal and Mechanical Design Guide Intel X58 Express Chipset Datasheet AP-485, Intel Processor Identification and the CPUID Instruction IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide, Part 1 Volume 3B: Systems Programming Guide, Part 2 Location http://www.intel.com/Assets/PDF/spe cupdate/323254.pdf http://download.intel.com/design/pro cessor/datashts/323253.pdf http://download.intel.com/design/pro cessor/designex/320837.pdf http://www.intel.com/Assets/PDF/dat asheet/320838.pdf http://www.intel.com/design/processo r/applnots/241618.htm
http://www.intel.com/products/proces sor/manuals/
Notes: 1. Contact your Intel representative to receive the latest revisions of these documents. 2. Document is available publicly at http://developer.intel.com. 3. Document not available at time of printing. 4. The LGA1366 Socket and Heatsink Keepout Zones Mechanical Models will be made available electronically.
Datasheet, Volume 1
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Introduction
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Datasheet, Volume 1
Electrical Specifications
2
2.1
Intel QuickPath Interconnect (Intel QPI) Differential Signaling
The processor provides an Intel QPI port for high speed serial transfer between other Intel QPI-enabled components. The Intel QPI port consists of two unidirectional links (for transmit and receive). Intel QPI uses a differential signalling scheme where pairs of opposite-polarity (D_P, D_N) signals are used. On-die termination (ODT) provided on the processor silicon and termination is to VSS. Intel chipsets also provide ODT; thus, eliminating the need to terminate the Intel QPI links on the system board. Intel strongly recommends performing analog simulations of the Intel QPI interface. Figure 2-1 illustrates the active ODT. Signal listings are included in Table 2-3 and Table 2-4. See Chapter 5 for the pin signal definitions. All Intel QPI signals are in the differential signal group.
Figure 2-1.
Active ODT for a Differential Link Example
TX
Signal Signal
RX
RTT
RTT
RTT
RTT
2.2
Power and Ground Lands

For clean on-chip processor core power distribution, the processor has 210 VCC pads and 119 VSS pads associated with VCC; 8 VTTA pads and 5 VSS pads associated with VTTA; 28 VTTD pads and 17 VSS pads associated with VTTD, 28 VDDQ pads and 17 VSS pads associated with VDDQ; and 3 VCCPLL pads. All VCCP, VTTA, VTTD, VDDQ, and VCCPLL lands must be connected to their respective processor power planes, while all VSS lands must be connected to the system ground plane. The processor VCC lands must be supplied with the voltage determined by the processor Voltage IDentification (VID) signals. Table 2-1 specifies the voltage level for the various VIDs.
2.3
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic capacitors, supply current during longer lasting changes in current demand; such as, coming out of an idle condition. Similarly, capacitors act as a storage well for current when entering an idle
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condition from a running condition. Care must be taken in the baseboard design to ensure that the voltage provided to the processor remains within the specifications listed in Table 2-7. Failure to do so can result in timing violations or reduced lifetime of the processor.
2.3.1
VCC, VTTA, VTTD, VDDQ Decoupling

Voltage regulator solutions need to provide bulk capacitance and the baseboard designer must assure a low interconnect resistance from the regulator to the LGA1366 socket. Bulk decoupling must be provided on the baseboard to handle large current swings. The power delivery solution must insure the voltage and current specifications are met (as defined in Table 2-7).
2.4
Processor Clocking (BCLK_DP, BCLK_DN)

The processor core, Intel QPI, and integrated memory controller frequencies are generated from BCLK_DP and BCLK_DN. Unlike previous processors based on front side bus architecture, there is no direct link between core frequency and Intel QPI link frequency (such as, no core frequency to Intel QPI multiplier). The processor maximum core frequency, Intel QPI link frequency and integrated memory controller frequency, are set during manufacturing. It is possible to override the processor core frequency setting using software. This permits operation at lower core frequencies than the factory set maximum core frequency. The processors maximum non-turbo core frequency is configured during power-on reset by using values stored internally during manufacturing. The stored value sets the highest core multiplier at which the particular processor can operate. If lower maximum non-turbo speeds are desired, the appropriate ratio can be configured using the CLOCK_FLEX_MAX MSR. The processor uses differential clocks (BCLK_DP, BCLK_DN). Clock multiplying within the processor is provided by the internal phase locked loop (PLL) that requires a constant frequency BCLK_DP, BCLK_DN input, with exceptions for spread spectrum clocking. The processor core frequency is determined by multiplying the ratio by 133 MHz.
2.4.1
PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 2-7 for DC specifications.
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Datasheet, Volume 1
2.5
Voltage Identification (VID)

The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator Down (VRD) 11.1 Design Guidelines. The voltage set by the VID signals is the reference voltage regulator output voltage to be delivered to the processor VCC pins. VID signals are CMOS push/pull drivers. Refer to Table 2-15 for the DC specifications for these signals. The VID codes will change due to temperature and/or current load changes in order to minimize the power of the part. A voltage range is provided in Table 2-7. The specifications have been set such that one voltage regulator can operate with all supported frequencies. Individual processor VID values may be set during manufacturing such that two devices at the same core frequency may have different default VID settings. This is reflected by the VID range values provided in Table 2-1. The processor uses eight voltage identification signals, VID[7:0], to support automatic selection of voltages. Table 2-1 specifies the voltage level corresponding to the state of VID[7:0]. A 1 in this table refers to a high voltage level and a 0 refers to a low voltage level. If the processor socket is empty (VID[7:0] = 11111111), or the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself. See the Voltage Regulator Down (VRD) 11.1 Design Guidelines for further details. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the loadline. It should be noted that a low-to-high or high-to-low voltage state change will result in as many VID transitions as necessary to reach the target core voltage. Transitions above the maximum specified VID are not permitted. Table 2-8 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 2-8. The VR used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 2-7 and Table 2-8. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for further details.
Datasheet, Volume 1
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Table 2-1.
VID 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Voltage Identification Definition (Sheet 1 of 2)

VID 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID VCC_MAX 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 VID 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID 6 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID 5 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID 4 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 VID 3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID 2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VCC_MAX 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95626 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84374 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 0.76250 0.75625 0.75000
VID 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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Table 2-1.
VID 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Voltage Identification Definition (Sheet 2 of 2)

VID 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID VCC_MAX 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 VID 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID 4 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID 3 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID 2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 VCC_MAX 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF
VID 5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Table 2-2.
Market Segment Selection Truth Table for MS_ID[2:0]

MSID2 0 0 0 0 1 1 1 1 Notes: 1. The MSID[2:0] signals are provided to indicate the market segment for the processor and may be used for future processor compatibility or for keying. MSID1 0 0 1 1 0 0 1 1 MSID0 0 1 0 1 0 1 0 1 Reserved Reserved Reserved Reserved Reserved Reserved Intel Core i7-900 desktop processor Extreme Edition series and Intel Core i7-900 desktop processor series on 32-nm process Reserved Description1
2.6
Reserved or Unused Signals

All Reserved (RSVD) signals must remain unconnected. Connection of these signals to VCC, VTTA, VTTD, VDDQ, VCCPLL, VSS, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all Reserved signals. For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level, except for unused integrated memory controller inputs, outputs, and bi-directional pins that may be left floating. Unused active high inputs should be connected through a resistor to ground (VSS). Unused outputs may be left unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability.
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Datasheet, Volume 1
2.7
Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 2-3. The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board. The signals that have ODT are listed in Table 2-4.
Table 2-3.
Signal Groups (Sheet 1 of 2)

Signal Group System Reference Clock Differential Clock Input BCLK_DP, BCLK_DN Type Signals1,2
Intel QPI Signal Groups Differential Differential Intel QPI Input Intel QPI Output QPI_DRX_D[N/P][19:0], QPI_CLKRX_DP, QPI_CLKRX_DN QPI_DTX_D[N/P][19:0], QPI_CLKTX_DP, QPI_CLKTX_DN
DDR3 Reference Clocks Differential DDR3 Output DDR{0/1/2}_CLK[D/P][3:0]
DDR3 Command Signals Single ended Single ended DDR3 Control Signals Single ended DDR3 Data Signals Single ended Differential TAP Single ended Single ended Control Sideband Single ended Single ended Single ended Single Ended Single Ended Single ended Single ended Asynchronous GTL Output Asynchronous GTL Input GTL Bi-directional Asynchronous Bi-directional Analog Input Asynchronous GTL Bidirectional Asynchronous GTL Output PRDY# PREQ# CAT_ERR#, BPM#[7:0] PECI COMP0, QPI_CMP[0], DDR_COMP[2:0] PROCHOT# THERMTRIP# VID[7:6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0] VTT_VID[4:2] TAP Input GTL Output TCK, TDI, TMS, TRST# TDO CMOS Bi-directional CMOS Bi-directional DDR{0/1/2}_DQ[63:0] DDR{0/1/2}_DQS_[N/P][7:0] CMOS Output DDR{0/1/2}_CS#[5:4], DDR{0/1/2}_CS#[1:0], DDR{0/1/2}_ODT[3:0], DDR{0/1/2}_CKE[3:0] CMOS Output Asynchronous Output DDR{0/1/2}_RAS#, DDR{0/1/2}_CAS#, DDR{0/1/2}_WE#, DDR{0/1/2}_MA[15:0], DDR{0/1/2}_BA[2:0] DDR{0/1/2}_RESET#
Single ended
CMOS Input/Output
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Table 2-3.
Signal Groups (Sheet 2 of 2)

Signal Group Single ended Single ended Reset Signal Single ended PWRGOOD Signals Single ended Power/Other Power Asynchronous CMOS Output Sense Points Other Notes: 1. 2. Refer to Chapter 5 for signal descriptions. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2. VCC, VTTA, VTTD, VCCPLL, VDDQ PSI# VCC_SENSE, VSS_SENSE SKTOCC#, DBR# Asynchronous Input VCCPWRGOOD, VTTPWRGOOD, VDDPWRGOOD Reset Input RESET# Type CMOS Output Analog Input VTT_VID[4:2] ISENSE Signals1,2
Table 2-4.
Signals with ODT

QPI_DRX_DP[19:0], QPI_DRX_DN[19:0], QPI_DTX_DP[19:0], QPI_DTX_DN[19:0], QPI_CLKRX_D[N/P], QPI_CLKTX_D[N/P] DDR{0/1/2}_DQ[63:0], DDR{0/1/2}_DQS_[N/P][7:0], DDR{0/1/2}_PAR_ERR#[0:2], VDDPWRGOOD BCLK_ITP_D[N/P] PECI BPM#[7:0], PREQ#, TRST#, VCCPWRGOOD, VTTPWRGOOD
Note: 1. Unless otherwise specified, signals have ODT in the package with 50 pulldown to VSS. 2. PREQ#, BPM[7:0], TDI, TMS and BCLK_ITP_D[N/P] have ODT in package with 35 pullup to VTT. 3. VCCPWRGOOD, VDDPWRGOOD, and VTTPWRGOOD have ODT in package with a 10 k to 20 k pulldown to VSS. 4. TRST# has ODT in package with a 1 k to 5 k pullup to VTT. 5. All DDR signals are terminated to VDDQ/2 6. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2. 7. While TMS and TDI do not have On-Die Termination, these signals are weakly pulled up using a 15 k resistor to VTT 8. While TCK does not have On-Die Termination, this signal is weakly pulled down using a 15 kresistor to VSS.
All Control Sideband Asynchronous signals are required to be asserted/de-asserted for at least eight BCLKs for the processor to recognize the proper signal state. See Section 2.11 for the DC specifications. See Chapter 6 for additional timing requirements for entering and leaving the low power states.
2.8
Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended that the processor be first in the TAP chain and followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.
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Datasheet, Volume 1
2.9
Platform Environmental Control Interface (PECI) DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature. Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information may be found in the Platform Environment Control Interface (PECI) Specification.
2.9.1
DC Characteristics
The PECI interface operates at a nominal voltage set by VTTD. The set of DC electrical specifications shown in Table 2-5 is used with devices normally operating from a VTTD interface supply. VTTD nominal levels will vary between processor families. All PECI devices will operate at the VTTD level determined by the processor installed in the system. For specific nominal VTTD levels, refer to Table 2-7.
Table 2-5.
PECI DC Electrical Limits

Symbol Vin Vhysteresis Vn Vp Isource Isink Ileak+ IleakCbus Vnoise Definition and Conditions Input Voltage Range Hysteresis Negative-edge threshold voltage Positive-edge threshold voltage High level output source (VOH = 0.75 * VTTD) Low level output sink (VOL = 0.25 * VTTD) High impedance state leakage to VTTD (Vleak = VOL) High impedance leakage to GND (Vleak = VOH) Bus capacitance per node Signal noise immunity above 300 MHz Min -0.150 0.1 * VTTD 0.275 * VTTD 0.550 * VTTD -6.0 0.5 N/A N/A N/A 0.1 * VTTD Max VTTD N/A 0.500 * VTTD 0.725 * VTTD N/A 1.0 100 100 10 N/A Units V V V V mA mA A A pF Vp-p 2 2 Notes1
Note: 1. VTTD supplies the PECI interface. PECI behavior does not affect VTTD min/max specifications. 2. The leakage specification applies to powered devices on the PECI bus.
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2.9.2
Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 2-2 as a guide for input buffer design.
Figure 2-2.
Input Device Hysteresis
VTTD Maximum VP Minimum VP Minimum Hysteresis Maximum VN Minimum VN PECI Ground PECI Low Range Valid Input Signal Range PECI High Range
2.10
Absolute Maximum and Minimum Ratings

Table 2-6 specifies absolute maximum and minimum ratings, which lie outside the functional limits of the processor. Only within specified operation limits can functionality and long-term reliability be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor l ong-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from ElectroStatic Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields.
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Datasheet, Volume 1
Table 2-6.
Processor Absolute Minimum and Maximum Ratings

Symbol VCC VTTA Parameter Processor Core voltage with respect to VSS Voltage for the analog portion of the integrated memory controller, QPI link and Shared Cache with respect to VSS Voltage for the digital portion of the integrated memory controller, QPI link and Shared Cache with respect to VSS Processor I/O supply voltage for DDR3 with respect to VSS Processor PLL voltage with respect to VSS Processor case temperature Storage temperature Min -0.3 -0.3 Max 1.4 1.4 Unit V V 3 Notes1, 2
VTTD VDDQ VCCPLL TCASE TSTORAGE
-0.3
1.4
-0.3 -0.3 See Chapter 6 See Chapter 6
1.8 2.0 See Chapter 6 See Chapter 6
V V C C
Notes: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. VTTA and VTTD should be derived from the same VR.
2.11
Processor DC Specifications
The processor DC specifications in this section are defined at the processor pads, unless noted otherwise. See Chapter 4 for the processor land listings and Chapter 5 for signal definitions. Voltage and current specifications are detailed in Table 2-7. For platform planning, refer to Table 2-8 that provides VCC static and transient tolerances. This same information is presented graphically in Figure 2-3. The DC specifications for the DDR3 signals are listed in Table 2-11. Control Sideband and Test Access Port (TAP) are listed in Table 2-12 through Table 2-15. Table 2-7 through Table 2-15 list the DC specifications for the processor and are valid only while meeting specifications for case temperature (TCASE as specified in Chapter 6, Thermal Specifications), clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.
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2.11.1
Table 2-7.
DC Voltage and Current Specification

Voltage and Current Specifications
Symbol VID VID range Processor Number i7-990X i7-980X i7-980 i7-970 VCC for processor core 3.46 3.33 3.33 3.20 GHz GHz GHz GHz See Table 2-8 and Figure 2-3 V
3,4
Parameter
Min 0.8
Typ
Max 1.375
Unit V
Notes 1
2
VCC
VTTA
Voltage for the analog portion of the integrated memory controller, QPI link and Shared Cache Voltage for the digital portion of the integrated memory controller, QPI link and Shared Cache Processor I/O supply voltage for DDR3 PLL supply voltage (DC + AC specification) Processor Number i7-990X i7-980X i7-980 i7-970 ICC for processor 3.46 3.33 3.33 3.20 GHz GHz GHz GHz
See Table 2-10 and Figure 2-4
VTTD VDDQ VCCPLL
See Table 2-9 and Figure 2-4 1.425 1.71 1.5 1.8 1.575 1.89
V V V
ICC
145 145 145 145 5
ITTA
Current for the analog portion of the integrated memory controller, QPI link and Shared Cache Current for the digital portion of the integrated memory controller, QPI link and Shared Cache Processor I/O supply current for DDR3 Processor I/O supply current for DDR3 while in S3 PLL supply current (DC + AC specification)
ITTD IDDQ IDDQS3 ICC_VCCPLL Notes: 1. 2.
23 6 1 1.1
A A A A
7
3.
4. 5. 6. 7.
Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note that this differs from the VID employed by the processor during a power management event (Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States). The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. Refer to Table 2-8 and Figure 2-3 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. See Table 2-9 for details on VTT Voltage Identification. See Table 2-10 and Figure 2-4 for details on the VTT Loadline ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 2-3 for details. This specification is based on a processor temperature, as reported by the DTS, of less than or equal to TCONTROL25.
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Table 2-8.
VCC Static and Transient Tolerance

ICC (A) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 78 85 90 95 100 105 110 115 120 125 130 135 140 VCC_Max (V) VID 0.000 VID 0.004 VID 0.008 VID 0.012 VID 0.016 VID 0.020 VID 0.024 VID 0.028 VID 0.032 VID 0.036 VID 0.040 VID 0.044 VID 0.048 VID 0.052 VID 0.056 VID 0.060 VID 0.062 VID 0.068 VID 0.072 VID 0.076 VID 0.080 VID 0.084 VID 0.088 VID 0.092 VID 0.096 VID 0.100 VID 0.104 VID 0.108 VID 0.112 VCC_Typ (V) VID 0.019 VID 0.023 VID 0.027 VID 0.031 VID 0.035 VID 0.039 VID 0.043 VID 0.047 VID 0.051 VID 0.055 VID 0.059 VID 0.063 VID 0.067 VID 0.071 VID 0.075 VID 0.079 VID 0.081 VID 0.087 VID 0.091 VID 0.095 VID 0.099 VID 0.103 VID 0.107 VID 0.111 VID 0.115 VID 0.119 VID 0.123 VID 0.127 VID 0.131 VCC_Min (V) VID 0.038 VID 0.042 VID 0.046 VID 0.050 VID 0.054 VID 0.058 VID 0.062 VID 0.066 VID 0.070 VID 0.074 VID 0.078 VID 0.082 VID 0.086 VID 0.090 VID 0.094 VID 0.098 VID 0.100 VID 0.106 VID 0.110 VID 0.114 VID 0.118 VID 0.122 VID 0.126 VID 0.130 VID 0.134 VID 0.138 VID 0.142 VID 0.146 VID 0.150 Notes 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3
Notes: 1. The VCC_MIN and VCC_MAX loadlines represent static and transient limits. See Section 2.11.2 for VCC overshoot specifications. 2. This table is intended to aid in reading discrete points on Figure 2-3. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and VSS_SENSE lands. Refer to the Voltage Regulator Down (VRD) 11.1 Design Guidelines for socket load line guidelines and VR implementation.
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Figure 2-3.
VCC Static and Transient Tolerance Load Lines

Icc [A] 0 VID - 0.000 VID - 0.013 VID - 0.025 Vcc Maximum VID - 0.038 VID - 0.050 VID - 0.063 VID - 0.075 V VID - 0.088 c c VID - 0.100 V VID - 0.113 VID - 0.125 VID - 0.138 VID - 0.150 VID - 0.163 VID - 0.175 Vcc Minimum Vcc Typical 10 20 30 40 50 60 70 80 90 100 110 120 130 140
Table 2-9.
VTT Voltage Identification (VID) Definition

VTT VR - VID Input VID7 0 0 0 0 0 0 0 0 VID6 1 1 1 1 1 1 1 1 VID5 0 0 0 0 0 0 0 0 VID4 0 0 0 0 1 1 1 1 VID3 0 0 1 1 0 0 1 1 VID2 0 1 0 1 0 1 0 1 VID1 1 1 1 1 1 1 1 1 VID0 0 0 0 0 0 0 0 0 VTT_Typ 1.220 V 1.195 V 1.170 V 1.145 V 1.120 V 1.095 V 1.070 V 1.045 V
Notes: 1. The associated voltage with the VTT_VID codes listed in this table do not match the Voltage RegulatorDown (VRD) 11.1 Design Guidelines, they include a +20 mV offset. 2. This is a typical voltage. See Table 2-10 for VTT_Max and VTT_Min voltage.
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Table 2-10. VTT Static and Transient Tolerance 1

ITT (A) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Notes: 1. The ITT listed in this table is a sum of ITTA and ITTD. 2. The loadlines specify voltage limits at the die measured at the VTT_SENSE and VSS_SENSE_VTT lands. Voltage regulation feedback for voltage regulator circuits must also be taken from the processor VTT_SENSE and VSS_SENSE_VTT lands. VTT_Max (V) VID + 0.0315 VID + 0.0255 VID + 0.0195 VID + 0.0135 VID + 0.0075 VID + 0.0015 VID 0.0045 VID 0.0105 VID 0.0165 VID 0.0225 VID 0.0285 VID 0.0345 VID 0.0405 VID 0.0465 VID 0.0525 VID 0.0585 VID 0.0645 VID 0.0705 VID 0.0765 VID 0.0825 VID 0.0885 VID 0.0945 VID 0.1005 VID 0.1065 VID 0.1125 VID 0.1185 VID 0.1245 VID 0.1305 VID 0.1365 VTT_Typ (V) VID 0.0000 VID 0.0060 VID 0.0120 VID 0.0180 VID 0.0240 VID 0.0300 VID 0.0360 VID 0.0420 VID 0.0480 VID 0.0540 VID 0.0600 VID 0.0660 VID 0.0720 VID 0.0780 VID 0.0840 VID 0.0900 VID 0.0960 VID 0.1020 VID 0.1080 VID 0.1140 VID 0.1200 VID 0.1260 VID 0.1320 VID 0.1380 VID 0.1440 VID 0.1500 VID 0.1560 VID 0.1620 VID 0.1680 VTT_Min (V) VID 0.0315 VID 0.0375 VID 0.0435 VID 0.0495 VID 0.0555 VID 0.0615 VID 0.0675 VID 0.0735 VID 0.0795 VID 0.0855 VID 0.0915 VID 0.0975 VID 0.1035 VID 0.1095 VID 0.1155 VID 0.1215 VID 0.1275 VID 0.1335 VID 0.1395 VID 0.1455 VID 0.1515 VID 0.1575 VID 0.1635 VID 0.1695 VID 0.1755 VID 0.1815 VID 0.1875 VID 0.1935 VID 0.1995 Notes
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Figure 2-4.
VTT Static and Transient Tolerance Load Line

Itt [A] (sum of Itta and Ittd) 0 0.0500 0.0375 0.0250 0.0125 0.0000 V t t V -0.0125 -0.0250 -0.0375 -0.0500 -0.0625 -0.0750 -0.0875 -0.1000 -0.1125 -0.1250 -0.1375 -0.1500 -0.1625 -0.1750 -0.1875 -0.2000 -0.2125 Vtt Minimum Vtt Typical Vtt Maximum 5 10 15 20 25
Table 2-11. DDR3 Signal Group DC Specifications

Symbol VIL VIH VOL VOH RON RON RON RON RON ILI Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage DDR3 Clock Buffer On Resistance DDR3 Command Buffer On Resistance DDR3 Reset Buffer On Resistance DDR3 Control Buffer On Resistance DDR3 Data Buffer On Resistance Input Leakage Current Min 0.57*VDDQ 21 16 25 21 21 N/A 99 24.65 128.7 Typ (VDDQ / 2)* (RON / (RON+RVTT_TERM)) VDDQ ((VDDQ / 2)* (RON/(RON+RVTT_TERM)) N/A 100 24.9 130 Max 0.43*VDDQ 31 24 75 31 33 1 101 25.15 131.30 Units V V V V mA 5 5 5 4 7 Notes1 2,4 3
DDR_COMP0 COMP Resistance DDR_COMP1
COMP Resistance
DDR_COMP2 COMP Resistance
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
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3. 4. 5. 6.
VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality specifications. COMP resistance must be provided on the system board with 1% resistors. DDR_COMP[2:0] resistors are to VSS This is the pull down driver resistance.
Table 2-12. RESET# Signal DC Specifications

Symbol VIL VIH ILI Parameter Input Low Voltage Input High Voltage Input Leakage Current Min 0.80 * VTTA Typ Max 0.40 * VTTA 200 Units V V A Notes1 2 2,4 3
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VTTA referred to in these specifications refers to instantaneous VTTA. 3. For Vin between 0 V and VTTA. Measured when the driver is tristated. 4. VIH and VOH may experience excursions above VTT.
Table 2-13. TAP Signal Group DC Specifications

Symbol VIL VIH VOL VOH Ron ILI Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Buffer on Resistance Input Leakage Current Min 0.75 * VTTA VTTA 10 Typ Max 0.40 * VTTA VTTA * RON / (RON + Rsys_term) 18 200 Units V V V V A 3 Notes1 2 2,4 2 2,4
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VTTA referred to in these specifications refers to instantaneous VTTA. 3. For Vin between 0 V and VTTA. Measured when the driver is tristated. 4. VIH and VOH may experience excursions above VTT.
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Table 2-14. PWRGOOD Signal Group DC Specifications

Symbol VIL VIL VIH VIH Ron ILI Parameter Input Low Voltage for VCCPWRGOOD and VTTPWRGOOD Signals Input Low Voltage for VDDPWRGOOD Signal Input High Voltage for VCCPWRGOOD and VTTPWRGOOD Signals Input High Voltage for VDDPWRGOOD Signal Buffer on Resistance Input Leakage Current Min Typ Max 0.25 * VTTA 0.29 Units V Notes1 2,5
0.75 * VTTA 0.87 10
2,5
18 200
V A
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VTTA referred to in these specifications refers to instantaneous VTTA. 3. For Vin between 0 V and VTTA. Measured when the driver is tristated. 4. VIH and VOH may experience excursions above VTT. 5. This specification applies to VCCPWRGOOD and VTTPWRGOOD 6. This specification applies to VDDPWRGOOD
Table 2-15. Control Sideband Signal Group DC Specifications

Symbol VIL VIL VIH VOL VOH Ron Ron ILI COMP0 Parameter Input Low Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Buffer on Resistance Buffer on Resistance for VID[7:0] Input Leakage Current COMP Resistance Min 0.76 * VTTA VTTA 10 49.4 Typ 100 49.9 Max 0.64 * VTTA 0.61 * VTTA VTTA * RON / (RON + Rsys_term) 18 200 50.40 Units V V V V V A 3 5 Notes1 2 2 2 2,4 2,4
Notes: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. The VTTA referred to in these specifications refers to instantaneous VTTA. 3. For Vin between 0 V and VTTA. Measured when the driver is tristated. 4. VIH and VOH may experience excursions above VTT. 5. COMP resistance must be provided on the system board with 1% resistors. COMP0 resistors are to VSS.
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Datasheet, Volume 1
2.11.2
VCC Overshoot Specification

The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high-to-low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
Table 2-16. VCC Overshoot Specifications

Symbol VOS_MAX TOS_MAX Parameter Magnitude of VCCP overshoot above VID Time duration of VCCP overshoot above VID Min Max 50 25 Units mV s Figure 2-5 2-5 Notes
Figure 2-5.
VCC Overshoot Example Waveform
Example Overshoot Waveform

VID + VOS
VOS
Voltage (V)
VID
TOS
Time TOS: Overshoot time above VID VOS: Overshoot above VID
2.11.3
Die Voltage Validation

Core voltage (VCC) overshoot events at the processor must meet the specifications in Table 2-16 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.
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31
2.12
Intel QuickPath Interconnect (Intel QPI) Specifications

The processor Intel QPI specifications in this section are defined at the processor pins. Routing topologies are dependent on the processors supported and the chipset used in the design. In most cases, termination resistors are not required as these are integrated into the processor silicon.
Table 2-17. Intel QuickPath Interconnect (Intel QPI) Specifications

Symbol UIavg Parameter Average UI size at x GT/s (Where x= 4.8 GT/s, 6.4 GT/s, etc.) Defined as the slope of the rising or falling waveform as measured between 100 mV of the differential transmitter output, for any data or clock. Defined as: (max(ZTX_LOW_CM_DC) min(ZTX_LOW_CM_DC)) /ZTX_LOW_CM_DC expressed in%, over full range of Tx single ended voltage Defined as: (max(ZTX_LOW_CM_DC) min(ZTX_LOW_CM_DC)) /ZTX_LOW_CM_DC expressed in%, over full range of Tx single ended voltage # of UI over which the eye mask voltage and timing specification needs to be validated Single ended DC impedance to GND for either D+ or D- of any data bit at Tx Single ended DC impedance to GND for either D+ or D- of any data bit at Tx Link Detection Resistor Phase variability between reference Clk (at Tx input) and Tx output. Phase skew between D+ and D- lines for any data bit at Rx Time taken by clock detector to observe clock stability Time taken by clock frequency detector to decide slow vs operational clock after stable clock Bit Error Rate per lane valid for 4.8 GT/s and 6.4 GT/s % error in Tx equalization setting as measured by errors in DC levels when sending a steady 1. COMP Resistance Min 0.999 * nominal Nom 1000/f Max 1.001 * nominal Unit psec Notes
Tslew-rise-fall-pin
10
25
V / nsec
ZTX_LOW_CM_DC
-6
% of ZTX_LOW_CM_DC
ZRX_LOW_CM_DC
-6
% of ZTX_LOW_CM_DC
NMIN-UI-Validation ZTX_HIGH_CM_DC ZRX_HIGH_CM_DC ZTX_LINK_DETECT TRefclk-Tx-Variability LD+/D-RX-Skew TCLK_DET TCLK_FREQ_DET BERLane TXEQ-error QPI_CMP[0] Notes:
1,000,000
10 k 10 k 500
2000 500 0.03 20K
psec UI UI Reference Clock Cycles Events
32
1.0E-14
-10 20.79
0 21
10 21.21
% of VO
3
1. Indicates the output impedance of the transmitter during initialization when the transmitter is OFF, that is, the output driver is disconnected and only the minimum termination is connected. The link detection resistor is assumed not connected when specifying this parameter. 2. Used during initialization. It is the state of OFF condition for the receiver when only the minimum termination is connected. 3. COMP resistance must be provided on the system board with 1% resistors. QPI_CMP[0] resistors are to VSS.
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Datasheet, Volume 1
Table 2-18. Parameter Values for Intel QuickPath Interconnect (Intel QPI) Channel at 6.4 GT/s1
Symbol
Parameter
DC resistance of Tx terminations at half the single ended swing (which is usually 0.25*VTxdiff-pp-pin) bias point DC resistance of Rx terminations at half the single ended swing (which is usually 0.25*VTxdiff-pp-pin) bias point Transmitter Differential swing Transmitter output DC common mode, defined as average of VD+ and VDTransmitter output AC common mode, defined as ((VD+ + VD)/2 VTX-cm-dc-pin). Average of UI-UI jitter UI-UI jitter measured at Tx output pins with 1E-7 probability UI-UI jitter measured at Tx output pins with 1E-9 probability P-p accumulated jitter out of any Tx data or clock over 0 n N UI where N=12, measured with 1E-7 probability. P-p accumulated jitter out of any Tx data or clock over 0 n N UI where N=12, measured with 1E9 probability. Delay of any data lane relative to clock lane, as measured at Tx output (UI) Delay of any data lane relative to the clock lane, as measured at the end of Tx+Channel. This parameter is a collective sum of effects of data clock mismatches in Tx and on the medium connecting Tx and Rx. (UI). DC common mode ranges at the Rx input for any data or clock channel, defined as average of VD+ and VD- (mV) AC common mode ranges at the Rx input for any data or clock channel, defined as ((VD+ + VD-)/2 VRX-cm-dc-pin). Measured timing margin during receiver margining with any receiver equalizer off Measured voltage margin during receiver margining with receiver equalizer off Measured timing margin during receiver margining with receiver equalizer on and at the optimum setting that maximizes the timing margin Measured voltage margin during receiver margining with receiver equalizer on and at the optimum setting that maximizes the voltage margin
Min 38
Nom
Max 52
Unit ohms
Notes
ZTX_LOW_CM_DC ZRX_LOW_CM_DC VTx-diff-pp-pin VTx-cm-dc-pin VTx-cm-ac-pin TXduty-pin TXjitUI-UI-1E-7pin TXjitUI-UI-1E-9pin TXclk-acc-jit-N_UI-1E-7 TXclk-acc-jit-N_UI-1E-9 TTx-data-clk-skew-pin
38 800 0.23 0.0375 -0.05 -0.07 -0.075 0
52 1400 27 0.0375 0.05 0.07 0.075 0.18
ohms mV Fraction of VTX-diff-pp-pin Fraction of VTX-diff-pp-pin UI UI UI UI
0 -0.5
0.2 0.5
UI UI
TRx-data-clk-skew-pin
-1
UI
VRx-cm-dc-pin VRx-cm-ac-pin
TRx-margin VRx-margin
90
350
mV
50 0.1 40
50
mV UI mV
TRx-margin-RxEQ
0.12
UI
VRx-margin-RxEQ Notes:
50
mV
1. It is expected that the receiver will have equalization, which will boost received voltage and mitigate timing jitter, with the minimum level of swing specified. Platform electrical design should determine the optimum level of equalization necessary, depending on the link.
Datasheet, Volume 1
33
34
Datasheet, Volume 1
Package Mechanical Specifications

The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard using an LGA1366 socket. The package consists of a processor mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor thermal solutions, such as a heatsink. Figure 3-1 shows a sketch of the processor package components and how they are assembled together. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for complete details on the LGA1366 socket. The package components shown in Figure 3-1 include the following: Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) Processor core (die) Package substrate Capacitors
Figure 3-1.
Processor Package Assembly Sketch
IHS Substrate
Die
TIM
Capacitors LGA1366 Socket LGA System Board

Note: 1. Socket and motherboard are included for reference and are not part of the processor package.
3.1
Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: Package reference with tolerances (total height, length, width, etc.) IHS parallelism and tilt Land dimensions Top-side and back-side component keep-out dimensions Reference datums All drawing dimensions are in mm. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
Datasheet, Volume 1
35
Figure 3-2.
36
8
DWG. NO
7
D76126
SHT.
6
1
REV
H
B 1 G 1 C 1 C 3 D SEE DETAIL E
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
SEE DETAIL
SEE DETAIL B
C
H 1
G
C 4
SEE DETAIL B
C 2
B 2
G 2
H 2
SEE DETAIL B
2
E
PIN 1
BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
E
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 J 1 SYMBOL
IHS LID
PIN 1
MILLIMETERS
COMMENTS
SEE DETAIL B
MIN B B 1 2 C 1 44.93 42.43 38.9 C 2 36.4
MAX 45.07 42.57 39.1 36.6 1 C E 1 C D
Processor Package Drawing (Sheet 1 of 2)
D
0.203
D
M 2 4X RM 1
C 3 C 4 F F 2 4 G 1 2.2 2.2 4.377 2.498 2.3 2.3 4.757 2.896 42.672 BASIC
SECTION
A-A
SEE DETAIL
IHS LID 0.05 0.203 C
C
IHS SEALANT 0.203 C 0.08
PACKAGE SUBSTRATE
M 3
G 2 H 1 DETAIL SCALE 20:1
40.64 BASIC 21.336 BASIC
C C
DETAIL B SUBSTRATE ALIGNMENT FIDUCIAL X5 SCALE 35:1
H 2 J J 1 20.32 BASIC 1.016 BASIC 2 1.016 BASIC
0.203 0.071
C D E C
F 0.02 4
M 1 M 2 M 3
0.19 0.88 0.53
0.23 0.96 0.61
B
F
DATE
DEPARTMENT
DETAIL SCALE 20:1
DATE DATE
2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119
DESIGNED BY UNLESS OTHERWISE SPECIFIED INTERPRET DIMENSIONS AND TOLERANCES IN ACCORDANCE WITH ASME Y14.5M-1994 DRAWN BY DIMENSIONS ARE IN MILLIMETERS ALL UNTOLERANCED LINEAR DIMENSIONS 0 CHECKED BY ANGLES 0.5 TITLE
THIRD ANGLE PROJECTION

APPROVED BY MATERIAL DATE FINISH SIZE
EMTS DRAWING A1
SCALE: DRAWING NUMBER
D76126
2:1
DO NOT SCALE DRAWING
SHEET
REV
1 OF 2
7 7 6 5 4 3 2 1
Datasheet, Volume 1
8
Figure 3-3.
Datasheet, Volume 1
8
DWG. NO
7
D76126
SHT.
REV
H
SEE DETAIL V 2 C E T 1
THIS DRAWING CONTAINS INTEL CORPORATION CONFIDENTIAL INFORMATION. IT IS DISCLOSED IN CONFIDENCE AND ITS CONTENTS MAY NOT BE DISCLOSED, REPRODUCED, DISPLAYED OR MODIFIED, WITHOUT THE PRIOR WRITTEN CONSENT OF INTEL CORPORATION.
H D
H
2X 39
F
2X 36.5 14.4
4X SURFACE TEST PAD AREA
7.2
Processor Package Drawing (Sheet 2 of 2)
BA AY AW AV AU AT AR AP AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 9.455 18.91 T 2
V 1 G 1.06 MAX COMPONENT HEIGHT
0.23 C H E M N M N H
SEE DETAIL
E C
C
E R 2 DETAIL SCALE 15:1
SYMBOL R 1 R 2
MILLIMETERS MIN R1.09 R1.09 T 1 T V V 2 1 0.2 11.7 0.2 MAX
COMMENTS ------
B
G
R 1
J 0.23 C H G J K DETAIL SCALE 15:1
11.7
--
DEPARTMENT
R
2200 MISSION COLLEGE BLVD. P.O. BOX 58119 SANTA CLARA, CA 95052-8119
A1 8 7 6 5 4 3 2 1
SIZE
DRAWING NUMBER
D76126
SCALE: 2:1
REV
7
DO NOT SCALE DRAWING
SHEET 2 OF
A
2
37
3.2
Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the top-side or land-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.
3.3
Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution.
Table 3-1.
Processor Loading Specifications

Parameter Static Compressive Load Dynamic Compressive Load Maximum 934 N [210 lbf] 1834 N [410 lbf] [max static compressive + dynamic load] Notes 1, 2, 3 1, 3, 4
Notes: 1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS. 2. This is the minimum and maximum static force that can be applied by the heatsink and retention solution to maintain the heatsink and processor interface. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.
3.4
Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.
Table 3-2.
Package Handling Guidelines

Parameter Shear Tensile Torque Maximum Recommended 70 lbs 25 lbs 35 in.lbs Notes -
3.5
Package Insertion Specifications

The processor can be inserted into and removed from an LGA1366 socket 15 times. The socket should meet the LGA1366 requirements detailed in the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
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Datasheet, Volume 1
3.6
Processor Mass Specification

The typical mass of the processor is 35g. This mass [weight] includes all the components that are included in the package.
3.7
Table 3-3.
Processor Materials
Table 3-3 lists some of the package components and associated materials. Processor Materials
Component Integrated Heat Spreader (IHS) Substrate Substrate Lands Material Nickel Plated Copper Fiber Reinforced Resin Gold Plated Copper
3.8
Processor Markings
Figure 3-4 shows the top-side markings on the processor. This diagram is to aid in the identification of the processor.
Figure 3-4.
Processor Top-side Markings
INTEL M '07 PROC# BRAND SLxxx [COO] SPEED/CACHE/INTC/FMB [FPO] e4
Datasheet, Volume 1
S/N
39
3.9
Processor Land Coordinates

Figure 3-5 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands.
Figure 3-5.
Processor Land Coordinates and Quadrants, Top View
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Datasheet, Volume 1
Land Listing
Land Listing
This chapter provides sorted land lists in Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor lands ordered alphabetically by land name. Table 4-2 is a listing of all processor lands ordered by land number.
Table 4-1. Land Listing by Land Name (Sheet 1 of 29)

Land Name BCLK_DN BCLK_DP BCLK_ITP_DN BCLK_ITP_DP BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] CAT_ERR# COMP0 DBR# DDR_COMP[0] DDR_COMP[1] DDR_COMP[2] DDR_VREF DDR0_BA[0] DDR0_BA[1] DDR0_BA[2] DDR0_CAS# DDR0_CKE[0] DDR0_CKE[1] DDR0_CKE[2] DDR0_CKE[3] DDR0_CLK_N[0] DDR0_CLK_N[1] DDR0_CLK_N[2] DDR0_CLK_N[3] DDR0_CLK_P[0] DDR0_CLK_P[1] DDR0_CLK_P[2] DDR0_CLK_P[3] DDR0_CS#[0] DDR0_CS#[1] DDR0_CS#[4] Land No. AH35 AJ35 AA4 AA5 B3 A5 C2 B4 D1 C3 D2 E2 AC37 AB41 AF10 AA8 Y7 AC1 L23 B16 A16 C28 C12 C29 A30 B30 B31 K19 C19 E18 E19 J19 D19 F18 E20 G15 B10 B15 Buffer Type CMOS CMOS CMOS CMOS GTL GTL GTL GTL GTL GTL GTL GTL GTL Analog Asynch Analog Analog Analog Analog CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CMOS CMOS CMOS I O O O O O O O O O O O O O O O O O O O I Direction I I O O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Land Name DDR0_CS#[5] DDR0_DQ[0] DDR0_DQ[1] DDR0_DQ[2] DDR0_DQ[3] DDR0_DQ[4] DDR0_DQ[5] DDR0_DQ[6] DDR0_DQ[7] DDR0_DQ[8] DDR0_DQ[9] DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[12] DDR0_DQ[13] DDR0_DQ[14] DDR0_DQ[15] DDR0_DQ[16] DDR0_DQ[17] DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[20] DDR0_DQ[21] DDR0_DQ[22] DDR0_DQ[23] DDR0_DQ[24] DDR0_DQ[25] DDR0_DQ[26] DDR0_DQ[27] DDR0_DQ[28] DDR0_DQ[29] DDR0_DQ[30] DDR0_DQ[31] DDR0_DQ[32] DDR0_DQ[33] DDR0_DQ[34] DDR0_DQ[35] DDR0_DQ[36] DDR0_DQ[37] Land No. A7 W41 V41 R43 R42 W40 W42 U41 T42 N41 N43 K42 K43 P42 P41 L43 L42 H41 H43 E42 E43 J42 J41 F43 F42 D40 C41 A38 D37 D41 D42 C38 B38 B5 C4 F1 G3 B6 C6 Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Datasheet, Volume 1
41
Land Listing

Land Name DDR0_DQ[38] DDR0_DQ[39] DDR0_DQ[40] DDR0_DQ[41] DDR0_DQ[42] DDR0_DQ[43] DDR0_DQ[44] DDR0_DQ[45] DDR0_DQ[46] DDR0_DQ[47] DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[50] DDR0_DQ[51] DDR0_DQ[52] DDR0_DQ[53] DDR0_DQ[54] DDR0_DQ[55] DDR0_DQ[56] DDR0_DQ[57] DDR0_DQ[58] DDR0_DQ[59] DDR0_DQ[60] DDR0_DQ[61] DDR0_DQ[62] DDR0_DQ[63] DDR0_DQS_N[0] DDR0_DQS_N[1] DDR0_DQS_N[2] DDR0_DQS_N[3] DDR0_DQS_N[4] DDR0_DQS_N[5] DDR0_DQS_N[6] DDR0_DQS_N[7] DDR0_DQS_P[0] DDR0_DQS_P[1] DDR0_DQS_P[2] DDR0_DQS_P[3] DDR0_DQS_P[4] DDR0_DQS_P[5] DDR0_DQS_P[6] DDR0_DQS_P[7] DDR0_MA[0] DDR0_MA[1] DDR0_MA[10] DDR0_MA[11] DDR0_MA[12] DDR0_MA[13] Land No. F3 F2 H2 H1 L1 M1 G1 H3 L3 L2 N1 N2 T1 T2 M3 N3 R4 T3 U4 V1 Y2 Y3 U1 U3 V4 W4 U43 M41 G41 B40 E4 K3 R3 W1 T43 L41 F41 B39 E3 K2 R2 W2 A20 B21 B19 A26 B26 A10 Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O

Land Name DDR0_MA[14] DDR0_MA[15] DDR0_MA[2] DDR0_MA[3] DDR0_MA[4] DDR0_MA[5] DDR0_MA[6] DDR0_MA[7] DDR0_MA[8] DDR0_MA[9] DDR0_ODT[0] DDR0_ODT[1] DDR0_ODT[2] DDR0_ODT[3] DDR0_RAS# DDR0_RESET# DDR0_WE# DDR1_BA[0] DDR1_BA[1] DDR1_BA[2] DDR1_CAS# DDR1_CKE[0] DDR1_CKE[1] DDR1_CKE[2] DDR1_CKE[3] DDR1_CLK_N[0] DDR1_CLK_N[1] DDR1_CLK_N[2] DDR1_CLK_N[3] DDR1_CLK_P[0] DDR1_CLK_P[1] DDR1_CLK_P[2] DDR1_CLK_P[3] DDR1_CS#[0] DDR1_CS#[1] DDR1_CS#[4] DDR1_CS#[5] DDR1_DQ[0] DDR1_DQ[1] DDR1_DQ[2] DDR1_DQ[3] DDR1_DQ[4] DDR1_DQ[5] DDR1_DQ[6] DDR1_DQ[7] DDR1_DQ[8] DDR1_DQ[9] DDR1_DQ[10] Land No. A28 B29 C23 D24 B23 B24 C24 A25 B25 C26 F12 C9 B11 C7 A15 D32 B13 C18 K13 H27 E14 H28 E27 D27 C27 D21 G20 L18 H19 C21 G19 K18 H18 D12 A8 C17 E10 AA37 AA36 Y35 Y34 AA35 AB36 Y40 Y39 P34 P35 P39 Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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Datasheet, Volume 1
Land Listing

Land Name DDR1_DQ[11] DDR1_DQ[12] DDR1_DQ[13] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[16] DDR1_DQ[17] DDR1_DQ[18] DDR1_DQ[19] DDR1_DQ[20] DDR1_DQ[21] DDR1_DQ[22] DDR1_DQ[23] DDR1_DQ[24] DDR1_DQ[25] DDR1_DQ[26] DDR1_DQ[27] DDR1_DQ[28] DDR1_DQ[29] DDR1_DQ[30] DDR1_DQ[31] DDR1_DQ[32] DDR1_DQ[33] DDR1_DQ[34] DDR1_DQ[35] DDR1_DQ[36] DDR1_DQ[37] DDR1_DQ[38] DDR1_DQ[39] DDR1_DQ[40] DDR1_DQ[41] DDR1_DQ[42] DDR1_DQ[43] DDR1_DQ[44] DDR1_DQ[45] DDR1_DQ[46] DDR1_DQ[47] DDR1_DQ[48] DDR1_DQ[49] DDR1_DQ[50] DDR1_DQ[51] DDR1_DQ[52] DDR1_DQ[53] DDR1_DQ[54] DDR1_DQ[55] DDR1_DQ[56] DDR1_DQ[57] DDR1_DQ[58] Land No. N39 R34 R35 N37 N38 M35 M34 K35 J35 N34 M36 J36 H36 H33 L33 K32 J32 J34 H34 L32 K30 E9 E8 E5 F5 F10 G8 D6 F6 H8 J6 G4 H4 G9 H9 G5 J5 K4 K5 R5 T5 J4 M6 R8 R7 W6 W7 Y10 Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Land Name DDR1_DQ[59] DDR1_DQ[60] DDR1_DQ[61] DDR1_DQ[62] DDR1_DQ[63] DDR1_DQS_N[0] DDR1_DQS_N[1] DDR1_DQS_N[2] DDR1_DQS_N[3] DDR1_DQS_N[4] DDR1_DQS_N[5] DDR1_DQS_N[6] DDR1_DQS_N[7] DDR1_DQS_P[0] DDR1_DQS_P[1] DDR1_DQS_P[2] DDR1_DQS_P[3] DDR1_DQS_P[4] DDR1_DQS_P[5] DDR1_DQS_P[6] DDR1_DQS_P[7] DDR1_MA[0] DDR1_MA[1] DDR1_MA[2] DDR1_MA[3] DDR1_MA[4] DDR1_MA[5] DDR1_MA[6] DDR1_MA[7] DDR1_MA[8] DDR1_MA[9] DDR1_MA[10] DDR1_MA[11] DDR1_MA[12] DDR1_MA[13] DDR1_MA[14] DDR1_MA[15] DDR1_ODT[0] DDR1_ODT[1] DDR1_ODT[2] DDR1_ODT[3] DDR1_RAS# DDR1_RESET# DDR1_WE# DDR2_BA[0] DDR2_BA[1] DDR2_BA[2] DDR2_CAS# Land No. W10 V9 W5 AA7 W9 Y37 R37 L36 L31 D7 G6 L5 Y9 Y38 R38 L35 L30 E7 H6 L6 Y8 J14 J16 J17 L28 K28 F22 J27 D22 E22 G24 H14 E23 E24 B14 H26 F26 D11 C8 D14 F11 G14 D29 G13 A17 F17 L26 F16 Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O O O O O O O
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Land Name DDR2_CKE[0] DDR2_CKE[1] DDR2_CKE[2] DDR2_CKE[3] DDR2_CLK_N[0] DDR2_CLK_N[1] DDR2_CLK_N[2] DDR2_CLK_N[3] DDR2_CLK_P[0] DDR2_CLK_P[1] DDR2_CLK_P[2] DDR2_CLK_P[3] DDR2_CS#[0] DDR2_CS#[1] DDR2_CS#[4] DDR2_CS#[5] DDR2_DQ[0] DDR2_DQ[1] DDR2_DQ[2] DDR2_DQ[3] DDR2_DQ[4] DDR2_DQ[5] DDR2_DQ[6] DDR2_DQ[7] DDR2_DQ[8] DDR2_DQ[9] DDR2_DQ[10] DDR2_DQ[11] DDR2_DQ[12] DDR2_DQ[13] DDR2_DQ[14] DDR2_DQ[15] DDR2_DQ[16] DDR2_DQ[17] DDR2_DQ[18] DDR2_DQ[19] DDR2_DQ[20] DDR2_DQ[21] DDR2_DQ[22] DDR2_DQ[23] DDR2_DQ[24] DDR2_DQ[25] DDR2_DQ[26] DDR2_DQ[27] DDR2_DQ[28] DDR2_DQ[29] DDR2_DQ[30] DDR2_DQ[31] Land No. J26 G26 D26 L27 J21 K20 G21 L21 J22 L20 H21 L22 G16 K14 E17 D9 W34 W35 V36 U36 U34 V34 V37 V38 U38 U39 R39 T36 W39 V39 T41 R40 M39 M40 J40 J39 P40 N36 L40 K38 G40 F40 J37 H37 H39 G39 F38 E38 Buffer Type CMOS CMOS CMOS CMOS CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CLOCK CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction O O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

Land Name DDR2_DQ[32] DDR2_DQ[33] DDR2_DQ[34] DDR2_DQ[35] DDR2_DQ[36] DDR2_DQ[37] DDR2_DQ[38] DDR2_DQ[39] DDR2_DQ[40] DDR2_DQ[41] DDR2_DQ[42] DDR2_DQ[43] DDR2_DQ[44] DDR2_DQ[45] DDR2_DQ[46] DDR2_DQ[47] DDR2_DQ[48] DDR2_DQ[49] DDR2_DQ[50] DDR2_DQ[51] DDR2_DQ[52] DDR2_DQ[53] DDR2_DQ[54] DDR2_DQ[55] DDR2_DQ[56] DDR2_DQ[57] DDR2_DQ[58] DDR2_DQ[59] DDR2_DQ[60] DDR2_DQ[61] DDR2_DQ[62] DDR2_DQ[63] DDR2_DQS_N[0] DDR2_DQS_N[1] DDR2_DQS_N[2] DDR2_DQS_N[3] DDR2_DQS_N[4] DDR2_DQS_N[5] DDR2_DQS_N[6] DDR2_DQS_N[7] DDR2_DQS_P[0] DDR2_DQS_P[1] DDR2_DQS_P[2] DDR2_DQS_P[3] DDR2_DQS_P[4] DDR2_DQS_P[5] DDR2_DQS_P[6] DDR2_DQS_P[7] Land No. K12 J12 H13 L13 G11 G10 H12 L12 L10 K10 M9 N9 L11 M10 L8 M8 P7 N6 P9 P10 N8 N7 R10 R9 U5 U6 T10 U10 T6 T7 V8 U9 W36 T38 K39 E40 J9 K7 P5 T8 W37 T37 K40 E39 J10 L7 P6 U8 Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
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Land Name DDR2_MA[0] DDR2_MA[1] DDR2_MA[2] DDR2_MA[3] DDR2_MA[4] DDR2_MA[5] DDR2_MA[6] DDR2_MA[7] DDR2_MA[8] DDR2_MA[9] DDR2_MA[10] DDR2_MA[11] DDR2_MA[12] DDR2_MA[13] DDR2_MA[14] DDR2_MA[15] DDR2_ODT[0] DDR2_ODT[1] DDR2_ODT[2] DDR2_ODT[3] DDR2_RAS# DDR2_RESET# DDR2_WE# FC_AH5 ISENSE PECI PRDY# PREQ# PROCHOT# PSI# QPI_CLKRX_DN QPI_CLKRX_DP QPI_CLKTX_DN QPI_CLKTX_DP QPI_CMP[0] QPI_DRX_DN[0] QPI_DRX_DN[1] QPI_DRX_DN[2] QPI_DRX_DN[3] QPI_DRX_DN[4] QPI_DRX_DN[5] QPI_DRX_DN[6] QPI_DRX_DN[7] QPI_DRX_DN[8] QPI_DRX_DN[9] QPI_DRX_DN[10] QPI_DRX_DN[11] QPI_DRX_DN[12] Land No. A18 K17 G18 J20 F20 K23 K22 J24 L25 H22 H17 H23 G23 F15 H24 G25 L16 F13 D15 D10 D17 E32 C16 AH5 AK8 AH36 B41 C42 AG35 AP7 AR42 AR41 AF42 AG42 AL43 AU37 AV38 AV37 AY36 BA37 AW38 AY38 AT39 AV40 AU41 AT42 AR43 AR40 Analog Asynch GTL GTL GTL CMOS QPI QPI QPI QPI Analog QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI I I I I I I I I I I I I I I I/O O I I/O O I I O O Buffer Type CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Direction O O O O O O O O O O O O O O O O O O O O O O O

Land Name QPI_DRX_DN[13] QPI_DRX_DN[14] QPI_DRX_DN[15] QPI_DRX_DN[16] QPI_DRX_DN[17] QPI_DRX_DN[18] QPI_DRX_DN[19] QPI_DRX_DP[0] QPI_DRX_DP[1] QPI_DRX_DP[2] QPI_DRX_DP[3] QPI_DRX_DP[4] QPI_DRX_DP[5] QPI_DRX_DP[6] QPI_DRX_DP[7] QPI_DRX_DP[8] QPI_DRX_DP[9] QPI_DRX_DP[10] QPI_DRX_DP[11] QPI_DRX_DP[12] QPI_DRX_DP[13] QPI_DRX_DP[14] QPI_DRX_DP[15] QPI_DRX_DP[16] QPI_DRX_DP[17] QPI_DRX_DP[18] QPI_DRX_DP[19] QPI_DTX_DN[0] QPI_DTX_DN[1] QPI_DTX_DN[2] QPI_DTX_DN[3] QPI_DTX_DN[4] QPI_DTX_DN[5] QPI_DTX_DN[6] QPI_DTX_DN[7] QPI_DTX_DN[8] QPI_DTX_DN[9] QPI_DTX_DN[10] QPI_DTX_DN[11] QPI_DTX_DN[12] QPI_DTX_DN[13] QPI_DTX_DN[14] QPI_DTX_DN[15] QPI_DTX_DN[16] QPI_DTX_DN[17] QPI_DTX_DN[18] QPI_DTX_DN[19] QPI_DTX_DP[0] Land No. AN42 AM43 AM40 AM41 AP40 AP39 AR38 AT37 AU38 AV36 AW36 BA36 AW37 BA38 AU39 AW40 AU40 AU42 AT43 AT40 AP42 AN43 AN40 AM42 AP41 AN39 AP38 AH38 AG39 AK38 AJ39 AJ40 AK41 AH42 AJ42 AH43 AG41 AE43 AE41 AC42 AB43 AD39 AC40 AC38 AB38 AE38 AF40 AG38 Buffer Type QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI Direction I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O O O O O O O O O O O O O O O O O
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Land Name QPI_DTX_DP[1] QPI_DTX_DP[2] QPI_DTX_DP[3] QPI_DTX_DP[4] QPI_DTX_DP[5] QPI_DTX_DP[6] QPI_DTX_DP[7] QPI_DTX_DP[8] QPI_DTX_DP[9] QPI_DTX_DP[10] QPI_DTX_DP[11] QPI_DTX_DP[12] QPI_DTX_DP[13] QPI_DTX_DP[14] QPI_DTX_DP[15] QPI_DTX_DP[16] QPI_DTX_DP[17] QPI_DTX_DP[18] QPI_DTX_DP[19] RESET# RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Land No. AF39 AK37 AJ38 AH40 AK40 AH41 AK42 AJ43 AG40 AF43 AE42 AD42 AC43 AD40 AC41 AC39 AB39 AD38 AE40 AL39 D35 D34 C36 A36 F32 C33 C37 A37 B34 C34 G34 G33 D36 F36 E33 G36 E37 F37 E34 G35 G30 G29 H32 F33 E29 E30 J31 J30 Buffer Type QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI QPI Asynch Direction O O O O O O O O O O O O O O O O O O O I

Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Land No. F31 F30 AB5 C13 B9 C11 B8 M43 G43 C39 D4 J1 P1 V3 B35 V42 N42 H42 D39 D5 J2 P2 V2 B36 V43 B20 D25 B28 A27 E15 E13 C14 E12 P37 E35 K37 K33 F7 J7 M4 Y5 AA41 P36 L37 K34 F8 H7 M5 Buffer Type Direction
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Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Land No. Y4 F35 AA40 D20 C22 E25 F25 D16 H16 L17 J15 T40 L38 G38 J11 K8 P4 V7 G31 T35 U40 M38 H38 H11 K9 N4 V6 H31 U35 B18 F21 J25 F23 A31 A40 AB3 AB6 AC3 AC4 AC6 AC8 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Buffer Type Direction

Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Land No. AD8 AE1 AE3 AE4 AE5 AE6 AF1 AF2 AF3 AF4 AF6 AG1 AG2 AG4 AG5 AG6 AG7 AG8 AH2 AH3 AH4 AH6 AH8 AJ1 AJ2 AJ3 AJ37 AJ4 AJ6 AJ7 AJ8 AK1 AK2 AK35 AK36 AK4 AK5 AK6 AL3 AL38 AL4 AL40 AL41 AL5 AL6 AL8 AM1 AM2 Buffer Type Direction
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Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD Land No. AM3 AM36 AM38 AM4 AM6 AM7 AM8 AN1 AN2 AN36 AN38 AN4 AN5 AN6 AP2 AP3 AP4 AR1 AR36 AR37 AR4 AR5 AR6 AT1 AT2 AT3 AT36 AT4 AT5 AT6 AU2 AU3 AU4 AU6 AU7 AU8 AV1 AV2 AV35 AV42 AV43 AV5 AV7 AV8 AW2 AW3 AW39 AW4 Buffer Type Direction

Land Name RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD SKTOCC# TCK TDI TDO THERMTRIP# TMS TRST# VCC VCC VCC Land No. AW41 AW42 AW5 AW7 AY3 AY35 AY39 AY4 AY40 AY41 AY5 AY6 AY8 B33 BA4 BA40 BA6 BA7 BA8 C31 C32 D30 D31 E28 F27 F28 G28 H29 J29 K15 K24 K25 K27 K29 L15 U11 V11 AK7 AG36 AH10 AJ9 AJ10 AG37 AG10 AH9 AH11 AH33 AJ11 GTL TAP TAP TAP GTL TAP TAP PWR PWR PWR O I I O O I I Buffer Type Direction
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Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land No. AJ33 AK11 AK12 AK13 AK15 AK16 AK18 AK19 AK21 AK24 AK25 AK27 AK28 AK30 AK31 AK33 AL12 AL13 AL15 AL16 AL18 AL19 AL21 AL24 AL25 AL27 AL28 AL30 AL31 AL33 AL34 AM12 AM13 AM15 AM16 AM18 AM19 AM21 AM24 AM25 AM27 AM28 AM30 AM31 AM33 AM34 AN12 AN13 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Direction

Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land No. AN15 AN16 AN18 AN19 AN21 AN24 AN25 AN27 AN28 AN30 AN31 AN33 AN34 AP12 AP13 AP15 AP16 AP18 AP19 AP21 AP24 AP25 AP27 AP28 AP30 AP31 AP33 AP34 AR10 AR12 AR13 AR15 AR16 AR18 AR19 AR21 AR24 AR25 AR27 AR28 AR30 AR31 AR33 AR34 AT10 AT12 AT13 AT15 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Direction
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Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land No. AT16 AT18 AT19 AT21 AT24 AT25 AT27 AT28 AT30 AT31 AT33 AT34 AT9 AU10 AU12 AU13 AU15 AU16 AU18 AU19 AU21 AU24 AU25 AU27 AU28 AU30 AU31 AU33 AU34 AU9 AV10 AV12 AV13 AV15 AV16 AV18 AV19 AV21 AV24 AV25 AV27 AV28 AV30 AV31 AV33 AV34 AV9 AW10 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Direction

Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Land No. AW12 AW13 AW15 AW16 AW18 AW19 AW21 AW24 AW25 AW27 AW28 AW30 AW31 AW33 AW34 AW9 AY10 AY12 AY13 AY15 AY16 AY18 AY19 AY21 AY24 AY25 AY27 AY28 AY30 AY31 AY33 AY34 AY9 BA10 BA12 BA13 BA15 BA16 BA18 BA19 BA24 BA25 BA27 BA28 BA30 BA9 M11 M13 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Direction
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Land Name VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC_SENSE VCCPLL VCCPLL VCCPLL VCCPWRGOOD VDDPWRGOOD VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ Land No. M15 M19 M21 M23 M25 M29 M31 M33 N11 N33 R11 R33 T11 T33 W11 AR9 U33 V33 W33 AR7 AA6 A14 A19 A24 A29 A9 B12 B17 B22 B27 B32 B7 C10 C15 C20 C25 C30 D13 D18 D23 D28 E11 E16 E21 E26 E31 F14 F19 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Analog PWR PWR PWR Asynch Asynch PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR I I Direction

Land Name VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VID[0]/MSID[0] VID[1]/MSID[1] VID[2]/MSID[2] VID[3]/CSC[0] VID[4]/CSC[1] VID[5]/CSC[2] VID[6] VID[7] VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. F24 G17 G22 G27 H15 H20 H25 J18 J23 J28 K16 K21 K26 L14 L19 L24 M17 M27 AL10 AL9 AN9 AM10 AN10 AP9 AP8 AN8 A35 A39 A4 A41 A6 AA3 AA34 AA38 AA39 AA9 AB37 AB4 AB40 AB42 AB7 AC2 AC36 AC5 AC7 AC9 AD11 AD33 Buffer Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O I/O I/O I/O I/O I/O O O Direction
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Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. AD37 AD41 AD43 AE2 AE39 AE7 AF35 AF38 AF41 AF5 AG11 AG3 AG33 AG43 AG9 AH1 AH34 AH37 AH39 AH7 AJ34 AJ36 AJ41 AJ5 AK10 AK14 AK17 AK20 AK22 AK23 AK26 AK29 AK3 AK32 AK34 AK39 AK43 AK9 AL1 AL11 AL14 AL17 AL2 AL20 AL22 AL23 AL26 AL29 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction

Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. AL32 AL35 AL36 AL37 AL42 AL7 AM11 AM14 AM17 AM20 AM22 AM23 AM26 AM29 AM32 AM35 AM37 AM39 AM5 AM9 AN11 AN14 AN17 AN20 AN22 AN23 AN26 AN29 AN3 AN32 AN35 AN37 AN41 AN7 AP1 AP10 AP11 AP14 AP17 AP20 AP22 AP23 AP26 AP29 AP32 AP35 AP36 AP37 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction
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Datasheet, Volume 1
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Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. AP43 AP5 AP6 AR11 AR14 AR17 AR2 AR20 AR22 AR23 AR26 AR29 AR3 AR32 AR35 AR39 AT11 AT14 AT17 AT20 AT22 AT23 AT26 AT29 AT32 AT35 AT38 AT41 AT7 AT8 AU1 AU11 AU14 AU17 AU20 AU22 AU23 AU26 AU29 AU32 AU35 AU36 AU43 AU5 AV11 AV14 AV17 AV20 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction

Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. AV22 AV23 AV26 AV29 AV32 AV39 AV4 AV41 AW1 AW11 AW14 AW17 AW20 AW22 AW23 AW26 AW29 AW32 AW35 AW6 AW8 AY11 AY14 AY17 AY2 AY20 AY22 AY23 AY26 AY29 AY32 AY37 AY42 AY7 B2 B37 B42 BA11 BA14 BA17 BA20 BA26 BA29 BA3 BA35 BA39 BA5 C35 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction
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Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. C40 C43 C5 D3 D33 D38 D43 D8 E1 E36 E41 E6 F29 F34 F39 F4 F9 G12 G2 G32 G37 G42 G7 H10 H30 H35 H40 H5 J13 J3 J33 J38 J43 J8 K1 K11 K31 K36 K41 K6 L29 L34 L39 L4 L9 M12 M14 M16 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction

Land Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Land No. M18 M2 M20 M22 M24 M26 M28 M30 M32 M37 M42 M7 N10 N35 N40 N5 P11 P3 P33 P38 P43 P8 R1 R36 R41 R6 T34 T39 T4 T9 U2 U37 U42 U7 V10 V35 V40 V5 W3 W38 W43 W8 Y1 Y11 Y33 Y36 Y41 Y6 Buffer Type GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Direction
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Land Name VSS_SENSE VSS_SENSE_VTT VTT_SENSE VTT_VID2 VTT_VID3 VTT_VID4 VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTA VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTD VTTPWRGOOD Land No. AR8 AE37 AE36 AV3 AF7 AV6 AD10 AE10 AE11 AE33 AF11 AF33 AF34 AG34 AA10 AA11 AA33 AB10 AB11 AB33 AB34 AB8 AB9 AC10 AC11 AC33 AC34 AC35 AD34 AD35 AD36 AD9 AE34 AE35 AE8 AE9 AF36 AF37 AF8 AF9 AB35 Buffer Type Analog Analog Analog CMOS CMOS CMOS PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Asynch I O O O Direction
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Table 4-2. Land Listing by Land Number (Sheet 1 of 29)

Land No. A4 A5 A6 A7 A8 A9 A10 A14 A15 A16 A17 A18 A19 A20 A24 A25 A26 A27 A28 A29 A30 A31 A35 A36 A37 A38 A39 A40 A41 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 VSS BPM#[1] VSS DDR0_CS#[5] DDR1_CS#[1] VDDQ DDR0_MA[13] VDDQ DDR0_RAS# DDR0_BA[1] DDR2_BA[0] DDR2_MA[0] VDDQ DDR0_MA[0] VDDQ DDR0_MA[7] DDR0_MA[11] RSVD DDR0_MA[14] VDDQ DDR0_CKE[1] RSVD VSS RSVD RSVD DDR0_DQ[26] VSS RSVD VSS VSS BPM#[0] BPM#[3] DDR0_DQ[32] DDR0_DQ[36] VDDQ RSVD RSVD DDR0_CS#[1] DDR0_ODT[2] VDDQ DDR0_WE# DDR1_MA[13] DDR0_CS#[4] DDR0_BA[0] VDDQ RSVD DDR0_MA[10] RSVD CMOS O CMOS CMOS PWR CMOS CMOS CMOS CMOS PWR O O O O O O GND GND GTL GTL CMOS CMOS PWR I/O I/O I/O I/O CMOS GND I/O GND CMOS PWR CMOS O O Pin Name Buffer Type GND GTL GND CMOS CMOS PWR CMOS PWR CMOS CMOS CMOS CMOS PWR CMOS PWR CMOS CMOS O O O O O O O O O O I/O Direction

Land No. B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 BA3 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20 BA24 BA25 BA26 BA27 BA28 BA29 BA30 BA35 VDDQ DDR0_MA[4] DDR0_MA[5] DDR0_MA[8] DDR0_MA[12] VDDQ RSVD DDR0_MA[15] DDR0_CKE[2] DDR0_CKE[3] VDDQ RSVD RSVD RSVD RSVD VSS DDR0_DQ[31] DDR0_DQS_P[3] DDR0_DQS_N[3] PRDY# VSS VSS RSVD VSS RSVD RSVD RSVD VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND GND CMOS CMOS CMOS GTL GND GND I/O I/O I/O O CMOS CMOS CMOS PWR O O O Pin Name DDR0_MA[1] Buffer Type CMOS PWR CMOS CMOS CMOS CMOS PWR O O O O Direction O
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Land No. BA36 BA37 BA38 BA39 BA40 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 D1 Pin Name QPI_DRX_DP[4] QPI_DRX_DN[4] QPI_DRX_DP[6] VSS RSVD BPM#[2] BPM#[5] DDR0_DQ[33] VSS DDR0_DQ[37] DDR0_ODT[3] DDR1_ODT[1] DDR0_ODT[1] VDDQ RSVD DDR0_CAS# RSVD RSVD VDDQ DDR2_WE# DDR1_CS#[4] DDR1_BA[0] DDR0_CLK_N[1] VDDQ DDR1_CLK_P[0] RSVD DDR0_MA[2] DDR0_MA[6] VDDQ DDR0_MA[9] DDR1_CKE[3] DDR0_BA[2] DDR0_CKE[0] VDDQ RSVD RSVD RSVD RSVD VSS RSVD RSVD DDR0_DQ[30] RSVD VSS DDR0_DQ[25] PREQ# VSS BPM#[4] GND CMOS GTL GND GTL I/O I/O I CMOS I/O GND CMOS CMOS PWR CMOS CMOS CMOS CMOS PWR O O O O O O PWR CMOS CMOS CMOS CLOCK PWR CLOCK O O O O O CMOS O GTL GTL CMOS GND CMOS CMOS CMOS CMOS PWR I/O O O O I/O I/O I/O Buffer Type QPI QPI QPI GND Direction I I I

Land No. D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 D42 D43 E1 E2 E3 E4 E5 E6 VSS RSVD RSVD DDR1_DQ[38] DDR1_DQS_N[4] VSS DDR2_CS#[5] DDR2_ODT[3] DDR1_ODT[0] DDR1_CS#[0] VDDQ DDR1_ODT[2] DDR2_ODT[2] RSVD DDR2_RAS# VDDQ DDR0_CLK_P[1] RSVD DDR1_CLK_N[0] DDR1_MA[7] VDDQ DDR0_MA[3] RSVD DDR2_CKE[2] DDR1_CKE[2] VDDQ DDR1_RESET# RSVD RSVD DDR0_RESET# VSS RSVD RSVD RSVD DDR0_DQ[27] VSS RSVD DDR0_DQ[24] DDR0_DQ[28] DDR0_DQ[29] VSS VSS BPM#[7] DDR0_DQS_P[4] DDR0_DQS_N[4] DDR1_DQ[34] VSS CMOS CMOS CMOS GND GND GTL CMOS CMOS CMOS GND I/O I/O I/O I/O I/O I/O I/O CMOS GND I/O CMOS GND O CMOS CMOS PWR CMOS O O O CLOCK CMOS PWR CMOS O O O CMOS PWR CLOCK O O CMOS CMOS GND CMOS CMOS CMOS CMOS PWR CMOS CMOS O O O O O O I/O I/O Pin Name BPM#[6] Buffer Type GTL GND Direction I/O
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Land No. E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26 E27 E28 E29 E30 E31 E32 E33 E34 E35 E36 E37 E38 E39 E40 E41 E42 E43 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 Pin Name DDR1_DQS_P[4] DDR1_DQ[33] DDR1_DQ[32] DDR1_CS#[5] VDDQ RSVD RSVD DDR1_CAS# RSVD VDDQ DDR2_CS#[4] DDR0_CLK_N[2] DDR0_CLK_N[3] DDR0_CLK_P[3] VDDQ DDR1_MA[8] DDR1_MA[11] DDR1_MA[12] RSVD VDDQ DDR1_CKE[1] RSVD RSVD RSVD VDDQ DDR2_RESET# RSVD RSVD RSVD VSS RSVD DDR2_DQ[31] DDR2_DQS_P[3] DDR2_DQS_N[3] VSS DDR0_DQ[18] DDR0_DQ[19] DDR0_DQ[34] DDR0_DQ[39] DDR0_DQ[38] VSS DDR1_DQ[35] DDR1_DQ[39] RSVD RSVD VSS DDR1_DQ[36] DDR1_ODT[3] GND CMOS CMOS I/O O CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND PWR CMOS O PWR CMOS O PWR CMOS CLOCK CLOCK CLOCK PWR CMOS CMOS CMOS O O O O O O O CMOS O Buffer Type CMOS CMOS CMOS CMOS PWR Direction I/O I/O I/O O

Land No. F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 F32 F33 F34 F35 F36 F37 F38 F39 F40 F41 F42 F43 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 Pin Name DDR0_ODT[0] DDR2_ODT[1] VDDQ DDR2_MA[13] DDR2_CAS# DDR2_BA[1] DDR0_CLK_P[2] VDDQ DDR2_MA[4] RSVD DDR1_MA[5] RSVD VDDQ RSVD DDR1_MA[15] RSVD RSVD VSS RSVD RSVD RSVD RSVD VSS RSVD RSVD RSVD DDR2_DQ[30] VSS DDR2_DQ[25] DDR0_DQS_P[2] DDR0_DQ[23] DDR0_DQ[22] DDR0_DQ[44] VSS DDR0_DQ[35] DDR1_DQ[42] DDR1_DQ[46] DDR1_DQS_N[5] VSS DDR1_DQ[37] DDR1_DQ[44] DDR2_DQ[37] DDR2_DQ[36] VSS DDR1_WE# DDR1_RAS# DDR0_CS#[0] DDR2_CS#[0] CMOS GND CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GND GND CMOS O PWR CMOS O Buffer Type CMOS CMOS PWR CMOS CMOS CMOS CLOCK PWR CMOS O O O O O Direction O O
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Land No. G17 G18 G19 G20 G21 G22 G23 G24 G25 G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G41 G42 G43 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 VDDQ DDR2_MA[2] DDR1_CLK_P[1] DDR1_CLK_N[1] DDR2_CLK_N[2] VDDQ DDR2_MA[12] DDR1_MA[9] DDR2_MA[15] DDR2_CKE[1] VDDQ RSVD RSVD RSVD RSVD VSS RSVD RSVD RSVD RSVD VSS RSVD DDR2_DQ[29] DDR2_DQ[24] DDR0_DQS_N[2] VSS RSVD DDR0_DQ[41] DDR0_DQ[40] DDR0_DQ[45] DDR1_DQ[43] VSS DDR1_DQS_P[5] RSVD DDR1_DQ[40] DDR1_DQ[45] VSS RSVD DDR2_DQ[38] DDR2_DQ[34] DDR1_MA[10] VDDQ RSVD DDR2_MA[10] DDR1_CLK_P[3] DDR1_CLK_N[3] VDDQ DDR2_CLK_P[2] CMOS CLOCK CLOCK PWR CLOCK O O O O CMOS CMOS CMOS PWR I/O I/O O CMOS CMOS GND I/O I/O CMOS CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O CMOS CMOS CMOS GND I/O I/O I/O GND GND Pin Name Buffer Type PWR CMOS CLOCK CLOCK CLOCK PWR CMOS CMOS CMOS CMOS PWR O O O O O O O O Direction

Land No. H22 H23 H24 H25 H26 H27 H28 H29 H30 H31 H32 H33 H34 H35 H36 H37 H38 H39 H40 H41 H42 H43 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 J23 J24 J25 J26 Pin Name DDR2_MA[9] DDR2_MA[11] DDR2_MA[14] VDDQ DDR1_MA[14] DDR1_BA[2] DDR1_CKE[0] RSVD VSS RSVD RSVD DDR1_DQ[24] DDR1_DQ[29] VSS DDR1_DQ[23] DDR2_DQ[27] RSVD DDR2_DQ[28] VSS DDR0_DQ[16] RSVD DDR0_DQ[17] RSVD RSVD VSS DDR1_DQ[52] DDR1_DQ[47] DDR1_DQ[41] RSVD VSS DDR2_DQS_N[4] DDR2_DQS_P[4] RSVD DDR2_DQ[33] VSS DDR1_MA[0] RSVD DDR1_MA[1] DDR1_MA[2] VDDQ DDR0_CLK_P[0] DDR2_MA[3] DDR2_CLK_N[0] DDR2_CLK_P[0] VDDQ DDR2_MA[7] RSVD DDR2_CKE[0] CMOS O CMOS CMOS PWR CLOCK CMOS CLOCK CLOCK PWR CMOS O O O O O O O CMOS GND CMOS O I/O GND CMOS CMOS I/O I/O GND CMOS CMOS CMOS I/O I/O I/O CMOS I/O CMOS GND CMOS I/O I/O CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O GND Buffer Type CMOS CMOS CMOS PWR CMOS CMOS CMOS O O O Direction O O O
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Land No. J27 J28 J29 J30 J31 J32 J33 J34 J35 J36 J37 J38 J39 J40 J41 J42 J43 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 K23 K24 K25 K26 K27 K28 K29 K30 K31 VDDQ RSVD RSVD RSVD DDR1_DQ[27] VSS DDR1_DQ[28] DDR1_DQ[19] DDR1_DQ[22] DDR2_DQ[26] VSS DDR2_DQ[19] DDR2_DQ[18] DDR0_DQ[21] DDR0_DQ[20] VSS VSS DDR0_DQS_P[5] DDR0_DQS_N[5] DDR1_DQ[48] DDR1_DQ[49] VSS DDR2_DQS_N[5] RSVD RSVD DDR2_DQ[41] VSS DDR2_DQ[32] DDR1_BA[1] DDR2_CS#[1] RSVD VDDQ DDR2_MA[1] DDR1_CLK_P[2] DDR0_CLK_N[0] DDR2_CLK_N[1] VDDQ DDR2_MA[6] DDR2_MA[5] RSVD RSVD VDDQ RSVD DDR1_MA[4] RSVD DDR1_DQ[31] VSS CMOS GND I/O CMOS O PWR PWR CMOS CLOCK CLOCK CLOCK PWR CMOS CMOS O O O O O O CMOS GND CMOS CMOS CMOS I/O O O I/O CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS GND GND CMOS CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name DDR1_MA[6] Buffer Type CMOS PWR Direction O

Land No. K32 K33 K34 K35 K36 K37 K38 K39 K40 K41 K42 K43 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 L21 L22 L23 L24 L25 L26 L27 L28 L29 L30 L31 L32 L33 L34 L35 L36 RSVD RSVD DDR1_DQ[18] VSS RSVD DDR2_DQ[23] DDR2_DQS_N[2] DDR2_DQS_P[2] VSS DDR0_DQ[10] DDR0_DQ[11] DDR0_DQ[42] DDR0_DQ[47] DDR0_DQ[46] VSS DDR1_DQS_N[6] DDR1_DQS_P[6] DDR2_DQS_P[5] DDR2_DQ[46] VSS DDR2_DQ[40] DDR2_DQ[44] DDR2_DQ[39] DDR2_DQ[35] VDDQ RSVD DDR2_ODT[0] RSVD DDR1_CLK_N[2] VDDQ DDR2_CLK_P[1] DDR2_CLK_N[3] DDR2_CLK_P[3] DDR_VREF VDDQ DDR2_MA[8] DDR2_BA[2] DDR2_CKE[3] DDR1_MA[3] VSS DDR1_DQS_P[3] DDR1_DQS_N[3] DDR1_DQ[30] DDR1_DQ[25] VSS DDR1_DQS_P[2] DDR1_DQS_N[2] CLOCK PWR CLOCK CLOCK CLOCK Analog PWR CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O I/O I/O O O O O O O O I O CMOS O CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS PWR I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CMOS GND I/O Pin Name DDR1_DQ[26] Buffer Type CMOS Direction I/O
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Land No. L37 L38 L39 L40 L41 L42 L43 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 M29 M30 M31 M32 M33 M34 M35 M36 M37 M38 M39 M40 M41 RSVD RSVD VSS DDR2_DQ[22] DDR0_DQS_P[1] DDR0_DQ[15] DDR0_DQ[14] DDR0_DQ[43] VSS DDR0_DQ[52] RSVD RSVD DDR1_DQ[53] VSS DDR2_DQ[47] DDR2_DQ[42] DDR2_DQ[45] VCC VSS VCC VSS VCC VSS VDDQ VSS VCC VSS VCC VSS VCC VSS VCC VSS VDDQ VSS VCC VSS VCC VSS VCC DDR1_DQ[17] DDR1_DQ[16] DDR1_DQ[21] VSS RSVD DDR2_DQ[16] DDR2_DQ[17] DDR0_DQS_N[1] CMOS CMOS CMOS I/O I/O I/O CMOS GND CMOS CMOS CMOS PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR GND PWR CMOS CMOS CMOS GND I/O I/O I/O I/O I/O I/O I/O GND CMOS CMOS CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O I/O Pin Name Buffer Type Direction

Land No. M42 M43 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N33 N34 N35 N36 N37 N38 N39 N40 N41 N42 N43 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P33 P34 P35 P36 P37 P38 P39 P40 P41 P42 P43 R1 R2 VSS RSVD DDR0_DQ[48] DDR0_DQ[49] DDR0_DQ[53] RSVD VSS DDR2_DQ[49] DDR2_DQ[53] DDR2_DQ[52] DDR2_DQ[43] VSS VCC VCC DDR1_DQ[20] VSS DDR2_DQ[21] DDR1_DQ[14] DDR1_DQ[15] DDR1_DQ[11] VSS DDR0_DQ[8] RSVD DDR0_DQ[9] RSVD RSVD VSS RSVD DDR2_DQS_N[6] DDR2_DQS_P[6] DDR2_DQ[48] VSS DDR2_DQ[50] DDR2_DQ[51] VSS VSS DDR1_DQ[8] DDR1_DQ[9] RSVD RSVD VSS DDR1_DQ[10] DDR2_DQ[20] DDR0_DQ[13] DDR0_DQ[12] VSS VSS DDR0_DQS_P[6] GND CMOS CMOS CMOS CMOS GND GND CMOS I/O I/O I/O I/O I/O CMOS CMOS CMOS GND CMOS CMOS GND GND CMOS CMOS I/O I/O I/O I/O I/O I/O I/O GND CMOS I/O GND CMOS CMOS CMOS CMOS GND PWR PWR CMOS GND CMOS CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O CMOS CMOS CMOS I/O I/O I/O Pin Name Buffer Type GND Direction
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Land No. R3 R4 R5 R6 R7 R8 R9 R10 R11 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 T1 T10 T11 T2 T3 T4 T5 T6 T7 T8 T9 T33 T34 T35 T36 T37 T38 T39 T40 T41 T42 T43 U1 U2 U3 U4 U5 U6 Pin Name DDR0_DQS_N[6] DDR0_DQ[54] DDR1_DQ[50] VSS DDR1_DQ[55] DDR1_DQ[54] DDR2_DQ[55] DDR2_DQ[54] VCC VCC DDR1_DQ[12] DDR1_DQ[13] VSS DDR1_DQS_N[1] DDR1_DQS_P[1] DDR2_DQ[10] DDR2_DQ[15] VSS DDR0_DQ[3] DDR0_DQ[2] DDR0_DQ[50] DDR2_DQ[58] VCC DDR0_DQ[51] DDR0_DQ[55] VSS DDR1_DQ[51] DDR2_DQ[60] DDR2_DQ[61] DDR2_DQS_N[7] VSS VCC VSS RSVD DDR2_DQ[11] DDR2_DQS_P[1] DDR2_DQS_N[1] VSS RSVD DDR2_DQ[14] DDR0_DQ[7] DDR0_DQS_P[0] DDR0_DQ[60] VSS DDR0_DQ[61] DDR0_DQ[56] DDR2_DQ[56] DDR2_DQ[57] CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O CMOS CMOS CMOS GND I/O I/O I/O Buffer Type CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS PWR PWR CMOS CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS PWR CMOS CMOS GND CMOS CMOS CMOS CMOS GND PWR GND I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Direction I/O I/O I/O

Land No. U7 U8 U9 U10 U11 U33 U34 U35 U36 U37 U38 U39 U40 U41 U42 U43 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V33 V34 V35 V36 V37 V38 V39 V40 V41 V42 V43 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 VSS DDR2_DQS_P[7] DDR2_DQ[63] DDR2_DQ[59] RSVD VCCPLL DDR2_DQ[4] RSVD DDR2_DQ[3] VSS DDR2_DQ[8] DDR2_DQ[9] RSVD DDR0_DQ[6] VSS DDR0_DQS_N[0] DDR0_DQ[57] RSVD RSVD DDR0_DQ[62] VSS RSVD RSVD DDR2_DQ[62] DDR1_DQ[60] VSS RSVD VCCPLL DDR2_DQ[5] VSS DDR2_DQ[2] DDR2_DQ[6] DDR2_DQ[7] DDR2_DQ[13] VSS DDR0_DQ[1] RSVD RSVD DDR0_DQS_N[7] DDR0_DQS_P[7] VSS DDR0_DQ[63] DDR1_DQ[61] DDR1_DQ[56] DDR1_DQ[57] VSS DDR1_DQ[63] DDR1_DQ[59] CMOS CMOS GND CMOS CMOS CMOS CMOS GND CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O PWR CMOS GND CMOS CMOS CMOS CMOS GND CMOS I/O I/O I/O I/O I/O I/O CMOS CMOS GND I/O I/O CMOS GND I/O CMOS GND CMOS CMOS I/O I/O I/O CMOS GND CMOS CMOS I/O I/O I/O PWR CMOS I/O Pin Name Buffer Type GND CMOS CMOS CMOS I/O I/O I/O Direction
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Land No. W11 W33 W34 W35 W36 W37 W38 W39 W40 W41 W42 W43 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y33 Y34 Y35 Y36 Y37 Y38 Y39 Y40 Y41 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA33 AA34 AA35 AA36 AA37 AA38 AA39 VCC VCCPLL DDR2_DQ[0] DDR2_DQ[1] DDR2_DQS_N[0] DDR2_DQS_P[0] VSS DDR2_DQ[12] DDR0_DQ[4] DDR0_DQ[0] DDR0_DQ[5] VSS VSS DDR0_DQ[58] DDR0_DQ[59] RSVD RSVD VSS DDR_COMP[1] DDR1_DQS_P[7] DDR1_DQS_N[7] DDR1_DQ[58] VSS VSS DDR1_DQ[3] DDR1_DQ[2] VSS DDR1_DQS_N[0] DDR1_DQS_P[0] DDR1_DQ[7] DDR1_DQ[6] VSS VSS BCLK_ITP_DN BCLK_ITP_DP VDDPWRGOOD DDR1_DQ[62] DDR_COMP[0] VSS VTTD VTTD VTTD VSS DDR1_DQ[4] DDR1_DQ[1] DDR1_DQ[0] VSS VSS GND Analog CMOS CMOS CMOS GND GND CMOS CMOS GND CMOS CMOS CMOS CMOS GND GND CMOS CMOS Asynch CMOS Analog GND PWR PWR PWR GND CMOS CMOS CMOS GND GND I/O I/O I/O O O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Pin Name Buffer Type PWR PWR CMOS CMOS CMOS CMOS GND CMOS CMOS CMOS CMOS GND GND CMOS CMOS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Direction

Land No. AA40 AA41 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB40 AB41 AB42 AB43 AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40 AC41 AC42 AC43 AD1 AD2 AD3 AD4 RSVD RSVD RSVD VSS RSVD RSVD VSS VTTD VTTD VTTD VTTD VTTD VTTD VTTPWRGOOD DDR1_DQ[5] VSS QPI_DTX_DN[17] QPI_DTX_DP[17] VSS COMP0 VSS QPI_DTX_DN[13] DDR_COMP[2] VSS RSVD RSVD VSS RSVD VSS RSVD VSS VTTD VTTD VTTD VTTD VTTD VSS CAT_ERR# QPI_DTX_DN[16] QPI_DTX_DP[16] QPI_DTX_DN[15] QPI_DTX_DP[15] QPI_DTX_DN[12] QPI_DTX_DP[13] RSVD RSVD RSVD RSVD GND PWR PWR PWR PWR PWR GND GTL QPI QPI QPI QPI QPI QPI I/O O O O O O O GND GND GND PWR PWR PWR PWR PWR PWR Asynch CMOS GND QPI QPI GND Analog GND QPI Analog GND O O O I I/O GND Pin Name Buffer Type Direction
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Land No. AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE33 AE34 AE35 AE36 AE37 AE38 AE39 AE40 AE41 AE42 AE43 AF1 AF10 AF11 AF2 AF3 AF4 AF5 AF6 RSVD RSVD RSVD RSVD VTTD VTTA VSS VSS VTTD VTTD VTTD VSS QPI_DTX_DP[18] QPI_DTX_DN[14] QPI_DTX_DP[14] VSS QPI_DTX_DP[12] VSS RSVD VSS RSVD RSVD RSVD RSVD VSS VTTD VTTD VTTA VTTA VTTA VTTD VTTD VTT_SENSE VSS_SENSE_VTT QPI_DTX_DN[18] VSS QPI_DTX_DP[19] QPI_DTX_DN[11] QPI_DTX_DP[11] QPI_DTX_DN[10] RSVD DBR# VTTA RSVD RSVD RSVD VSS RSVD GND Asynch PWR I GND PWR PWR PWR PWR PWR PWR PWR Analog Analog QPI GND QPI QPI QPI QPI O O O O O GND PWR PWR GND GND PWR PWR PWR GND QPI QPI QPI GND QPI GND O O O O Pin Name Buffer Type Direction

Land No. AF7 AF8 AF9 AF33 AF34 AF35 AF36 AF37 AF38 AF39 AF40 AF41 AF42 AF43 AG1 AG2 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AG10 AG11 AG33 AG34 AG35 AG36 AG37 AG38 AG39 AG40 AG41 AG42 AG43 AH1 AH2 AH3 AH4 AH5 AH6 AH7 AH8 AH9 AH10 AH11 AH33 VTTD VTTD VTTA VTTA VSS VTTD VTTD VSS QPI_DTX_DP[1] QPI_DTX_DN[19] VSS QPI_CLKTX_DN QPI_DTX_DP[10] RSVD RSVD VSS RSVD RSVD RSVD RSVD RSVD VSS TMS VSS VSS VTTA PROCHOT# SKTOCC# THERMTRIP# QPI_DTX_DP[0] QPI_DTX_DN[1] QPI_DTX_DP[9] QPI_DTX_DN[9] QPI_CLKTX_DP VSS VSS RSVD RSVD RSVD FC_AH5 RSVD VSS RSVD TRST# TCK VCC VCC TAP TAP PWR PWR I I GND GND TAP GND GND PWR GTL GTL GTL QPI QPI QPI QPI QPI GND GND I/O O O O O O O O I GND Pin Name VTT_VID3 Buffer Type CMOS PWR PWR PWR PWR GND PWR PWR GND QPI QPI GND QPI QPI O O O O Direction O
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Land No. AH34 AH35 AH36 AH37 AH38 AH39 AH40 AH41 AH42 AH43 AJ1 AJ2 AJ3 AJ4 AJ5 AJ6 AJ7 AJ8 AJ9 AJ10 AJ11 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ40 AJ41 AJ42 AJ43 AK1 AK2 AK3 AK4 AK5 AK6 AK7 AK8 AK9 AK10 AK11 AK12 AK13 AK14 AK15 AK16 VSS BCLK_DN PECI VSS QPI_DTX_DN[0] VSS QPI_DTX_DP[4] QPI_DTX_DP[6] QPI_DTX_DN[6] QPI_DTX_DN[8] RSVD RSVD RSVD RSVD VSS RSVD RSVD RSVD TDI TDO VCC VCC VSS BCLK_DP VSS RSVD QPI_DTX_DP[3] QPI_DTX_DN[3] QPI_DTX_DN[4] VSS QPI_DTX_DN[7] QPI_DTX_DP[8] RSVD RSVD VSS RSVD RSVD RSVD RSVD ISENSE VSS VSS VCC VCC VCC VSS VCC VCC Analog GND GND PWR PWR PWR GND PWR PWR I GND QPI QPI QPI GND QPI QPI O O O O O TAP TAP PWR PWR GND CMOS GND I I O GND Pin Name Buffer Type GND CMOS Asynch GND QPI GND QPI QPI QPI QPI O O O O O I I/O Direction

Land No. AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AK39 AK40 AK41 AK42 AK43 AL1 AL2 AL3 AL4 AL5 AL6 AL7 AL8 AL9 AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS RSVD RSVD QPI_DTX_DP[2] QPI_DTX_DN[2] VSS QPI_DTX_DP[5] QPI_DTX_DN[5] QPI_DTX_DP[7] VSS VSS VSS RSVD RSVD RSVD RSVD VSS RSVD VID[1]/MSID[1] VID[0]/MSID[0] VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC CMOS CMOS GND PWR PWR GND PWR PWR GND PWR PWR GND PWR I/O I/O GND QPI QPI GND QPI QPI QPI GND GND GND O O O O O Pin Name Buffer Type GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND Direction
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Land No. AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AL37 AL38 AL39 AL40 AL41 AL42 AL43 AM1 AM2 AM3 AM4 AM5 AM6 AM7 AM8 AM9 AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS VSS RSVD RESET# RSVD RSVD VSS QPI_CMP[0] RSVD RSVD RSVD RSVD VSS RSVD RSVD RSVD VSS VID[3]/CSC[0] VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS GND CMOS GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND I/O GND GND Analog Asynch I Pin Name Buffer Type GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND GND GND Direction

Land No. AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 AM40 AM41 AM42 AM43 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 VCC VCC VSS VCC VCC VSS VCC VCC VSS RSVD VSS RSVD VSS QPI_DRX_DN[15] QPI_DRX_DN[16] QPI_DRX_DP[16] QPI_DRX_DN[14] RSVD RSVD VSS RSVD RSVD RSVD VSS VID[7] VID[2]/MSID[2] VID[4]/CSC[1] VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC GND CMOS CMOS CMOS GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR O I/O I/O GND GND QPI QPI QPI QPI I I I I GND Pin Name Buffer Type PWR PWR GND PWR PWR GND PWR PWR GND Direction
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Land No. AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN40 AN41 AN42 AN43 AP1 AP2 AP3 AP4 AP5 AP6 AP7 AP8 AP9 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 VSS VCC VCC VSS RSVD VSS RSVD QPI_DRX_DP[18] QPI_DRX_DP[15] VSS QPI_DRX_DN[13] QPI_DRX_DP[14] VSS RSVD RSVD RSVD VSS VSS PSI# VID[6] VID[5]/CSC[2] VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS GND GND CMOS CMOS CMOS GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND GND O O I/O QPI QPI GND QPI QPI GND I I I I GND Pin Name Buffer Type GND PWR PWR GND Direction

Land No. AP37 AP38 AP39 AP40 AP41 AP42 AP43 AR1 AR2 AR3 AR4 AR5 AR6 AR7 AR8 AR9 AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39 AR40 AR41 VSS QPI_DRX_DP[19] QPI_DRX_DN[18] QPI_DRX_DN[17] QPI_DRX_DP[17] QPI_DRX_DP[13] VSS RSVD VSS VSS RSVD RSVD RSVD VCCPWRGOOD VSS_SENSE VCC_SENSE VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS RSVD RSVD QPI_DRX_DN[19] VSS QPI_DRX_DN[12] QPI_CLKRX_DP QPI GND QPI QPI I I I Asynch Analog Analog PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND I GND GND Pin Name Buffer Type GND QPI QPI QPI QPI QPI GND I I I I I Direction
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Land No. AR42 AR43 AT1 AT2 AT3 AT4 AT5 AT6 AT7 AT8 AT9 AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT40 AT41 AT42 AT43 AU1 AU2 AU3 Pin Name QPI_CLKRX_DN QPI_DRX_DN[11] RSVD RSVD RSVD RSVD RSVD RSVD VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS RSVD QPI_DRX_DP[0] VSS QPI_DRX_DN[7] QPI_DRX_DP[12] VSS QPI_DRX_DN[10] QPI_DRX_DP[11] VSS RSVD RSVD QPI GND QPI QPI GND QPI QPI GND I I I I I GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND Buffer Type QPI QPI Direction I I

Land No. AU4 AU5 AU6 AU7 AU8 AU9 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 AU40 AU41 AU42 AU43 AV1 AV2 AV3 AV4 AV5 AV6 AV7 AV8 RSVD VSS RSVD RSVD RSVD VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VSS QPI_DRX_DN[0] QPI_DRX_DP[1] QPI_DRX_DP[7] QPI_DRX_DP[9] QPI_DRX_DN[9] QPI_DRX_DP[10] VSS RSVD RSVD VTT_VID2 VSS RSVD VTT_VID4 RSVD RSVD CMOS O CMOS GND O PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND GND QPI QPI QPI QPI QPI QPI GND I I I I I I GND Pin Name Buffer Type Direction
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Land No. AV9 AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AV37 AV38 AV39 AV40 AV41 AV42 AV43 AW1 AW2 AW3 AW4 AW5 AW6 AW7 AW8 AW9 AW10 AW11 AW12 AW13 VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC RSVD QPI_DRX_DP[2] QPI_DRX_DN[2] QPI_DRX_DN[1] VSS QPI_DRX_DN[8] VSS RSVD RSVD VSS RSVD RSVD RSVD RSVD VSS RSVD VSS VCC VCC VSS VCC VCC GND PWR PWR GND PWR PWR GND GND QPI QPI QPI GND QPI GND I I I I Pin Name Buffer Type PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR Direction

Land No. AW14 AW15 AW16 AW17 AW18 AW19 AW20 AW21 AW22 AW23 AW24 AW25 AW26 AW27 AW28 AW29 AW30 AW31 AW32 AW33 AW34 AW35 AW36 AW37 AW38 AW39 AW40 AW41 AW42 AY2 AY3 AY4 AY5 AY6 AY7 AY8 AY9 AY10 AY11 AY12 AY13 AY14 AY15 AY16 AY17 AY18 AY19 AY20 VSS VCC VCC VSS VCC VCC VSS VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS QPI_DRX_DP[3] QPI_DRX_DP[5] QPI_DRX_DN[5] RSVD QPI_DRX_DP[8] RSVD RSVD VSS RSVD RSVD RSVD RSVD VSS RSVD VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND GND GND QPI I Pin Name Buffer Type GND PWR PWR GND PWR PWR GND PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR GND QPI QPI QPI I I I Direction
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Land No. AY21 AY22 AY23 AY24 AY25 AY26 AY27 AY28 AY29 AY30 AY31 AY32 AY33 AY34 AY35 AY36 AY37 AY38 AY39 AY40 AY41 AY42 VCC VSS VSS VCC VCC VSS VCC VCC VSS VCC VCC VSS VCC VCC RSVD QPI_DRX_DN[3] VSS QPI_DRX_DN[6] RSVD RSVD RSVD VSS GND QPI GND QPI I I Pin Name Buffer Type PWR GND GND PWR PWR GND PWR PWR GND PWR PWR GND PWR PWR Direction
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5
Table 5-1.
Signal Descriptions
This chapter provides the processor signal definitions. Signal Definitions (Sheet 1 of 4)
Name BCLK_DN BCLK_DP BCLK_ITP_DN BCLK_ITP_DP Type I O Description Differential bus clock input to the processor. Buffered differential bus clock pair to ITP. BPM#[7:0] are breakpoint and performance monitor signals. They are outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. Indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors and other internal unrecoverable error. Since this is an I/O pin, external agents are allowed to assert this pin which will cause the processor to take a machine check exception. Impedance compensation must be terminated on the system board using a precision resistor. Intel QPI received clock is the input clock that corresponds to the received data. Intel QPI forwarded clock sent with the outbound data. Must be terminated on the system board using a precision resistor. QPI_DRX_DN[19:0] and QPI_DRX_DP[19:0] comprise the differential receive data for the QPI port. The inbound 20 lanes are connected to another components outbound direction. QPI_DTX_DN[19:0] and QPIQPI_DTX_DP[19:0] comprise the differential transmit data for the QPI port. The outbound 20 lanes are connected to another components inbound direction. DBR# is used only in systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal. Must be terminated on the system board using precision resistors. Voltage reference for DDR3 Defines the bank which is the destination for the current Activate, Read, Write, or Precharge command. Column Address Strobe. Clock Enable. Differential clocks to the DIMM. All command and control signals are valid on the rising edge of clock. Each signal selects one rank as the target of the command and address. DDR3 Data bits. 1 1 1 1 1 1 Notes
BPM#[7:0]
I/O
CAT_ERR#
I/O
COMP0 QPI_CLKRX_DN QPI_CLKRX_DP QPI_CLKTX_DN QPI_CLKTX_DP QPI_CMP[0] QPI_DRX_DN[19:0] QPI_DRX_DP[19:0] QPI_DTX_DN[19:0] QPI_DTX_DP[19:0]
I I
O O I I I O O
DBR#
DDR_COMP[2:0] DDR_VREF DDR{0/1/2}_BA[2:0] DDR{0/1/2}_CAS# DDR{0/1/2}_CKE[3:0] DDR{0/1/2}_CLK_N[2:0] DDR{0/1/2}_CLK_P[2:0] DDR{0/1/2}_CS[1:0]# DDR{0/1/2}_CS[5:4]# DDR{0/1/2}_DQ[63:0]
I I O O O O O I/O
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Table 5-1.
Signal Definitions (Sheet 2 of 4)

Name Type Description Differential pair, Data Strobe x8. Differential strobes latch data/ECC for each DRAM. Different numbers of strobes are used depending on whether the connected DRAMs are x4 or x8. Driven with edges in center of data, receive edges are aligned with data edges. Selects the Row address for reads and writes, and the column address for activates. Also used to set values for DRAM configuration registers. Enables various combinations of termination resistance in the target and non-target DIMMs when data is read or written Row Address Strobe. Resets DRAMs. Held low on power up, held high during self refresh; otherwise, controlled by configuration register. Write Enable. Current sense from VRD11.1. PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power, and error management. Details regarding the PECI electrical specifications, protocols, and functions can be found in the Platform Environment Control Interface Specification. PRDY# is a processor output used by debug tools to determine processor debug readiness. PREQ# is used by debug tools to request debug operation of the processor. PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. This signal can also be driven to the processor to activate the Thermal Control Circuit. This signal does not have on-die termination and must be terminated on the system board. Processor Power Status Indicator signal. This signal is asserted when maximum possible processor core current consumption is less than 20 A. Assertion of this signal is an indication that the VR controller does not currently need to be able to provide ICC above 20 A, and the VR controller can use this information to move to a more efficient operation point. This signal will de-assert at least 3.3 us before the current consumption will exceed 20 A. The minimum PSI# assertion and de-assertion time is 1 BCLK. Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. Note that some PLL, QPI, and error states are not effected by reset and only VCCPWRGOOD forces them to a known state. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. RESET# must not be kept asserted for more than 10 ms while VCCPWRGOOD is asserted. RESET# must be held de-asserted for at least 1 ms before it is asserted again. RESET# must be held asserted before VCCPWRGOOD is asserted. This signal does not have on-die termination and must be terminated on the system board. RESET# is a common clock signal. SKTOCC# (Socket Occupied) will be pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present. TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the Test Access Port). Notes
DDR{0/1/2}_DQS_N[7:0] DDR{0/1/2}_DQS_P[7:0]
I/O
DDR{0/1/2}_MA[15:0]
DDR{0/1/2}_ODT[3:0] DDR{0/1/2}_RAS# DDR{0/1/2}_RESET# DDR{0/1/2}_WE# ISENSE
O O O O I
1 1 1 1
PECI
I/O
PRDY# PREQ#
O I/O
PROCHOT#
I/O
PSI#
RESET#
SKTOCC#
TCK
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Table 5-1.

Name TDI Type I Description TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. TESTLOW must be connected to ground through a resistor for proper processor operation. Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To further protect the processor, its core voltage (VCC), VTTA VTTD, and VDDQ must be removed following the assertion of THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal may de-assert THERMTRIP#, if the processor junction temperature remains at or above the trip level, THERMTRIP# will again be asserted after RESET# is de-asserted. TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. Power for processor core. VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to the processor core power and ground. They can be used to sense or measure voltage near the silicon. Power for on-die PLL filter. VCCPWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that BCLK, VCC, VCCPLL, VTTA and VTTD supplies are stable and within their specifications. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. VCCPWRGOOD can be driven inactive at any time, but BCLK and power must again be stable before a subsequent rising edge of VCCPWRGOOD. In addition, at the time VCCPWRGOOD is asserted RESET# must be active. The PWRGOOD signal must be supplied to the processor. It should be driven high throughout boundary scan operation. VDDPWRGOOD is an input that indicates the VDDQ power supply is good. The processor requires this signal to be a clean indication that the VDDQ power supply is stable and within specifications. "Clean" implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the VDDQ supply is turned on until it comes within specification. The signals must then transition monotonically to a high state. The PWRGOOD signal must be supplied to the processor. Notes
TDO
TESTLOW
THERMTRIP#
TMS TRST# VCC VCC_SENSE VSS_SENSE VCCPLL
I I I O O I
VCCPWRGOOD
VDDPWRGOOD
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Signal Descriptions
Table 5-1.

Name Type Description VID[7:0] (Voltage ID) are used to support automatic selection of power supply voltages (VCC). Refer to the Voltage Regulator-Down (VRD) 11.1 Design Guidelines for more information. The voltage supply for these signals must be valid before the VR can supply VCC to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals become valid. The VR must supply the voltage that is requested by the signals, or disable itself. VID7 and VID6 should be tied separately to VSS using a 1 k resistor during reset (This value is latched on the rising edge of VTTPWRGOOD). MSID[2:0] MSID[2:0] is used to indicate to the processor whether the platform supports a particular TDP. A processor will only boot if the MSID[2:0] pins are strapped to the appropriate setting on the platform (see Table 2-2 for MSID encodings). In addition, MSID protects the platform by preventing a higher power processor from booting in a platform designed for lower power processors. CSC[2:0] Current Sense Configuration bits, for ISENSE gain setting. See Voltage Regulator-Down (VRD) 11.1 Design Guidelines for gain setting information. This value is latched on the rising edge of VTTPWRGOOD. Power for the analog portion of the integrated memory controller, QPI, and Shared Cache. Power for the digital portion of the integrated memory controller, QPI, and Shared Cache. VTT_VID[2:4] (VTT Voltage ID) are used to support automatic selection of power supply voltages (VTT). Refer to the Voltage Regulator-Down (VRD) 11.1 Design Guidelines for more information. VTT_SENSE and VSS_SENSE_VTT provide an isolated, low impedance connection to the processor VTT voltage and ground. They can be used to sense or measure voltage near the silicon. The processor requires this input signal to be a clean indication that the VTT power supply is stable and within specifications. 'Clean' implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Note that it is not valid for VTTPWRGOOD to be de-asserted while VCCPWRGOOD is asserted. Notes
VID[7:6] VID[5:3]/CSC[2:0] VID[2:0]/MSID[2:0]
I/O
VTTA VTTD
I I
VTT_VID[4:2]
VTT_SENSE VSS_SENSE_VTT
O O
VTTPWRGOOD
Note: 1. DDR{0/1/2} refers to DDR3 Channel 0, DDR3 Channel 1, and DDR3 Channel 2.
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Thermal Specifications
6
6.1
Package Thermal Specifications
The processor requires a thermal solution to maintain temperatures within its operating limits. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. Maintaining the proper thermal environment is key to reliable, long-term system operation. A complete solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor integrated heat spreader (IHS). This chapter provides data necessary for developing a complete thermal solution. For more information on designing a component level thermal solution, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
6.1.1
The processor thermal specification uses the on-die Digital Thermal Sensor (DTS) value reported using the PECI interface for all processor temperature measurements. The DTS is a factory calibrated, analog-to-digital thermal sensor. As a result, it will no longer be necessary to measure the processors case temperature. Consequently, there will be no need for a Thermal Profile specification defining the relationship between the processors TCASE and power dissipation.
Note: Note:
Unless otherwise specified, the term DTS refers to the DTS value returned by from the PECI interface gettemp command. A thermal solution that was verified compliant to the processor case temperature thermal profile at the customer defined boundary conditions is expected to be compliant with this update. No redesign of the thermal solution should be necessary. A fan speed control algorithm that was compliant to the previous thermal requirements is also expected to be compliant with this specification. The fan speed control algorithm can be updated to use the additional information to optimize acoustics. To allow the optimal operation and long-term reliability of Intel processor-based systems, the processor thermal solution must deliver the specified thermal solution performance in response to the DTS sensor value. The thermal solution performance will be measured using a Thermal Test Vehicle (TTV). See Table 6-1 and Figure 6-1 or Figure 6-2 for the TTV thermal profile. See Table 6-4 for the required thermal solution performance table when DTS values are greater than TCONTROL. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. When the DTS value is less than TCONTROL, the thermal solution performance is not defined and the fans may be slowed down. This is unchanged from the prior specification. For more details on thermal solution design, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). The processors implement a methodology for managing processor temperatures, which is intended to support acoustic noise reduction through fan speed control and to assure processor reliability. Selection of the appropriate fan speed is based on the relative temperature data reported by the processors Digital Temperature Sensor (DTS). The
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DTS can be read using the Platform Environment Control Interface (PECI) as described in Section 6.3. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT# (see Section 6.2, Processor Thermal Features). Systems that implement fan speed control must be designed to use this data. Systems that do not alter the fan speed only need to ensure the thermal solution provides the CA that meets the TTV thermal profile specifications. A single integer change in the PECI value corresponds to approximately 1 C change in processor temperature. Although each processors DTS is factory calibrated, the accuracy of the DTS will vary from part to part and may also vary slightly with temperature and voltage. In general, each integer change in PECI should equal a temperature change between 0.9 C and 1.1 C. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that complete thermal solution designs target the Thermal Design Power (TDP), instead of the maximum processor power consumption. The Adaptive Thermal Monitor feature is intended to help protect the processor in the event that an application exceeds the TDP recommendation for a sustained time period. For more details on this feature, refer to Section 6.2. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2). for details on system thermal solution design, thermal profiles and environmental considerations. Table 6-1. Processor Thermal Specifications
Core Frequency Thermal Design Power (W) 130 130 130 130 Idle Power (W) 12 12 12 12 Minimum TTV TCASE (C) 5 5 5 5 Maximum TTV TCASE (C) See Figure 6-1; Table 6-2 See Figure 6-1; Table 6-2 See Figure 6-2; Table 6-3 See Figure 6-2; Table 6-3 Target Psi-ca Using Processor TTV (C/W)5 0.222 0.222 0.222 0.222 Notes
Processor
i7-990X i7-980X i7-980 i7-970
3.46 GHz 3.33 GHz 3.33 GHz 3.20 GHz
1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 6 1, 2, 3, 4, 6
Notes: 1. These values are specified at VCC_MAX for all processor frequencies. Systems must be designed to ensure the processor is not to be subjected to any static VCC and ICC combination wherein VCC exceeds VCC_MAX at specified ICC. Refer to the loadline specifications in Chapter 2. 2. Thermal Design Power (TDP) should be used for processor thermal solution design targets. TDP is not the maximum power that the processor can dissipate. TDP is measured at the TCC activation temperature. 3. These specifications are based on initial silicon characterization. These specifications may be further updated as more characterization data becomes available. 4. Power specifications are defined at all VIDs found in Table 2-1. The processor may be shipped under multiple VIDs for each frequency. 5. Target -ca Using the processor TTV (C/W) is based on a TAMBIENT of 39 C. 6. Processor idle power is specified under the lowest possible idle state: processor package C6 state. Achieving processor package C6 state is not supported by all chipsets. See the Intel X58 Express Chipset Datasheet for more details.
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Figure 6-1.
Intel Core i7-900 Desktop Processor Extreme Edition Series Thermal Profile
70.0
y = 43.2 + 0.19 * P
65.0
60.0 TTV Tcase in C
55.0
50.0
45.0
40.0 0 10 20 30 40 50 60 70 80 90 100 110 120 130

TTV Power (W)
Notes: 1. Refer to Table 6-2 for discrete points that constitute the thermal profile. 2. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system and environmental implementation details. 3. The thermal profile is based on data from the Thermal Test Vehicle (TTV).
Table 6-2.
Intel Core i7-900 Desktop Processor Extreme Edition Series Thermal Profile
Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 TCASE_MAX (C) 43.2 43.6 44.0 44.3 44.7 45.1 45.5 45.9 46.2 46.6 47.0 47.4 47.8 48.1 48.5 48.9 49.3 Power (W) 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 TCASE_MAX (C) 49.7 50.0 50.4 50.8 51.2 51.6 51.9 52.3 52.7 53.1 53.5 53.8 54.2 54.6 55.0 55.4 55.7 Power (W) 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 TCASE_MAX (C) 56.1 56.5 56.9 57.3 57.6 58.0 58.4 58.8 59.2 59.5 59.9 60.3 60.7 61.1 61.4 61.8 Power (W) 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 TCASE_MAX (C) 62.2 62.6 63.0 63.3 63.7 64.1 64.5 64.9 65.2 65.6 66.0 66.4 66.8 67.1 67.5 67.9
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Figure 6-2.
Intel Core i7-900 Desktop Processor Series Thermal Profile
Notes: 1. Refer to Table 6-3 for discrete points that constitute the thermal profile. 2. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for system and environmental implementation details. 3. The thermal profile is based on data from the Thermal Test Vehicle (TTV).
Table 6-3.
Intel Core i7-900 Desktop Processor Series Thermal Profile

Power (W) 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 TCASE_MAX (C) 44.1 44.5 44.9 45.2 45.6 46.0 46.4 46.8 47.1 47.5 47.9 48.3 48.7 49.0 49.4 49.8 50.2 Power (W) 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 TCASE_MAX (C) 50.6 50.9 51.3 51.7 52.1 52.5 52.8 53.2 53.6 54.0 54.4 54.7 55.1 55.5 55.9 56.3 56.6 Power (W) 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 TCASE_MAX (C) 57.0 57.4 57.8 58.2 58.5 58.9 59.3 59.7 60.1 60.4 60.8 61.2 61.6 62.0 62.3 62.7 Power (W) 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 TCASE_MAX (C) 63.1 63.5 63.9 64.2 64.6 65.0 65.4 65.8 66.1 66.5 66.9 67.3 67.7 68.0 68.4 68.8
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6.1.1.1
Specification for Operation Where Digital Thermal Sensor Exceeds TCONTROL

When the DTS value is less than TCONTROL, the fan speed control algorithm can reduce the speed of the thermal solution fan. This remains the same as with the previous guidance for fan speed control. During operation where the DTS value is greater than TCONTROL, the fan speed control algorithm must drive the fan speed to meet or exceed the target thermal solution performance (CA) shown in Table 6-4. The ability to monitor the inlet temperature (TAMBIENT) is required to fully implement the specification as the target CA is explicitly defined for various ambient temperature conditions. See the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on characterizing the fan speed to CA and ambient temperature measurement.
Table 6-4.
Thermal Solution Performance above TCONTROL

TAMBIENT1 43.2 42.0 41.0 40.0 39.0 38.0 37.0 36.0 35.0 34.0 33.0 32.0 31.0 30.0 29.0 28.0 27.0 26.0 25.0 24.0 23.0 22.0 21.0 20.0 19.0 18.0 CA at DTS = TCONTROL2 0.190 0.206 0.219 0.232 0.245 0.258 0.271 0.284 0.297 0.310 0.323 0.336 0.349 0.362 0.375 0.388 0.401 0.414 0.427 0.440 0.453 0.466 0.479 0.492 0.505 0.519 CA at DTS = -13 0.190 0.199 0.207 0.215 0.222 0.230 0.238 0.245 0.253 0.261 0.268 0.276 0.284 0.292 0.299 0.307 0.315 0.322 0.330 0.338 0.345 0.353 0.361 0.368 0.376 0.384
Notes: 1. The ambient temperature is measured at the inlet to the processor thermal solution. 2. This column can be expressed as a function of TAMBIENT by the following equation: YCA = 0.19 + (43.2 TAMBIENT) * 0.013 3. This column can be expressed as a function of TAMBIENT by the following equation: YCA = 0.19 + (43.2 TAMBIENT) * 0.0077
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6.1.2
Thermal Metrology
The minimum and maximum TTV case temperatures (TCASE) are specified in Table 6-1, and Table 6-2 and are measured at the geometric top center of the thermal test vehicle integrated heat spreader (IHS). Figure 6-3 illustrates the location where TCASE temperature measurements should be made. For detailed guidelines on temperature measurement methodology and attaching the thermocouple, refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
Figure 6-3.
Thermal Test Vehicle (TTV) Case Temperature (TCASE) Measurement Location
Notes: 1. Figure is not to scale and is for reference only. 2. B1: Max = 45.07 mm, Min = 44.93 mm. 3. B2: Max = 42.57 mm, Min = 42.43 mm. 4. C1: Max = 39.1 mm, Min = 38.9 mm. 5. C2: Max = 36.6 mm, Min = 36.4 mm. 6. C3: Max = 2.3 mm, Min = 2.2 mm 7. C4: Max = 2.3 mm, Min = 2.2 mm. 8. Refer to the appropriate Thermal and Mechanical Design Guide (see Section 1.2) for instructions on thermocouple installation on the processor TTV package.
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6.2
6.2.1
Processor Thermal Features

Processor Temperature
The processor contains a software readable field in the IA32_TEMPERATURE_TARGET register that contains the minimum temperature at which the TCC will be activated and PROCHOT# will be asserted. The TCC activation temperature is calibrated on a part-bypart basis and normal factory variation may result in the actual TCC activation temperature being higher than the value listed in the register. TCC activation temperatures may change based on processor stepping, frequency or manufacturing efficiencies.
Note:
There is no specified correlation between DTS temperatures and processor case temperatures; therefore it is not possible to use this feature to ensure the processor case temperature meets the Thermal Profile specifications.
6.2.2
Adaptive Thermal Monitor

The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when the processor silicon exceeds the Thermal Control Circuit (TCC) activation temperature. Adaptive Thermal Monitor uses TCC activation to reduce processor power using a combination of methods. The first method (Frequency/VID control, similar to Thermal Monitor 2 (TM2) in previous generation processors) involves the processor reducing its operating frequency (using the core ratio multiplier) and input voltage (using the VID signals). This combination of lower frequency and VID results in a reduction of the processor power consumption. The second method (clock modulation, known as Thermal Monitor 1 (TM1) in previous generation processors) reduces power consumption by modulating (starting and stopping) the internal processor core clocks. The processor intelligently selects the appropriate TCC method to use on a dynamic basis. BIOS is not required to select a specific method (as with previous-generation processors supporting TM1 or TM2). The temperature at which Adaptive Thermal Monitor activates the Thermal Control Circuit is factory calibrated and is not user configurable. Snooping and interrupt processing are performed in the normal manner while the TCC is active. When the TCC activation temperature is reached, the processor will initiate TM2 in attempt to reduce its temperature. If TM2 is unable to reduce the processor temperature, then TM1 will be also be activated. TM1 and TM2 will work together (clocks will be modulated at the lowest frequency ratio) to reduce power dissipation and temperature. With a properly designed and characterized thermal solution, it is anticipated that the TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a TCASE that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for information on designing a compliant thermal solution. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. The following sections provide more details on the different TCC mechanisms used by the processor.
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6.2.2.1
Frequency/VID Control
When the Digital Temperature Sensor (DTS) reaches a value of 0 (DTS temperatures reported using PECI may not equal zero when PROCHOT# is activated, see Section 6.3 for further details), the TCC will be activated and the PROCHOT# signal will be asserted. This indicates the processor temperature has met or exceeded the factory calibrated trip temperature and it will take action to reduce the temperature. Upon activation of the TCC, the processor will stop the core clocks, reduce the core ratio multiplier by 1 ratio and restart the clocks. All processor activity stops during this frequency transition, which occurs within 2 us. Once the clocks have been restarted at the new lower frequency, processor activity resumes while the voltage requested by the VID lines is stepped down to the minimum possible for the particular frequency. Running the processor at the lower frequency and voltage will reduce power consumption and should allow the processor to cool off. If after 1 ms the processor is still too hot (the temperature has not dropped below the TCC activation point, DTS still = 0 and PROCHOT is still active), then a second frequency and voltage transition will take place. This sequence of temperature checking and Frequency/VID reduction will continue until either the minimum frequency has been reached or the processor temperature has dropped below the TCC activation point. If the processor temperature remains above the TCC activation point even after the minimum frequency has been reached, then clock modulation (described below) at that minimum frequency will be initiated. There is no end user software or hardware mechanism to initiate this automated TCC activation behavior. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near the TCC activation temperature. Once the temperature has dropped below the trip temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point using the intermediate VID/frequency points. Transition of the VID code will occur first, to insure proper operation as the frequency is increased. Refer to Table 6-4 for an illustration of this ordering.
Figure 6-4.
Frequency and Voltage Ordering
Temperature
fMAX f1 f2
Frequency
VIDfMAX VIDf1 VIDf2
VID
PROCHOT#
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6.2.2.2
Clock Modulation
Clock modulation is a second method of thermal control available to the processor. Clock modulation is performed by rapidly turning the clocks off and on at a duty cycle that should reduce power dissipation by about 50% (typically a 3050% duty cycle). Clocks often will not be off for more than 32 us when the TCC is active. Cycle times are independent of processor frequency. The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. It is possible for software to initiate clock modulation with configurable duty cycles. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
6.2.2.3
Immediate Transiton to combined TM1 and TM2

As mentioned above, when the TCC is activated, the processor will sequentially step down the ratio multipliers and VIDs in an attempt to reduce the silicon temperature. If the temperature continues to increase and exceeds the TCC activation temperature by approximately 5 C before the lowest ratio/VID combination has been reached, then the processor will immediately transition to the combined TM1/TM2 condition. The processor will remain in this state until the temperature has dropped below the TCC activation point. Once below the TCC activation temperature, TM1 will be discontinued and TM2 will be exited by stepping up to the appropriate ratio/VID state.
6.2.2.4
Critical Temperature Flag

If TM2 is unable to reduce the processor temperature, then TM1 will be also be activated. TM1 and TM2 will then work together to reduce power dissipation and temperature. It is expected that only a catastrophic thermal solution failure would create a situation where both TM1 and TM2 are active. If TM1 and TM2 have both been active for greater than 20 ms and the processor temperature has not dropped below the TCC activation point, then the Critical Temperature Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator of a catastrophic thermal solution failure and that the processor cannot reduce its temperature. Unless immediate action is taken to resolve the failure, the processor will probably reach the Thermtrip temperature (see Section 6.2.3 ) within a short time. To prevent possible permanent silicon damage, Intel recommends removing power from the processor within second of the Critical Temperature Flag being set.
6.2.2.5
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has exceeded its specification. If Adaptive Thermal Monitor is enabled (note that it must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Although the PROCHOT# signal is an output by default, it may be configured as bidirectional. When configured in bi-directional mode, it is either an output indicating the processor has exceeded its TCC activation temperature or it can be driven from an
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external source (such as, a voltage regulator) to activate the TCC. The ability to activate the TCC using PROCHOT# can provide a means for thermal protection of system components. As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or more cores has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC for all cores. TCC activation when PROCHOT# is asserted by the system will result in the processor immediately transitioning to the minimum frequency and corresponding voltage (using Freq/VID control). Clock modulation is not activated in this case. The TCC will remain active until the system de-asserts PROCHOT#. Use of PROCHOT# in bi-directional mode can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power.
6.2.3
THERMTRIP# Signal
Regardless of whether or not Adaptive Thermal Monitor is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in Table 5-1). THERMTRIP# activation is independent of processor activity. The temperature at which THERMTRIP# asserts is not user configurable and is not software visible.
6.3
6.3.1
Platform Environment Control Interface (PECI)

Introduction
The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between the Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal and other information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at the factory to provide a digital representation of relative processor temperature. Instantaneous temperature readings from the DTS are available using the IA32_THERM_STATUS MSR; averaged DTS values are read using the PECI interface. The PECI physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a logic '0' or logic '1'. PECI also includes variable data transfer rate established with every message. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information.
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6.3.1.1
Fan Speed Control with Digital Thermal Sensor

Fan speed control solutions use a value stored in the static variable, TCONTROL. The DTS temperature data that is delivered over PECI (in response to a GetTemp0() command), is compared to this TCONTROL reference. The DTS temperature is reported as a relative value versus an absolute value. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as indicated by PROCHOT#. Therefore, as the temperature approaches TCC activation, the value approaches zero degrees.
6.3.1.2
Processor Thermal Data Sample Rate and Filtering

The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots that inherently leads to more varying temperature readings over short time intervals. To reduce the sample rate requirements on PECI and improve thermal data stability versus time the processor DTS implements an averaging algorithm that filters the incoming data. This filter is expressed mathematically as: PECI(t) = PECI(t1)+1 / (2^^X)*[Temp PECI(t1)] Where: PECI(t) is the new averaged temperature, PECI(t-1) is the previous averaged temperature; Temp is the raw temperature data from the DTS; X is the Thermal Averaging Constant (TAC)
Note:
Only values read using the PECI interface are averaged. Temperature values read using the IA32_THERM_STATUS MSR are not averaged. The Thermal Averaging Constant is a BIOS configurable value that determines the time in milliseconds over which the DTS temperature values are averaged. Short averaging times will make the averaged temperature values respond more quickly to DTS changes. Long averaging times will result in better overall thermal smoothing but also incur a larger time lag between fast DST temperature changes and the value read using PECI. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for further details on the Data Filter and the Thermal Averaging Constant. Within the processor, the DTS converts an analog signal into a digital value representing the temperature relative to TCC activation. The conversions are in integers with each single number change corresponding to approximately 1 C. DTS values reported using the internal processor MSR will be in whole integers. As a result of the averaging function described above, DTS values reported over PECI will include a 6-bit fractional value. Under typical operating conditions, where the temperature is close to TCONTROL, the fractional values may not be of interest. But when the temperature approaches zero, the fractional values can be used to detect the activation of the TCC. An averaged temperature value between 0 and 1 can only occur if the TCC has been activated during the averaging window. As TCC activation time increases, the fractional value will approach zero. Fan control circuits can detect this situation and take appropriate action as determined by the system designers. Of course, fan control chips can also monitor the PROCHOT# pin to detect TCC activation using a dedicated input pin on the package. Further details on how the Thermal Averaging Constant influences the fractional temperature values are available in the Thermal Design Guide.
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6.3.2
6.3.2.1
PECI Specifications
PECI Device Address
The PECI register resides at address 30h.
6.3.2.2
PECI Command Support

The processor supports the PECI commands listed in Table 6-5.
Table 6-5.
Supported PECI Command Functions and Codes

Command Function
Ping()
Code
N/A
Comments
This command targets a valid PECI device address followed by zero Write Length and zero Read Length. Write Length: 1 Read Length: 2 Returns the temperature of the processor in Domain 0
GetTemp0()
01h
6.3.2.3
PECI Fault Handling Requirements

PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification. The PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is known to be unresponsive. Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available using PECI. To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the host controller should take action to protect the system from possible damaging states. If the host controller cannot complete a valid PECI transactions of GetTemp0() with a given PECI device over 3 consecutive failed transactions or a one second maximum specified interval, then it should take appropriate actions to protect the corresponding device and/or other system components from overheating. The host controller may also implement an alert to software in the event of a critical or continuous fault condition.
6.3.2.4
PECI GetTemp0() Error Code Support

The error codes supported for the processor GetTemp() command are listed in Table 6-6.
Table 6-6.
GetTemp0() Error Codes

Error Code 8000h General sensor error Description
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6.4
Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity limits to which the device is exposed to while being stored. The specified storage conditions are for component level prior to board attach (see following notes on post board attach limits). Table 6-7 specifies absolute maximum and minimum storage temperature limits that represent the maximum or minimum device condition beyond which damage, latent or otherwise, may occur. The table also specifies sustained storage temperature, relative humidity, and time-duration limits. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality and reliability may be affected.
Table 6-7.
Storage Condition Ratings

Symbol Parameter The minimum/maximum device storage temperature beyond which damage (latent or otherwise) may occur when subjected to for any length of time. The minimum/maximum device storage temperature for a sustained period of time The maximum device storage relative humidity for a sustained period of time Min Max Notes
Tabs storage
-55 C
125 C
1, 2, 3, 4, 5
Tsustained storage RHsustained storage Timesustained storage
-5 C 0 months
40 C 60% @ 24 C 6 months
1, 2, 3, 4, 5 1, 2, 3, 4, 5 1, 2, 3, 4, 5
Notes: 1. Storage conditions are applicable to storage environments only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. 2. These ratings apply to the Intel component and do not include the tray or packaging. 3. Failure to adhere to this specification can affect the long-term reliability of the processor. 4. Non operating storage limits for post board attach: Storage condition limits for the component, once attached to the application board, are not specified. 5. Device storage temperature qualification methods follow JESD22-A119 (low temp) and JESD22-A103 (high temp) standards.
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Features
7
7.1
Features
Power-On Configuration (POC)
Several configuration options can be configured by hardware. For electrical specifications on these options, refer to Chapter 2. Note that request to execute BIST is not selected by hardware but is passed across the Intel QPI link during initialization. The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a "warm" reset and a power-on reset.
Table 7-1.
Power On Configuration Signal Options

Configuration Option
MSID CSC
Signal
VID[2:0]/MSID[2:0]1, 2 VID[5:3]/CSC[2:0]1, 2
Notes: 1. Latched when VTTPWRGOOD is asserted and all internal power good conditions are met. 2. See the signal definitions in Table 6-1 for the description of MSID and CSC.
7.2
Clock Control and Low Power States

The processor supports low power states at the individual thread, core, and package level for optimal power management. The processor implements software interfaces for requesting low power states: MWAIT instruction extensions with sub-state hints, the HLT instruction (for C1 and C1E) and P_LVLx reads to the ACPI P_BLK register block mapped in the processors I/O address space. The P_LVLx I/O reads are converted to equivalent MWAIT C-state requests inside the processor and do not directly result in I/O reads to the system. The P_LVLx I/O Monitor address does not need to be set up before using the P_LVLx I/O read interface. Software may make C-state requests by using a legacy method involving I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This feature is designed to provide legacy support for operating systems that initiate C-state transitions using access to pre-defined ICH registers. The base P_LVLx register is P_LVL2, corresponding to a C3 request. P_LVL3 is C6. P_LVL2 is defined in the PMG_IO_CAPTURE MSR. P_LVLx is limited to a subset of Cstates. For Example, P_LVL8 is not supported and will not cause an I/O redirection to a C8 request. Instead, it will fall through like a normal I/O instruction. The range of I/O addresses that may be converted into C-state requests is also defined in the PMG_IO_CAPTURE MSR, in the C-state Range field. This field maybe written by BIOS to restrict the range of I/O addresses that are trapped and redirected to MWAIT instructions. Note that when I/O instructions are used, no MWAIT substates can be defined, as therefore the request defaults to have a sub-state or zero, but always assumes the break on IF==0 control that can be selected using ECX with an MWAIT instruction.
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Features
Figure 7-1.
Power State
MWAIT C1, HLT

2
C0
2 2 2
MWAIT C6, I/O C6
MWAIT C1, HLT (C1E enabled)
MWAIT C3, I/O C3
C1
C1E
C3
C6
1. No transition to C0 is needed to service a snoop when in C1 or C1E.
, . 2. Transitions back to C0 occur on an interrupt or on access to monitored address (if state was entered via MWAIT). .
7.2.1
Thread and Core Power State Descriptions

Individual threads may request low power states. Core power states are automatically resolved by the processor as shown in Table 7-2.
Table 7-2.
Coordination of Thread Power States at the Core Level

Core State
C0 Thread0 State C11 C3 C6
Thread1 State C0
C0 C0 C0 C0
C11
C0 C11 C11 C11
C3
C0 C11 C3 C3
C6
C0 C11 C3 C6
Notes: 1. If enabled, state will be C1E.
7.2.1.1
C0 State
This is the normal operating state in the processor.
7.2.1.2
C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or MWAIT(C1E) instruction. The processor thread will transition to the C0 state upon occurrence of an interrupt or an access to the monitored address if the state was entered using the MWAIT instruction. RESET# will cause the processor to initialize itself. A System Management Interrupt (SMI) handler will return execution to either Normal state or the C1 state. See the Intel 64 and IA-32 Architecture Software Developer's Manuals, Volume III: System Programmer's Guide for more information. While in C1/C1E state, the processor will process bus snoops and snoops from the other threads.
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7.2.1.3
C3 State
Individual threads of the processor can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. Before entering core C3, the processor flushes the contents of its caches. Except for the caches, the processor core maintains all its architectural state while in the C3 state. All of the clocks in the processor core are stopped in the C3 state. Because the cores caches are flushed, the processor keeps the core in the C3 state when the processor detects a snoop on the Intel QPI Link or when another logical processor in the same package accesses cacheable memory. The processor core will transition to the C0 state upon occurrence of an interrupt. RESET# will cause the processor core to initialize itself.
7.2.1.4
C6 State
Individual threads of the processor can enter the C6 state by initiating a P_LVL3 read to the P_BLK or an MWAIT(C6) instruction. Before entering Core C6, the processor saves core state data (such as, registers) to the last level cache. This data is retired after exiting core C6. The processor achieves additional power savings in the core C6 state.
7.2.2
Package Power State Descriptions

The package supports C0, C3, and C6 power states. Note that there is no package C1 state. The package power state is automatically resolved by the processor depending on the core power states and permission from the rest of the system as described in the following sections.
7.2.2.1
Package C0 State
This is the normal operating state for the processor. The processor remains in the Normal state when at least one of its cores is in the C0 or C1 state or when another component in the system has not granted permission to the processor to go into a low power state. Individual components of the processor may be in low power states while the package is in C0.
7.2.2.2
Package C1/C1E State

The package will enter the C1/C1E low power state when at least one core is in the C1/C1E state and the rest of the cores are in the C1/C1E or lower power state. The processor will also enter the C1/C1E state when all cores are in a power state lower than C1/C1E but the package low power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR. In the C1E state, the processor will automatically transition to the lowest power operating point (lowest supported voltage and associated frequency). When entering the C1E state, the processor will first switch to the lowest bus ratio and then transition to the lower VID. No notification to the system occurs upon entry to C1/C1E.
7.2.2.3
Package C3 State
The package will enter the C3 low power state when all cores are in the C3 or lower power state and the processor has been granted permission by the other component(s) in the system to enter the C3 state. The package will also enter the C3 state when all cores are in an idle state lower than C3 but other component(s) in the system have only granted permission to enter C3. If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and for processors with an integrated memory controller, the DRAM will be put into selfrefresh.
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7.2.2.4
Package C6 State
The package will enter the C6 low power state when all cores are in the C6 or lower power state and the processor has been granted permission by the other component(s) in the system to enter the C6 state. The package will also enter the C6 state when all cores are in an idle state lower than C6 but the other component(s) have only granted permission to enter C6. If Intel QPI L1 has been granted, the processor will disable some clocks and PLLs and the shared cache will enter a deep sleep state. Additionally, for processors with an integrated memory controller, the DRAM will be put into self-refresh.
7.3
Sleep States
The processor supports the ACPI sleep states S0, S1, S3, and S4/S5 as shown in Table 7-3. For information on ACPI S-states and related terminology, refer to ACPI Specification. The S-state transitions are coordinated by the processor in response PM Request (PMReq) messages from the chipset. The processor itself will never request a particular S-state.
Table 7-3.
Processor S-States
S-State
S0 S1 S3 S4/S5 Notes:
Power Reduction
Normal Code Execution Cores in C1E like state, processor responds with CmpD(S1) message. Memory put into self-refresh, processor responds with CmpD(S3) message. Processor responds with CmpD(S4/S5) message.
Allowed Transitions
S1 (using PMReq) S0 (using reset or PMReq) S3, S4 (using PMReq) S0 (using reset) S0 (using reset)
1.
If the chipset requests an S-state transition, which is not allowed, a machine check error will be generated by the processor.
7.4
ACPI P-States (Intel Turbo Boost Technology)

The processor supports ACPI P-States. A new feature is that the P0 ACPI state will be a request for Turbo Boost Technology. Turbo Boost Technology opportunistically and automatically allows the processor to run faster than its marked frequency if the processor is operating below power, thermal, and current specifications. Maximum turbo frequency is dependant on the processor component and number of active cores. No special hardware support is necessary for Turbo Boost Technology. BIOS and the operating system can enable or disable Turbo Boost Technology.
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7.5
Enhanced Intel SpeedStep Technology

The processor features Enhanced Intel SpeedStep Technology. Following are the key features of Enhanced Intel SpeedStep Technology: Multiple voltage and frequency operating points provide optimal performance at the lowest power. Voltage and frequency selection is software controlled by writing to processor MSRs: If the target frequency is higher than the current frequency, VCC is ramped up in steps by placing new values on the VID pins and the PLL then locks to the new frequency. If the target frequency is lower than the current frequency, the PLL locks to the new frequency and the VCC is changed through the VID pin mechanism. Software transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition completes. The processor controls voltage ramp rates internally to ensure smooth transitions. Low transition latency and large number of transitions possible per second: Processor core (including shared cache) is unavailable for less than 5 s during the frequency transition.
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Boxed Processor Specifications
8
8.1

Introduction
The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators.
Note:
Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets]. Figure 8-1 shows a mechanical representation of a boxed processor. Drawings in this section reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for further guidance. Contact your local Intel Sales Representative for this document. Mechanical Representation of the Boxed Processor
Note:
Figure 8-1.
Note:
The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
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8.2
8.2.1
Mechanical Specifications
Boxed Processor Cooling Solution Dimensions
This section covers the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 8-1 shows a mechanical representation of the boxed processor. Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with assembled fan heatsink are shown in Figure 8-2 (side view), and Figure 8-3 (top view). The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in Figure 8-7 and Figure 8-8. Note that some figures have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.
Figure 8-2.
Space Requirements for the Boxed Processor (side view)
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Datasheet, Volume 1
Figure 8-3.
Space Requirements for the Boxed Processor (top view)
Notes: 1. Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Figure 8-4.
Space Requirements for the Boxed Processor (overall view)
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8.2.2
Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 550 grams. See Chapter 6 and the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2) for details on the processor weight and heatsink requirements.
8.2.3
Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

The boxed processor thermal solution requires a heatsink attach clip assembly to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly.
8.3
8.3.1
Electrical Requirements
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 8-5. Baseboards must provide a matched power header to support the boxed processor. Table 8-1 contains specifications for the input and output signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal that is an open-collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides VOH to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND. The fan heatsink receives a PWM signal from the motherboard from the 4th pin of the connector labeled as CONTROL. The boxed processor's fan heatsink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power header identification and location should be documented in the platform documentation, or on the system board itself. Figure 8-6 shows the location of the fan power connector relative to the processor socket. The baseboard power header should be positioned within 110 mm [4.33 inches] from the center of the processor socket.
Figure 8-5.
Boxed Processor Fan Heatsink Power Cable Connector Description
Pin 1 2 3 4
Signal GND +12 V SENSE CONTROL
Straight square pin, 4-pin terminal housing with polarizing ribs and friction locking ramp. 0.100" pitch, 0.025" square pin width. Match with straight pin, friction lock header on mainboard.
1 2 3 4
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Table 8-1.
Fan Heatsink Power and Signal Specifications

Description +12 V: 12 volt fan power supply IC: - Peak steady-state fan current draw - Average steady-state fan current draw SENSE: SENSE frequency CONTROL Notes: 1. Baseboard should pull this pin up to 5 V with a resistor. 2. Open drain type, pulse width modulated. 3. Fan will have pull-up resistor for this signal to maximum of 5.25 V. 21 2 25 3.0 2.0 28 A A pulses per fan revolution kHz Min 10.8 Typ 12 Max 13.2 Unit V Notes -
1 2, 3
Figure 8-6.
Baseboard Power Header Placement Relative to Processor Socket

R110 [4.33]
8.4
8.4.1
This section describes the cooling requirements of the fan heatsink solution used by the boxed processor.
Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is found in Chapter 6 of this document. The boxed processor fan heatsink is able to keep the processor temperature within the specifications (see Table 6-1) in chassis that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life. Figure 8-7 and Figure 8-8 illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 40 C. Again, meeting the processor's temperature specification is the responsibility of the system integrator.
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Figure 8-7.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (top view)
Figure 8-8.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (side view)
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8.4.2
Variable Speed Fan

If the boxed processor fan heatsink 4-pin connector is connected to a 3-pin motherboard header, it will operate as follows: The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If the internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains cooler than the lower set point. These set points, represented in Figure 8-9 and Table 8-2, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 40 C. Meeting the processor's temperature specification (see Chapter 6) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to Table 8-1 for the specific requirements.
Figure 8-9.
Boxed Processor Fan Heatsink Set Points
Higher Set Point Highest Noise Level
Increasing Fan Speed & Noise
Lowest Noise Level
Z Internal Chassis Temperature (Degrees C)
Table 8-2.
Fan Heatsink Power and Signal Specifications

Boxed Processor Fan Heatsink Set Point (C) X 30 Boxed Processor Fan Speed When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed. Recommended maximum internal chassis temperature for nominal operating environment. When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed. Recommended maximum internal chassis temperature for worst-case operating environment. Notes
Z 40 Notes:
1. Set point variance is approximately 1 C from fan heatsink to fan heatsink.
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If the boxed processor fan heatsink 4-pin connector is connected to a 4-pin motherboard header and the motherboard is designed with a fan speed controller with PWM output (CONTROL see Table 8-1) and remote thermal diode measurement capability, the boxed processor will operate as follows: As processor power has increased, the required thermal solutions have generated increasingly more noise. Intel has added an option to the boxed processor that allows system integrators to have a quieter system in the most common usage. The 4th wire PWM solution provides better control over chassis acoustics. This is achieved by more accurate measurement of processor die temperature through the processor's Digital Thermal Sensors (DTS) and PECI. Fan RPM is modulated through the use of an ASIC located on the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on actual processor temperature instead of internal ambient chassis temperatures. If the new 4-pin active fan heat sink solution is connected to an older 3-pin baseboard processor fan header, it will default back to thermistor controlled. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control, see the appropriate processor Thermal and Mechanical Design Guidelines (see Section 1.2).
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Datasheet, Volume 1

Core I7 900 Ee and Desktop Processor Series 32nm Datasheet Vol 1

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Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series

Date March 2010 July 2010 June 2011

High-Level View of Processor Interfaces

System Memory (DDR3)

Intel QuickPath Interconnect (Intel QPI)

Note: Note: Note:

Active ODT for a Differential Link Example

Power and Ground Lands

VCC, VTTA, VTTD, VDDQ Decoupling

Processor Clocking (BCLK_DP, BCLK_DN)

PLL Power Supply

Voltage Identification (VID)

Voltage Identification Definition (Sheet 1 of 2)

Voltage Identification Definition (Sheet 2 of 2)

Market Segment Selection Truth Table for MS_ID[2:0]

Reserved or Unused Signals

Signal Groups (Sheet 1 of 2)

DDR3 Reference Clocks Differential DDR3 Output DDR{0/1/2}_CLK[D/P][3:0]

Signal Groups (Sheet 2 of 2)

Signals with ODT

Test Access Port (TAP) Connection

Platform Environmental Control Interface (PECI) DC Specifications

PECI DC Electrical Limits

Input Device Hysteresis

Input Device Hysteresis

Absolute Maximum and Minimum Ratings

Processor Absolute Minimum and Maximum Ratings

VTTD VDDQ VCCPLL TCASE TSTORAGE

-0.3 -0.3 See Chapter 6 See Chapter 6

1.8 2.0 See Chapter 6 See Chapter 6

DC Voltage and Current Specification

See Table 2-10 and Figure 2-4

VTTD VDDQ VCCPLL

145 145 145 145 5

ITTD IDDQ IDDQS3 ICC_VCCPLL Notes: 1. 2.

VCC Static and Transient Tolerance

VCC Static and Transient Tolerance Load Lines

VTT Voltage Identification (VID) Definition

Table 2-10. VTT Static and Transient Tolerance 1

VTT Static and Transient Tolerance Load Line

Table 2-11. DDR3 Signal Group DC Specifications

DDR_COMP0 COMP Resistance DDR_COMP1

DDR_COMP2 COMP Resistance

Table 2-12. RESET# Signal DC Specifications

Table 2-13. TAP Signal Group DC Specifications

Table 2-14. PWRGOOD Signal Group DC Specifications

0.75 * VTTA 0.87 10

Table 2-15. Control Sideband Signal Group DC Specifications

VCC Overshoot Specification

Table 2-16. VCC Overshoot Specifications

VCC Overshoot Example Waveform

Example Overshoot Waveform

Die Voltage Validation

Intel QuickPath Interconnect (Intel QPI) Specifications

Table 2-17. Intel QuickPath Interconnect (Intel QPI) Specifications

2000 500 0.03 20K

psec UI UI Reference Clock Cycles Events

38 800 0.23 0.0375 -0.05 -0.07 -0.075 0

52 1400 27 0.0375 0.05 0.07 0.075 0.18

ohms mV Fraction of VTX-diff-pp-pin Fraction of VTX-diff-pp-pin UI UI UI UI

Package Mechanical Specifications

Package Mechanical Specifications