Synthesis Based Introduction to Opamps and Phase Locked Loops

2012 International Symposium on Circuits and Systems Seoul, Korea Nagendra Krishnapura
Department of Electrical Engineering Indian Institute of Technology, Madras Chennai, 600036, India

23 May 2012

Outline

Negative feedback amplier Integrate the error to drive the output Opamp to compute and integrate the error Gm loaded by a capacitorSingle stage opamp Better I-V conversionTwo stage opamp Further renementThree stage opamp PLL as negative feedback frequency multiplier Integrate frequency error to drive the outputType I PLL Static phase error causes reference spurs Additional integrator to null phase errorType II PLL Conclusions

Negative feedback system

desired value

+-

error

controller

output sensor

sensor output

Controller: Continuously changes the input until error goes

to zero

Negative feedback system

desired value

+-

error

dt

output sensor

sensor output

Controller: Continuously changes the input until error goes

to zero

Negative feedback amplier

Vi Vi (k-1)R

Vfb computing the error sensing the output

Vfb

Integrate the error Vi Vo /k to drive the output Opamp computes the error and integrates it

(k-1)R

+-

Ve

u dt

Vo

+ Ve -

+ u Vo

Opamp (integrator) realization

+ Ve

IGm

Vo Ro1 C1

Gm1

Gm C integrator Finite Ro1 Finite dc gain Steady state error

Transimpedance amplier for better I-V conversion

part of IGm(=Vo/Rout) IGm Ro1 Zc smaller part of IGm(=Vx/Rout) Vo-IGmZc IGm Ro1 + Vx + Vo Zc

Use negative feedback to realize a CCVS Vo IGm Zc within the unity loop gain frequency

Improved I-V conversionTwo stage opamp

part of IGm(=Vo/Rout) IGm Ro1 Zc smaller part of IGm(=Vx/Rout) Vo-IGmZc IGm Ro1 + Vx C1 + Gm1 Ro1 IGm + Gm2 Ro2 C2 u + Vo Zc

single stage opamp synthesized earlier Vo

Ve

Intuition about two stage opamp

I-V conversion bandwidth unity loop gain frequency u ,desired < u ,inner Gm2 Gm1 < C C2

Further improvementThree stage opamp

part of IGm(=Vo/Rout) IGm Ro1 Zc smaller part of IGm(=Vx/Rout) Vo-IGmZc IGm Ro1 + Vx u + C1 two stage opamp + Gm1 Ro1 Gm2 Ro2 + Gm3 Ro3 C3 Vout C2 Vo Zc

Ve

IGm

Intuition about three stage opamp

I-V conversion bandwidth unity loop gain frequency u ,desired < u ,inner G G Gm1 < m2 < m3 C C2 C3

Analysis of two and three stage opamps

Two stage opamp DC gain Pole locations, pole splitting Stability constraints RHP zero and its cancellation Three stage opamp DC gain Pole locations Stability constraints Zero pair and their optimization

Frequency multiplication analogous to voltage amplication

frequency error Vi + Ve Vf u dt Vo (k-1)R R fref input + frequency fout/N fe u dt fout output frequency

1/N

Frequency multiplication

frequency difference input signal at fref zero, at steady state frequency measure fref + fout/N frequency measure dt VCO N frequency divider Vctl output signal at fout fout = ffree+KvcoVctl

Integrate frequency difference Phase difference

input signal at fref

fout = ffree+KvcoVctl measure frequency Vctl dt + VCO dt measure phase difference measure frequency N frequency divider output signal at fout

measure phase

measure phase

Type I phase locked loop

fout = ffree+KvcoVctl phase detector Vctl output signal at fout

input signal at fref

VCO N frequency divider

Phase detector and VCO in a loop

Type I phase locked loop

input signal at fref = ref-out/N Kpd phase detector N frequency divider VCO In steady state, Vctl = (fout-ffree)/Kvco Kpd Vctl output signal at fout (fout=Nfref at steady state)

In steady state, = (fout-ffree)/KvcoKpd

Phase offset = (fout ffree )/Kvco Kpd between input and

feedback signals
|| limited to n due to periodic nature of phase Limited lock range |fout ffree |

Tri state phase detector example

Tref +1 reference -1 +1 divider o/p -1 pdout +Vpd -Vpd T = Tref/2 Tref divider o/p reference Tri-state phase detector pdout

Vout (t ) = Vpd

2 Average

sinc
n =1

cos(2 nfref t n/2)

Periodic error at fref

Type I PLL with a practical phase detector

Output average value Periodic signal at fref Periodic signal magnitude proportional to VCO modulated at fref and its harmonics PLL output has sidebands at integer multiples of fref

For a modest sideband level of 40 dB, PLL lock range 104 fref . Cannot change N at all!

Type I phase locked loop

input signal at fref = ref-out/N Kpd phase detector

In steady state, Vctl = (fout-ffree)/Kvco Kpd Vctl VCO N frequency divider

output signal at fout (fout=Nfref at steady state)

In steady state, = (fout-ffree)/KvcoKpd

= 0 if fout happens to be equal to fref . Zero spurs!

Changing the free running frequency of a VCO

Voff Vctl VCO VCO ffree = ffree+KvcoVoff (ffree+KvcoVoff)+KvcoVctl Vctl ffree+KvcoVctl

Add a bias to the input to change the free running

frequency

Slowly change the bias until = 0

monitor and continuously adjust Voff until =0 input signal at fref = ref-out/N Kpd phase detector ffree N frequency divider

+ Voff Kpd VCO

output signal at fout (fout=Nfref at steady state)

Slowly change the bias Voff until = 0

Slowly change the bias until = 0

integral phase detector Kpd,I dt Kpd,I dt In steady state, Voff = (fout-ffree)/KvcoKpd output signal at fout (fout=Nfref at steady state)

input signal at fref = ref-out/N Kpd phase detector

Voff Kpd ffree N frequency divider VCO

In steady state, = 0

Measure and integrate it to control Voff

Type II Phase locked loop

phase detector + loop filter integral phase detector Kpd,I dt Kpd,I dt proportional phase detector Kpd Kpd output signal at fout (fout=Nfref at steady state) VCO In steady state, = 0 N

input signal at fref = ref-out/N

Proportional + integral loop lter

Type II Phase locked loop implementation

output signal at fout (fout=Nfref at steady state) R1 VCO C1 C2

input signal at fref phase detector

Icp UP DN Icp

N frequency divider

Intuition about the Phase locked loop

Reason for using a phase detector for frequency synthesis Reason for an additional integrator in the loop lter Integral path for adjusting Voff slower than the main

path (type I)
PLL bandwidth (unity loop gain frequency) is the same as in

the type I loop

Presence of a zero before the PLL bandwidth (unity loop

gain frequency)
Integral path inuences the phase transfer functions only

well below the PLL bandwidth

Analysis of type II Phase locked loop

Pole zero locations Phase (jitter) transfer functions Higher order loop lter for higher spur suppression

Suggested course outline

Negative feedback circuits Stability analysis Opamp topologies using controlled sources (Gm ) Opamp topologies at the transistor level Phase locked loop at the system level

Conclusions

Negative feedback: Continuous adjustment to reduce error Integrator is the key element of the negative feedback loop Implementing a voltage integrator and seeking to improve

its performance leads to commonly used opamp topologies

Implementing a negative feedback frequency multiplier and

seeking to improve its performance leads to type I and II phase locked loops
Valuable intuition gained before embarking on analysis

References
Paul R. Gray, Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer, Analysis and Design of Analog Integrated Circuits, 5th ed., Wiley 2009. R. D. Middlebrook, Methods of design-oriented analysis: Low-entropy expressions, New Approaches to Undergraduate Education IV, Santa Barbara, 26-31 July 1992. Nagendra Krishnapura, Introducing negative feedback with an integrator as the central element, Proc. 2012 IEEE ISCAS, May 2012. Shanthi Pavan, EC201: Analog Circuits, Available: http://www.ee.iitm.ac.in/nagendra/videolectures Floyd M. Gardner, Phaselock Techniques, 3rd ed., Wiley-Interscience 2005. Roland Best, Phase Locked Loops: Design, Simulation and Applications, 5th ed., McGraw-Hill 2007. Stanley Goldman, Phase Locked Loop Engineering Handbook for Integrated Circuits, Artech House 2007. Behzad Razavi, Design of Analog CMOS Integrated Circuits, 1st edition, McGraw-Hill, 2000. Nagendra Krishnapura, EE5390: Analog Integrated Circuit Design, Available: http://www.ee.iitm.ac.in/nagendra/videolectures