Lecture 1

Silicon
Silicon is a dominant material compared to GaAs, Ge and other semiconductor materials. GaAs has high electron mobility (advantage) However low hole mobility, less stable during thermal processing, poor thermal oxide, high cost and higher defect densities. Silicon is an indirect band gap, whereas GaAs is a direct band gap material. GaAs is efficient in making LEDs and Lasers. GaAs emit in red spectrum (lower energy due to lower band gap). GaN emits in blue (higher energy due to wider band gap).

Trends and challenges

Moores Law Line width: Smallest lateral feature size that is printed on the wafer during fabrication process. Mask count is the measure of the number of lithography or printing operations required to manufacture the chips. As transistors get smaller, the electric fields in these devices will increase to unacceptable levels unless operating voltages are reduced.

Trend of scaling

When device dimensions reach 10 or 20 nm, quantum mechanical effects will become important.

Intel: From sand to silicon

http://www.intel.com/pressroom/kits/chipmaking/

Homework 2.1: Write a brief on difference in 22nm, 32nm and 45 nm technology ?

Covalent bonds
Covalent bond stable at low temperatures (below absolute ZERO). Ga(III column) and As (V column) bond. At temperatures above ZERO, thermal energy can break covalent bonds, creating free mobile electrons and holes (missing electrons). The concentration of electrons and holes are exactly equal in pure semiconductors and are referred as intrinsic carrier concentration (ni).

Carrier concentration
ni = 1.4 X 1010cm-3 in silicon. 5 X 1022cm-3 in silicon 1 in 1012 bonds are broken in room temperature. Hence poor conductor and not useful for devices. Dopants diffusion/ion-implantation is needed to generate free electrons.

Resistivity

Activity 1.1
Consider a pure silicon 1100 cm long with a cross sectional area of 1 m2. How much current will flow through this resistor at room temperature in response to applied voltage of 1V?

Intrinsic carrier concentration

Equations

Activity 1.2
A silicon diode has doping concentrations on the N and P sides of Nd = 1 X 1019 cm-3 and NA = 1 X 1015cm-3. Calculate the process temperature at which the two sides of the diode become intrinsic.

P-N junction

I = Io(exp(qV/KT) 1)

Junction capacitance
Built in voltage

Junction Capacitance

NMOS

PN junctions are zero biased or reverse biased, thereby very little current flows across the junctions. Field effect mechanism operate for insulators such as SiO2 grown on top of Si substrate.

NMOS and PMOS

Source
Polysilicon SiO2
1

Source

Gate

Drain

Gate

Drain

Polysilicon SiO2

n+ p

n+
S D

p+ n

p+ bulk Si

bulk Si

Body tied to GND. Gate LOW: Transistor is OFF Gate HIGH: Transistor is ON

Body tied to Vdd. Gate LOW: Transistor is ON Gate HIGH: Transistor is OFF Bubbles indicates inverted behavior

Power supply
GND = 0 V Vdd = 5 V in 1980s Vdd has decreased in modern processes. Two advantages:
Small Vdd saves power High Vdd would damage tiny transistors. Vdd = 3.3, 2,5, 1.8, 1.5, 1.2, 1.0

CMOS Inverter cross section

Substrate must be tied to GND and n-well to VDD.

A GND Y VDD SiO2 n+ diffusion n+ n+ p substrate nMOS transistor pMOS transistor p+ n well p+ p+ diffusion polysilicon metal1

CMOS Inverter
VDD

GND

Which Gate ?

Y A B

Inverter mask set

GND nMOS transistor substrate tap pMOS transistor well tap

VDD

Mask Set
n well

Polysilicon

n+ Diffusion

p+ Diffusion

Contact

Metal

Layout
Set of masks constitute the layout. Minimum dimensions of masks determine transistor size (and hence speed, cost, and power). Feature size f = distance between source and drain Set by minimum width of polysilicon. Express rules in terms of l = f/2
E.g. l = 0.3 mm in 0.6 mm process