dsk6713 TechRef

TMS320C6713 DSK
Technical
Reference
2003 DSP Development Systems

TMS320C6713 DSK
Technical Reference
506735-0001 Rev. B
November 2003
SPECTRUM DIGITAL, INC.

12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505 Fax: 281.494.5310
sales@spectrumdigital.com www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright © 2003 Spectrum Digital, Inc.

Contents
1 Introduction to the TMS320C6713 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

Provides you with a description of the TMS320C6713 DSK Module, key features, and
block diagram.
1.1 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.6 Power Supply ......................................................... 1-6
2 Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Describes the operation of the major board components on the TMS320C6713 DSK.
2.1 CPLD (programmable Logic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.1.1 CPLD Overview .................................................... 2-2
2.1.2 CPLD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
2.1.3 USER_REG Register .............................................. 2-3
2.1.4 DC_REG Register .................................................. 2-4
2.1.5 Version Register .................................................. 2-4
2.1.6 MISC Register ..................................................... 2-5
2.2 Codec Interface ..................................................... 2-6
2.3 SRAM Interface ..................................................... 2-7
2.4 Flash ROM Interface ................................................ 2-7
2.5 LEDs and DIP Switches .............................................. 2-7
2.6 Daughter Card Interface .............................................. 2-8
3 Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Describes the physical layout of the TMS320C6713 DSK and its connectors.
3.1 Board Layout ........................................................ 3-2
3.2 Connector Index .................................................... 3-3
3.3 Expansion Connectors ................................................ 3-3
3.3.1 J4, Memory Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
3.3.2 J3, Peripheral Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
3.3.3 J1, HPI Expansion Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.4 Audio Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.1 J301, Microphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.2 J303, Audio Line In Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
3.4.3 J304, Audio Line Out Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.4.4 J302, Headphone Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
3.5 Power Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.1 J5, +5V Main Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.5.2 J6, Optional Power Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.6. Miscellaneous Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
3.6.1 J201, USB Port .................................................... 3-10
3.6.2 J8, External JTAG Connector ........................................ 3-10
3.6.3 JP3, PLD Programming Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
3.7 System LEDs ....................................................... 3-11
3.8 Reset Switch ....................................................... 3-11
A Schematics .............................................................. A-1
Contains the schematics for the TMS320C6713 DSK
B Mechanical Information .................................................. B-1
Contains the mechanical information about the TMS320C6713 DSK
About This Manual
This document describes the board level operations of the TMS320C6713 DSP
Starter Kit (DSK) module. The DSK is based on the Texas Instruments
TMS320C6713 Digital Signal Processor.
The TMS320C6713 DSK is a table top card to allow engineers and software
developers to evaluate certain characteristics of the TMS320C6713 DSP to determine
if the processor meets the designers application requirements. Evaluators can create
software to execute onboard or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The TMS320C6713 DSK will sometimes be referred to as the DSK.
Program listings, program examples, and interactive displays are shown is a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.

This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents
Texas Instruments TMS320C67xx DSP CPU Reference Guide

Texas Instruments TMS320C67xx DSP Peripherals Reference Guide
Table 1: Manual History
Revision History
A Alpha Release
Chapter 1
Introduction to the
TMS320C6713 DSK
Chapter One provides a description of the TMS320C6713 DSK along

with the key features and a block diagram of the circuit board.
Topic Page
1.1 Key Features 1-2
1.2 Functional Overview 1-3
1.3 Basic Operation 1-4
1.4 Memory Map 1-5
1.5 Configuration Switch Settings 1-6
1.6 Power Supply 1-6
1-1
Spectrum Digital, Inc
1.1 Key Features
The C6713 DSK is a low-cost standalone development platform that enables users to
evaluate and develop applications for the TI C67xx DSP family. The DSK also serves
as a hardware reference design for the TMS320C6713 DSP. Schematics, logic
equations and application notes are available to ease hardware development and
reduce time to market.
LINE OUT
HP OUT
LINE IN
MIC IN
Memory Exp
32
McBSPs
AIC23 EMIF
MUX
Host Port Int

Codec 8 8 32
JP1 1.26V
SDRAM
CPLD
Flash
JP2 3.3V 6713
JTAG DSP
MUX
Voltage
Reg HPI
Embedded Peripheral Exp
JTAG
BOOTM 1
BOOTM 0
JP4 5V
ENDIAN
HPI_EN
Config
Ext. LED DIP
PWR
USB
SW3
JTAG 1 2 3 4 0123 0123
Figure 1-1, Block Diagram C6713 DSK

The DSK comes with a full compliment of on-board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments TMS320C6713 DSP operating at 225 MHz.
• An AIC23 stereo codec
• 16 Mbytes of synchronous DRAM
• 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default

configuration)
• 4 user accessible LEDs and DIP switches
• Software board configuration through registers implemented in CPLD
• Configurable boot options
• Standard expansion connectors for daughter card use
• JTAG emulation through on-board JTAG emulator with USB host

interface or external emulator
• Single voltage power supply (+5V)

1-2 TMS320C6713 DSK Module Technical Reference
1.2 Functional Overview of the TMS320C6713 DSK
The DSP on the 6713 DSK interfaces to on-board peripherals through a 32-bit wide
EMIF (External Memory InterFace). The SDRAM, Flash and CPLD are all connected
to the bus. EMIF signals are also connected daughter card expansion connectors
which are used for third party add-in boards.
The DSP interfaces to analog audio signals through an on-board AIC23 codec and four
3.5 mm audio jacks (microphone input, line input, line output, and headphone output).
The codec can select the microphone or the line input as the active input. The analog
output is driven to both the line out (fixed gain) and headphone (adjustable gain)
connectors. McBSP0 is used to send commands to the codec control interface while
McBSP1 is used for digital audio data. McBSP0 and McBSP1 can be re-routed to the
expansion connectors in software.
A programmable logic device called a CPLD is used to implement glue logic that ties
the board components together. The CPLD has a register based user interface that
lets the user configure the board by reading and writing to its registers.
The DSK includes 4 LEDs and a 4 position DIP switch as a simple way to provide the
user with interactive feedback. Both are accessed by reading and writing to the CPLD
registers.
An included 5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.26V DSP core voltage and +3.3V I/O supplies. The
board is held in reset until these supplies are within operating specifications.
Code Composer communicates with the DSK through an embedded JTAG emulator
with a USB host interface. The DSK can also be used with an external emulator
through the external JTAG connector.
1-3
1.3 Basic Operation
The DSK is designed to work with TI’s Code Composer Studio development
environment and ships with a version specifically tailored to work with the board.
Code Composer communicates with the board through the on-board JTAG emulator.
To start, follow the instructions in the Quick Start Guide to install Code Composer.
This process will install all of the necessary development tools, documentation and
drivers.
After the install is complete, follow these steps to run Code Composer. The DSK must
be fully connected to launch the DSK version of Code Composer.
1) Connect the included power supply to the DSK.
2) Connect the DSK to your PC with a standard USB cable (also included).
3) Launch Code Composer from its icon on your desktop.
Detailed information about the DSK including a tutorial, examples and reference
material is available in the DSK’s help file. You can access the help file through Code
Composer’s help menu. It can also be launched directly by double-clicking on the file
c6713dsk.hlp in Code Composer’s docs\hlp subdirectory.

1.4 Memory Map
The C67xx family of DSPs has a large byte addressable address space. Program code
and data can be placed anywhere in the unified address space. Addresses are always
32-bits wide.
The memory map shows the address space of a generic 6713 processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of the internal memory
can be reconfigured in software as L2 cache rather than fixed RAM.
The EMIF has 4 separate addressable regions called chip enable spaces (CE0-CE3).
The SDRAM occupies CE0 while the Flash and CPLD share CE1. CE2 and CE3 are
generally reserved for daughtercards.
C67x Family
Address Memory Type 6713 DSK
0x00000000
Internal
Internal Memory
Memory
0x00030000
Reserved Space Reserved
or or
Peripheral Regs Peripheral
0x80000000
EMIF CE0 SDRAM
0x90000000 Flash
EMIF CE1 0x90080000
CPLD
0xA0000000
EMIF CE2
Daughter
0xB0000000 Card
EMIF CE3
Figure 1-2, Memory Map, C6713 DSK
1-5
1.5 Configuration Switch Settings
The DSK has 4 configuration switches that allows users to control the operational state
of the DSP when it is released from reset. The configuration switch block is labeled
SW3 on the DSK board, next to the reset switch.
Configuration switch 1 controls the endianness of the DSP while switches 2 and 3
configure the boot mode that will be used when the DSP starts executing.
Configuration switch 4 controls the on-chip multiplexing of HPI and McASP signals
brought out to the HPI expansion connector. By default all switches are off which
corresponds to EMIF boot (out of 8-bit Flash) in little endian mode and HPI signals on
the HPI expansion connector.
Table 1: Configuration Switch Settings
Switch 1 Switch 2 Switch 3 Switch 4 Configuration Description

Off Little endian (default)
On Big endian
Off Off EMIF boot from 8-bit Flash (default)
Off On HPI/Emulation boot
On Off 32-bit EMIF boot
On On 16-bit EMIF boot
Off HPI enabled on HPI pins (default)
On McASP1 enabled on HPI pins
1.6 Power Supply
The DSK operates from a single +5V external power supply connected to the main
power input (J5). Internally, the +5V input is converted into +1.26V and +3.3V using
separate voltage regulators. The +1.26V supply is used for the DSP core while the
+3.3V supply is used for the DSP's I/O buffers and all other chips on the board. The
power connector is a 2.5mm barrel-type plug.
There are three power test points on the DSK at JP1, JP2 and JP4. All I/O current
passes through JP2 while all core current passes through JP1. All system current
passes through JP4. Normally these jumpers are closed. To measure the current
passing through remove the jumpers and connect the pins with a current measuring
device such as a multimeter or current probe.
It is possible to provide the daughter card with +12V and -12V when the external power
connector (J6) is used.

Chapter 2
Board Components
This chapter describes the operation of the major board components on

the TMS320C6713 DSK.
Topic Page
2.1 CPLD (Programmable Logic) 2-2
2.1.1 CPLD Overview 2-2
2.1.2 CPLD Registers 2-3
2.1.3 USER_REG Register 2-3
2.1.4 DC_REG Register 2-4
2.1.5 Version Register 2-4
2.1.6 MISC Register 2-5
2.2 AIC23 Codec 2-6
2.3 Sychronous DRAM 2-7
2.4 Flash Memory 2-7
2.5 LEDs and DIP Switches 2-7
2.6 Daughter Card Interface 2-8
2-1
2.1 CPLD (Programmable Logic)
The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic

Device (CPLD) device to implement:
• 4 Memory-mapped control/status registers that allow software

control of various board features.
• Control of the daughter card interface and signals.
• Assorted "glue" logic that ties the board components together.
2.1.1 CPLD Overview
The CPLD logic is used to implement functionality specific to the DSK. Your own
hardware designs will likely implement a completely different set of functions or take
advantage of the DSPs high level of integration for system design and avoid the use
of external logic completely.
The CPLD implements simple random logic functions that eliminate the need for
additional discrete devices. In particular, the CPLD aggregates the various reset
signals coming from the reset button and power supervisors and generates a global
reset.
The EPM3128TC100-10 is a 3.3V (5V tolerant), 100-pin QFP device that provides
128 macrocells, 80 I/O pins, and a 10 ns pin-to-pin delay. The device is
EEPROM-based and is in-system programmable via a dedicated JTAG interface
(a 10-pin header on the DSK). The CPLD source files are written in the industry
standard VHDL (Hardware Design Language) and included with the DSK.

2.1.2 CPLD Registers
The 4 CPLD memory-mapped registers allows users to control CPLD functions in

software. On the 6713 DSK the registers are primarily used to access the LEDs and
DIP switches and control the daughter card interface. The registers are mapped into
EMIF CE1 data space at address 0x90080000. They appear as 8-bit registers with a
simple asynchronous memory interface. The following table gives a high level
overview of the CPLD registers and their bit fields:
The table below shows the bit definitions for the 4 registers in CPLD.
Table 1: CPLD Register Definitions
Offset Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 USER_REG USR_SW3 USR_SW2 USR_SW1 USR_SW0 USR_LED3 USR_LED2 USR_LED1 USR_LED0

R R R R R/W R/W R/W R/W
0(Off) 0(Off) 0(Off) 0(Off)
1 DC_REG DC_DET 0 DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0

R R R R R/W R/W
0(No reset) 0(low) 0(low)
4 VERSION CPLD_VER[3.0] 0 BOARD VERSION[2.0]

R R
6 MISC SCR_5 SCR_4 SCR_3 SCR_2 SCR_1 FLASH_PAGE McBSP1 McBSP0

R/W R/W R/W R/W R/W R/W ON/OFF ON/OFF
0 0 0 0 0 0 Board Board
(Flash A19=0) R/W R/W
0 0
(Onboard) (Onboard)
2.1.3 USER_REG Register
USER_REG is used to read the state of the 4 DIP switches and turn the 4 LEDs on or
off to allow the user to interact with the DSK. The DIP switches are read by reading the
top 4 bits of the register and the LEDs are set by writing to the low 4 bits.
Table 2: CPLD USER_REG Register
Bit Name R/W Description
7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)

3 USER_LED3 R/W User-defined LED 3 Control (0 = Off, 1 = On)
2-3
2.1.4 DC_REG Register
DC_REG is used to monitor and control the daughter card interface. DC_DET detects
the presence of a daughter card. DC_STAT and DC_CNTL provide simple
communications with the daughter card through readable status lines and writable
control lines.
The daughter card is released from reset when the DSP is released from reset.
DC_RST can be used to put the card back in reset.
Table 3: DC_REG Register
7 DC_DET R Daughter Card Detect (1= Board detected)

6 0 R Always zero
5 DC_STAT1 R Daughter Card Status 1 (0=Low, 1 = High)
4 DC_STAT0 R Daughter Card Status 0 (0=Low, 1 = High)
3 DC_RST R/W Daughter Card Reset (0=No Reset, 1 = Reset)
2 0 R Always zero
1 DC_CNTL1 R/W Daughter Card Control 1(0 = Low, 1 = High)
0 DC_CNTL0 R/W Daughter Card Control 0(0 = Low, 1 = High)
2.1.5 VERSION Register
The VERSION register contains two read only fields that indicate the BOARD and
CPLD versions. This register will allow your software to differentiate between
production releases of the DSK and account for any variances. This register is not
expected to change often, if at all.
Table 4: Version Register Bit Definitions
Bit # Name R/W Description
7 CPLD_VER3 R Most Significant CPLD Version Bit

6 CPLD_VER2 R CPLD Version Bit
5 CPLD_VER1 R CPLD Version Bit
4 CPLD_VER0 R Least Significant CPLD Version Bit
3 0 R Always zero
2 DSK_VER2 R Most Significant DSK Board Version Bit
1 DSK_VER1 R DSK Board Version Bit
0 DSK_VER0 R Least Significant DSK Board Version Bit

2.1.6 MISC Register
The MISC register is used to provide software control for miscellaneous board
functions. On the 6713 DSK, the MISC register controls how auxiliary signals are
brought out to the daughter-card connectors.
McBSP0 and McBSP1 are usually used as the control and data ports of the on-board
AIC23 codec. The power-on state of these bits (both 0s) represents that situation.
Set the corresponding McBSP select bit to use the McBSP with a daughter card
instead.
The Flash and CPLD share CE1 which means that the highest DSP address bit (A21)
is used to differentiate between the two. The FLASH_PAGE bit is driven to the Flash as
a replacement for that address line which is connected to A19 of the Flash. On a
standard DSK, the on-board Flash is not large enough for this bit to be significant.
FLASH_PAGE is only useful if the board is re-populated with a larger pin-compatible
Flash chip.
The scratch bits are unused. They can be set to any value.
Table 5: MISC Register
7 SCRATCH_5 R/W Scratch bit 5

2 FLASH_PAGE R/W Flash address bit 19
1 MCBSP1SEL R/W McBSP1 on/off board (0 = on-board, 1 = off-board)
0 MCBSP0SEL R/W McBSP0 on/off board (0 = on-board, 1 = off-board)
2-5
2.2 AIC23 Codec
The DSK uses a Texas Instruments AIC23 (part #TLV320AIC23) stereo codec for input
and output of audio signals. The codec samples analog signals on the microphone or
line inputs and converts them into digital data so it can be processed by the DSP.
When the DSP is finished with the data it uses the codec to convert the samples back
into analog signals on the line and headphone outputs so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. McBSP0 is
used as the unidirectional control channel. It should be programmed to send a 16-bit
control word to the AIC23 in SPI format. The top 7 bits of the control word should
specify the register to be modified and the lower 9 should contain the register value.
The control channel is only used when configuring the codec, it is generally idle when
audio data is being transmitted,
McBSP1 is used as the bi-directional data channel. All audio data flows through the
data channel. Many data formats are supported based on the three variables of
sample width, clock signal source and serial data format. The DSK examples generally
use a 16-bit sample width with the codec in master mode so it generates the frame
sync and bit clocks at the correct sample rate without effort on the DSP side. The
preferred serial format is DSP mode which is designed specifically to operate with the
McBSP ports on TI DSPs.
The codec has a 12MHz system clock. The 12MHz system clock corresponds to USB
sample rate mode, named because many USB systems use a 12MHz clock and can
use the same clock for both the codec and USB controller. The internal sample rate
generate subdivides the 12MHz clock to generate common frequencies such as
48KHz, 44.1KHz and 8KHz. The sample rate is set by the codec’s SAMPLERATE
register. The figure below shows the codec interface on the C6713 DSK.
AIC23 Codec
0 LEFTINVOL
1 RIGHTINVOL
2 LEFTHPVOL MIC IN
Control Registers
3 RIGHTHPVOL
FSX1 McBSP0 CS 4 ANAPATH
CLKX1 SCLK 5 DIGPATH LINE IN
TX1 SDIN 6 POWERDOWN
SPI Format 7 DIGIF
8 SAMPLERATE
Digital 9 DIGACT Analog
15 RESET LINE OUT
DR2 McBSP1
DOUT MIC IN
FSX2 ADC
CLKR LRCOUT LINE IN
DSP Format BCLK
CLKX LRCIN
FSR2 DIN DAC LINE OUT
DX2 HP OUT HP OUT
Figure 2-1, TMS320C6713 DSK CODEC INTERFACE

2.3 Synchronous DRAM
The DSK uses a 128 megabit synchronous DRAM (SDRAM) on the 32-bit EMIF. The
SDRAM is mapped at the beginning of CE0 (address 0x80000000). Total available
memory is 16 megabytes. The integrated SDRAM controller is part of the EMIF and
must be configured in software for proper operation. The EMIF clock is derived from the
PLL settings and should be configured in software at 90MHz. This number is based on
an internal PLL clock of 450MHz required to achieve 225 MHz operation with a divisor
of 2 and a 90MHz EMIF clock with a divisor of 5.
When using SDRAM, the controller must be set up to refresh one row of the memory
array every 15.6 microseconds to maintain data integrity. With a 90MHz EMIF clock,
this period is 1400 bus cycles.
2.4 Flash Memory
Flash is a type of memory which does not lose its contents when the power is turned
off. When read it looks like a simple asynchronous read-only memory (ROM). Flash
can be erased in large blocks commonly referred to as sectors or pages. Once a block
has been erased each word can be programmed once through a special command
sequence. After than the entire block must be erased again to change the contents.
The DSK uses a 512Kbyte external Flash as a boot option. It is visible at the beginning
of CE1 (address 0x90000000). The Flash is wired as a 256K by 16 bit device to support
the DSK's 16-bit boot option. However, the software that ships with the DSK treats the
Flash as an 8-bit device (ignoring the top 8 bits) to match the 6713's default 8-bit boot
mode. In this configuration, only 256Kbytes are readily usable without software
changes.
2.5 LEDs and DIP Switches
The DSK includes 4 software accessible LEDs (D7-D10) and DIP switches (SW1) that
provide the user a simple form of input/output. Both are accessed through the CPLD
USER_REG register.
2-7
2.6 Daughter Card Interface
The DSK provides three expansion connectors that can be used to accept plug-in
daughter cards. The daughter card allows users to build on their DSK platform to
extend its capabilities and provide customer and application specific I/O. The
expansion connectors are for memory, peripherals, and the Host Port Interface (HPI)
The memory connector provides access to the DSP’s asynchronous EMIF signals to
interface with memories and memory mapped devices. It supports byte addressing on
32 bit boundries. The peripheral connector brings out the DSP’s peripheral signals like
McBSPs, timers, and clocks. Both connectors provide power and ground to the
daughter card
The HPI is a high speed interface that can be used to allow multiple DSPs to
communicate and cooperate on a given task. The HPI connector brings out the HPI
specific control signals.
Most of the expansion connector signals are buffered so that the daughter card cannot
directly influence the operation of the DSK board. The use of TI low voltage, 5V tolerant
buffers, and CBT interface devices allows the use of either +5V or +3.3V devices to be
used on the daughter card.
Other than the buffering, most daughter card signals are not modified on the board.
However, a few daughter card specific control signals like DC_RESET and
DC_DET exist and are accessible through the CPLD DC_REG register. The DSK
also multiplexes the McBSP0 and McBSP1 of on-board or external use. This function
is controlled through the CPLD MISC register.

Chapter 3
Physical Description
This chapter describes the physical layout of the TMS320C6713 DSK

and its connectors.
Topic Page
3.1 Board Layout 3-2
3.2 Connector Index 3-3
3.3 Expansion Connectors 3-3
3.3.1 J4, Memory Expansion Connector 3-4
3.3.2 J3, Peripheral Expansion Connector 3-5
3.3.3 J1, HPI Expansion Connector 3-6
3.4 Audio Connectors 3-7
3.4.1 J301, Microphone Connector 3-7
3.4.2 J303, Audio Line In Connector 3-7
3.4.3 J304, Audio Line Out Connector 3-8
3.4.4 J302, Headphone Connector 3-8
3.5 Power Connectors 3-9
3.5.1 J5, +5 Volt Connector 3-9
3.5.2 J6, Optional Power Connector 3-9
3.6 Miscellaneous Connectors 3-10
3.6.1 J201, USB Connector 3-10
3.6.2 J8, External JTAG Connector 3-10
3.6.3 JP3, PLD Programming Connector 3-11
3.7 System LEDs 3-11
3.8 Reset Switch 3-11
3-1
3.1 Board Layout
The C6713 DSK is a 8.75 x 4.5 inch (210 x 115 mm.) multi-layer board which is
powered by an external +5 volt only power supply. Figure 3-1 shows the layout of the
C6713 DSK.
J301 J303 J304 J302 J3 J4 J1
J6 J5 J201 JP3 SW1 D7-10 SW2 J8

Figure 3-1, TMS320C6713 DSK
3-2 TMS320VC6713 DSK Module Technical Reference

3.2 Connector Index
The TMS320C6713 DSK has many connectors which provide the user access
to the various signals on the DSK.
Table 1: TMS320C6713 DSK Connectors
Connector # Pins Function
J4 80 Memory
J3 80 Peripheral
J1 80 HPI
J301 3 Microphone
J303 3 Line In
J304 3 Line Out
J303 3 Headphone
J5 2 +5 Volt
J6 * 4 Optional Power Connector
J8 14 External JTAG
J201 5 USB Port
JP3 10 CPLD Programming
SW3 8 DSP Configuration Jumper
Note: “*” Not populated
3.3 Expansion Connectors
The TMS320C6713 DSK supports three expansion connectors that follow the Texas
Instruments interconnection guidelines. The expansion connector pinouts are
described in the following three sections.
The three expansion connectors are all 80 pin 0.050 x 0.050 inches low profile
connectors from Samtec or AMP. The Samtec SFM Series (surface mount) connectors
are designed for high speed interconnections because they have low propagation
delay, capacitance, and cross talk. The connectors present a small foot print on the
DSK. Each connector includes multiple ground, +5V, and +3.3V power signals so that
the daughter card can obtain power directly from the DSK. The peripheral expansion
connector additionally provides both +12V and -12V to the daughter card. The
recommended mating connector, whose part number is TFM-140-32-S-D-LC, is a
surface mount connector that provides a 0.465” mated height.
Note: I is on an Input pin

O is on an Output pin
Z is on a High Impedance pin
3-3
3.3.1 J4, Memory Expansion Connector
Table 2: J4, Memory Expansion Connector
Pin Signal I/O Description Pin Signal I/O Description

1 5V Vcc 5V voltage supply pin 2 5V Vcc 5V voltage supply pin
3 AEA21 O EMIF address pin 21 4 AEA20 O EMIF address pin 20
11 GND Vss System ground 12 GND Vss System ground
27 ABE3# O EMIF byte enable 3 28 ABE2# O EMIF byte enable 2
29 ABE1# O EMIF byte enable 1 30 ABE0# O EMIF byte enable 0
33 AED31 I/O EMIF data pin 31 34 AED30 I/O EMIF data pin 30
41 3.3V Vcc 3.3V voltage supply pin 42 3.3V Vcc 3.3V voltage supply pin
73 AARE# O EMIF async read enable 74 AAWE# O EMIF async write enable
75 AAOE# O EMIF async output enable 76 AARDY I EMIF asynchronous ready
77 ACE3# O Chip enable 3 78 ACE2# O Chip enable 2

3.3.2 J3, Peripheral Expansion Connector
Table 3: J3, Peripheral Expansion Connector

1 12V Vcc 12V voltage supply pin 2 -12V Vcc -12V voltage supply pin
11 N/C - No connect 12 N/C - No connect
19 3.3V Vcc 3.3V voltage supply pin 20 3.3V Vcc 3.3V voltage supply pin
21 CLKX0 I/O McBSP0 transmit clock 22 CLKS0 I McBSP0 clock source
23 FSX0 I/O McBSP0 transmit frame sync 24 DX0 O McBSP0 transmit data
27 CLKR0 I/O McBSP0 receive clock 28 N/C - No connect
29 FSR0 I/O McBSP0 receive frame sync 30 DR0 I McBSP0 receive data
33 CLKX1 I/O McBSP1 transmit clock 34 CLKS1 I McBSP1 clock source
35 FSX1 I/O McBSP1 transmit frame sync 36 DX1 O McBSP1 transmit data
39 CLKR1 I/O McBSP1 receive clock 40 N/C - No connect
41 FSR1 I/O McBSP1 receive frame sync 42 DR1 I McBSP1 receive data
45 TOUT0 O Timer 0 output 46 TINP0 I Timer 0 input
47 N/C - No connect 48 EXT_INT5 I External interrupt 5
49 TOUT1 O Timer 1 output 50 TINP1 I Timer 1 input
53 EXT_INT4 I External interrupt 4 54 N/C - No connect
59 RESET O System reset 60 N/C - No connect
63 CNTL1 O Daughtercard control 1 64 CNTL0 O Daughtercard control
65 STAT1 I Daughtercard status 1 66 STAT0 I Daughtercard status
67 EXT_INT6 I External interrupt 6 68 EXT_INT7 I External interrupt 7
69 ACE3# O Chip enable 3 70 N/C - No connect
75 DC_DET# Vss System ground 76 GND Vss System ground
77 GND Vss System ground 78 ECL KOUT O EMIF Clock
3-5
3.3.3 J1, HPI Expansion Connector
Table 4: J1, HPI Expansion Connector

3 GND Vss System ground 4 HPI_RESETn I HPI reset input
5 CLKOUT3 O Clock output3 6 N/C - No connect
9 HD1/AXR1[7] I/O HPI data 1 10 N/C - No connect
11 HD3/AMUTE1 I/O HPI data 3 12 HD0/AXR1[4] I/O HPI data 0
13 HD5/AHCLKX1 I/O HPI data 5 14 HD2/AFSX1 I/O HPI data 2
15 HD7/GP0[3] I/O HPI data 7 16 HD4/GP0[0] I/O HPI data 4
17 GND Vss System ground 18 HD6/AHCLKR1 I/O HPI data 6
19 HD8/GP0[8] I/O HPI data 8 20 GND Vss System ground
27 GND Vss System ground 28 HD15/GP0[15] I/O HPI data 15
29 HDS2z/AXR1[5] I/O Host data strobe 2 30 GND Vss System ground
31 GND Vss System ground 32 HASz/ACLKX1 I/O Host address strobe
33 HDS1z/AXR1[6] I/O Host data strobe 1 34 GND Vss System ground
35 GND Vss System ground 36 HCNTL0/AXR1[3] I/O Host control 1
37 HCSz/AXR1[2] I/O Host chip select 38 GND Vss System ground
39 GND Vss System ground 40 HHWIL/AFSR1 I/O Host half-word select
41 HCNTL1/AXR1[1] I/O Host control 1 42 GND Vss System ground
43 GND Vss System ground 44 HINTz/GP0[1] I/O Host interrupt
45 HRDYZ/ACLKR1 I/O Host Ready 46 GND Vss System ground
47 GND Vss System ground 48 N/C - No connect
49 HR/Wz/AXR1[0] I/O Host R/W strobe 50 N/C - No connect
55 N/C - No connect 56 GND Vss System ground
67 N/C - No connect 68 SCL0 I/O I2C0 Clock
71 GND Vss System ground 72 SDA0 I/O I2C0 Data
79 GND Vss System ground 80 CLKOUT2/GP0[2] I/O GP I/O 0 bit 2

3.4 Audio Connectors
The C6713 DSK has 4 audio connectors. They are described in the following
sections.
3.4.1 J301, Microphone Connector
The input is a 3.5 mm. stereo jack. Both inputs are connected to the microphone so it is
monaural. The signals on the plug are shown in the figure below.
Ground
Microphone In
Microphone Bias
Figure 3-2, Microphone Stereo Jack
3.4.2 J303, Audio Line In Connector
The audio line in is a stereo input. The input connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.
Ground
Right Line In
Left Line In
Figure 3-3, Audio Line In Stereo Jack
3-7
3.4.3 J304, Audio Line Out Connector
The audio line out is a stereo output. The output connector is a 3.5 mm stereo jack. The
signals on the mating plug are shown in the figure below.
Ground
Right Line Out
Left Line Out
Figure 3-4, Audio Line Out Stereo Jack
3.4.4 J303, Headphone Connector
Connector J4 is a headphone/speaker jack. It can drive standard headphones or a high

impedance speaker directly. The standard 3.5 mm jack is shown in the figure below.
Ground
Right Headphone
Left Headphone
Figure 3-5, Headphone Jack

3.5 Power Connectors
The C6713 DSK has 2 power connectors. They are described in the following
sections.
3.5.1 J5, +5 Volt Connector
Power (+5 volts) is brought onto the TMS320C6713 DSK via the J5 connector. The
connector has an outside diameter of 5.5 mm. and an inside diameter of 2.5 mm. The
A diagram of J5 is shown below.
+5V
J5 Ground
PC Board
Front View
Figure 3-6, TMS320C6713 DSK Power Connector
3.5.2 J6, Optional Power Connector
Connector J6 is an optional power connector. It will operate with the standard personal
computer power supply. To populate this connector use a Molex #15-24-4041. The
table below shows the voltages on the respective pins.
Table 5: J6, Optional Power Connector
Pin # Voltage Level
1 +12 Volts
2 -12 Volts
3 Ground
4 +5 Volts
WARNING !
Do not plug into J5 and J6 at the same time.
3-9
3.6 Miscellaneous Connectors
The C6713 DSK has 3 additional connectors to aid the user in developing with this
product. They are described in the following sections.
3.6.1 J201, USB Connector
Connector J201 provides a Universal Serial Bus (USB) Interface to the embedded
JTAG emulation logic on the DSK. This allows for code development and debug
without the use of an external emulator. The signals on this connector are shown in the
below.
Table 6: J201, USB Connector
Pin # USB Signal Name
1 USBVdd
2 D+
3 D-
4 USB Vss
5 Shield
6 Shield
3.6.2 J8, External JTAG Connector
The TMS320C6713 DSK is supplied with a 14 pin header interface, J8. This is the
standard interface used by JTAG emulators to interface to Texas Instruments DSPs.
The pinout for the connector is shown in the figure below.
TMS 1 2 TRST-
TDI 3 4 GND Header Dimensions
PD (+3.3V) 5 6 no pin (key) Pin-to-Pin spacing, 0.100 in. (X,Y)
TDO 7 8 GND Pin width, 0.025-in. square post
TCK-RET 9 10 GND Pin length, 0.235-in. nominal
TCK 11 12 GND
EMU0 13 14 EMU1
Figure 3-7, J8, JTAG INTERFACE

3.6.3 JP3, PLD Programming Connector
This connector interfaces to the Altera CPLD, U12. It is used in the in the factory for the
programming of the CPLD. This connector is not intended to be used outside the
factory.
3.7 System LEDs
TheTMS320C6713 DSK has four system light emitting diodes (LEDs). These
LEDs indicate various conditions on the DSK. These function of each LED is shown in
the table below.
Table 7: System LEDs
Reference On Signal
Color Function
Designator State
D4 Green USB Emulation in use. When External JTAG 1

Emulator is used this LED is off.
D3 Green +5 Volt present 1
D6 Orange RESET Active 1
DS201 Green USB Active, Blinks during USB data transfer 1
3.8 Reset Switch
There are three resets on the TMS320C6713 DSK. The first reset is the power on
reset. This circuit waits until power is within the specified range before releasing the
power on reset pin to the TMS320C6713.
External sources which control the reset are push button SW2, and the on board
embedded USB JTAG emulator.
3-11

Appendix A
Schematics
This appendix contains the schematics for the TMS320C6713 DSK.

Board components with designators over 200 (e.g. DS201, R211) are part
of Spectrum Digital’s embedded JTAG emulator and are not included in
these schematics.
A-1
A
REVI SI ONS
A-2
REV DESCRI PTI ON DATE APPROVED
A BETA 23-Jan-2003
07-October-2003
The TMS320C6713DSK design is based on
TMS320C6713 device device data sheet
SPRS186B and errata SPRZ173E. This
schematic is subject to change without notification.
Spectrum Digital Inc. assumes no liability for
applications assistance, customer product design
or infringement of patents described herein.
DWN DATE
REVI SI ON STATUS OF SHEETS
CHK DATE
REV
ENGR DATE SPECTRUM DIGITAL INCORPORATED
SH
ENGR- MGR DATE
REV A B A A A A A
QA DATE Title
SH 8 9 10 11 12 13 14
MFG DATE
TMS320C6713 DSK
REV C C A C A A B NEXT ASSY USED ON Size Document Number Rev
RLSE DATE B C
SH 1 2 3 4 5 6 7 APPLI CATI ON
506732
Date: Monday, November 24, 2003 Sheet 1 of 13
TMS320C6713 DSK Module Technical Reference

3.3V
3.3V
USB_DSP_RST# R35 10K
DC_EMIFA_OE# R56 10K
3
D11 CPLD_MCBSP0_MUX R40 10K
R84
10K MMBD4148 CPLD_MCBSP1_MUX R23 10K
U8
5
SW2 DC_STAT0 R97 10K
R83 SN74AHC1G14
1 4
1
2 3 2 4 DC_STAT1 R98 10K
RESET FLSHCEn R57

DGND PUSHBUTTON 33 C119 10K
3
0.1uF
3.3V
DGND
DGND DSP_RST# R22

1K
BRD_RST# R24
1K
39
91
3
18
34
51
66
82
U12 FLASH_PAGE R39
1K
TD[0..31]
TD0 42 25 DGND
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
DSP_DQ0 DC_STAT0 DC_STAT0
VCCINT
VCCINT
TD1 64 96 PULLUP/DOWN TO KEEP LOGIC IN RESET
DSP_DQ1 DC_STAT1 DC_STAT1
TD2 41 WHEN THE CPLD IS NOT PROGRAMMED.
3.3V TD3 DSP_DQ2
63 75 DC_CNTL0
10K RN19D TD4 DSP_DQ3 DC_CNTL0
44 81 DC_CNTL1
10K RN19E TD5 DSP_DQ4 DC_CNTL1
45
10K RN19F TD6 DSP_DQ5
46 52 DC_EMIFA_DIR
10K RN19G TD7 DSP_DQ6 DC_DBUF_DIR
58 37 DC_EMIFA_OE#
DSP_DQ7 DC_DBUF_OEn
TEA[2..21] 54 DC_CNTL_OE#
TEA2 DC_CNTL_OEn
40 79 DC_RST#
SW1 TEA3 DSP_ADDR0 DC_RESETn 3.3V
13 31 DC_DET
TEA4 DSP_ADDR1 DC_DETn
4 5 100
DSP_ADDR2
3 6 69 CPLD_MCBSP0_MUX
MCBSP_SEL0 R78 R79 R80 R81 R82
2 7 98 83 CPLD_MCBSP1_MUX
TCE1n TEA21 DSP_CSn MCBSP_SEL1 150 150 150 150 150
1 8 8
CPLD/FLASHn
76 BRD_RST#
DGND SW DIP-4/SM BRD_RSn
85 DSP_RST#
DSP_RSn D6 D7 D8 D9 D10
10 84
PADDLE SWITCH TCE2n DSP_DC_CS0n DSP_RSn_LED
12
TCE3n DSP_DC_CS1n YELLOW GREEN GREEN GREEN GREEN
90
TSDWEn DSP_DC_WEn
9
3.3V TSDCASn DSP_DC_REn
14 80
TSDRASn DSP_DC_OEn CPLD_CLK_OUT
97 67 USER_LED3
R53 R34 R33 USER_SW3 USER_LED3 USER_LED2
94 47
NU 1K NU USER_SW2 USER_LED2 USER_LED1
93 68
USER_SW1 USER_LED1 USER_LED0
35 71
USER_SW0 USER_LED0
PWB_REV2 29 60
PWB_REV1 PWB_REV2 SPARE0
23 30
PWB_REV0 PWB_REV1 SPARE1 TP TP10
20 48
PWB_REV0 SPARE2
21
R54 R37 R36 SPARE3 TP TP16
CODEC_CLK 87
1K NU 1K CLKIN
6 16
EMU_RSTn RSV0 TP TP19
36 56
PONRSn RSV1
92 61
PUSHBRSn RSV2 TP TP20
99
HPIRSn
57
DGND ISR_TCK FLASH_PAGE TP TP15
62 32
ISR_TMS TCK FLSH_CEn
15 19
ISR_TDI TMS FLSH_WEn
4 17 FLASH_PAGE
USB_DSP_RST# ISR_TDO TDI FLSH_OEn
73
SVS_RST# TDO
FLSHCEn
PUSHB_RS
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HPI_RESET# FLSHWEn
11
26
33
38
43
53
59
65
74
78
86
88
89
95
EPM3128ATC100-10
FLSHOEn
3.3V
JP3
2 1
4 3 DGND
6 5 3.3V
8 7 CPLD
10 9
C38 C68 C69 C71 C72 C39 C70 C40
DGND HEADER 5X2 Title
0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 TMS320C6713 DSK
10K RN19A
10K RN19B Size Document Number Rev
10K RN19C B C
DGND
506732
A-3
C121
A-4
XDS_4.1V
0.1 DGND
U21
24
Vcc
3 2 EINT4
DC_EINT4 1A1 1B1
4 5 EINT5
DC_EINT5 1A2 1B2
7 6 EINT6
DC_EINT6 1A3 1B3
8 9 EINT7
DC_EINT7 1A4 1B4
11 10 TINP0
DC_TINP0 1A5 1B5
1
1OE
14 15 TINP1
DC_TINP1 2A1 2B1
17 16 TOUT0
DC_TOUT0 2A2 2B2
18 19 TOUT1
DC_TOUT1 2A3 2B3
21 20
2A4 2B4
22 23
2A5 2B5
13 12
2OE GND
SN74CBTD3384PW
R77 DGND
360
Maximize the distance between switching signals

DGND and the PLL external components.
Place all PLL external components as close

U10E
to the DSP. All PLL external components
must be on a single side of the board. A13
DSP_RST# RESETn
TP28 C13
R51 NU NMI
C2
GP4/EXTINT4/AMUTEIN1
C1
GP5/EXTINT5/AMUTEIN0
D2
EXCCET103U GP6/EXTINT6
E3
E1 EMI FILTER GP7/EXTINT7
DSPIO_3.3V
G2 G1
TINP0/AXR0_3 TOUT0/AXR0_2
1 3 F2 F1
I O TINP1/AHCLKX0 TOUT1/AXR0_4
GND
CT10 C92
+ 10 0.1 A7 A8
DSP_TDI TDI TDO DSP_TDO
2
DSP_TMS B7
TMS
DSP_TCK A6
TCK
DSP_TRST# B6
TRSTn
D9 DSP_EMU0
DGND EMU0
B9 DSP_EMU1
EMU1
C5 D3 DSP_EMU2
PLLHV EMU2
B10 DSP_EMU3
EMU3
C11 DSP_EMU4
EMU4
CLKMODE0 C4 B12 DSP_EMU5
CLKMODE0 EMU5
C22 A3 Y12 R25 33
CLKIN CLKOUT2/GP2 CLKOUT2
R17 Y11 D10 R26 33
ECLKIN CLKOUT3 CLKOUT3
NO-POP
NO-POP TMS320C6713GDP
DGND OPTIONAL
3.3V
L5
C114 C113
0.1 0.01 Ferrite Chip
U14
1 8
OFFn VCC DGND
4 5 R50 33 DSP_CORE_CLK
GND CLK Title
DGND 50 MHz
TMS320C6713 DSK
Size Document Number Rev
B A
506732

TEA[2..21]
U13
3.3V TEA14 23 2 TD0
U15 SDBA0 BA1 DQ0 TD1
22 4
TEA2 SDA11 BA0 DQ1 TD2
25 37 21 5
TEA3 A0 VCC TEA12 NC DQ2 TD3
24 24 7
TEA4 A1 TD0 TEA11 A10 DQ3 TD4
23 29 66 8
TEA5 A2 DQ0 TD1 TEA10 A9 DQ4 TD5
22 31 65 10
21 33 64 11
20 35 63 13
19 38 62 74
18 40 61 76
8 42 60 77
7 44 27 79
6 30 26 80
5 32 25 82
TEA14 A11 DQ9 TD10 3.3V A0 DQ13 TD14
4 34 83
TEA15 A12 DQ10 TD11 TBE3n DQ14 TD15
3 36 59 85
TEA16 A13 DQ11 TD12 TBE2n DQM3 DQ15 TD16
FLASH_PAGE 2 39 28 31
TEA17 A14 DQ12 TD13 R41 TBE1n DQM2 DQ16 TD17
1 41 71 33
TEA18 A15 DQ13 TD14 TBE0n DQM1 DQ17 TD18
TD[0..31] 48 43 16 34
TEA19 A16 DQ14 TD15 DQM0 DQ18 TD19
17 45 36
TEA20 A17 DQ15/A-1 DQ19 TD20
16 73 37
A18 10K NC DQ20 TD21
9 15 57 39
A19 RY/BY NC DQ21 TD22
30 40
NC DQ22 TD23
10 14 42
NC1 NC DQ23
TD0
TD1
TD2
TD3
TD4
TD5
TD6
TD7
TD8
TD9
3.3V R58 10K TD24
TD10
TD11
TD12
TD13
TD14
TD15
TD16
TD17
TD18
TD19
TD20
TD21
TD22
TD23
TD24
TD25
TD26
TD27
TD28
TD29
TD30
TD31
47 13 45
BYTE NC2 TCE0n DQ24 TD25
FLSHCEn 26 14 20 47
CE NC3 TSDRASn CS DQ25 TD26
FLSHOEn 28 19 48
OE TSDCASn RAS DQ26 TD27
FLSHWEn 11 27 18 50
RN6A
RN6B
RN6C
RN6D
RN6E
RN6F
RN6G
RN6H
RN5A
RN5B
RN5C
RN5D
RN5E
RN5F
RN5G
RN5H
RN4A
RN4B
RN4C
RN4D
RN4E
RN4F
RN4G
RN4H
RN3A
RN3B
RN3C
RN3D
RN3E
RN3F
RN3G
RN3H
WE VSS TSDWEn CAS DQ27 TD28
BRD_RST# 12 46 17 51
RESET VSS WE DQ28 TD29
53
AM29LV400B DQ29 TD30
70 54
NC DQ30
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
DGND TEA16 69 56 TD31
256K x 16 TECLKOUT NC DQ31
68
3.3V R59 10K CLK
67
CKE
86 43
VSS VDD
72 29
VSS VDD
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30
ED31
58 15
VSS VDD
44 1
TEA13 TEA15 VSS VDD
84 81
JP501 VSSQ VDDQ
78 75
K18
K19
L18
L19
M19
M20
N18
N19
N20
P18
P20
R19
R20
T18
T20
T19
V4
W4
Y3
V2
V1
U2
U1
U3
T1
T2
R3
R2
P1
P2
P3
N3
1
1
JP500 VSSQ VDDQ

52 55
VSSQ VDDQ
A
A
46 49
SDBA0 VSSQ VDDQ 3.3V
2 2 SDA11 38 41
ED0
ED1
ED2
ED3
ED4
ED5
ED6
ED7
ED8
ED9
B B VSSQ VDDQ
ED10
ED11
ED12
ED13
ED14
ED15
ED16
ED17
ED18
ED19
ED20
ED21
ED22
ED23
ED24
ED25
ED26
ED27
ED28
ED29
ED30
ED31
32 35
C
C
VSSQ VDDQ
12 9
R42 33 TECLKOUT VSSQ VDDQ
6 3
VSSQ VDDQ
3
3
TP3 TP J17 Y10 R55 33 TEA15

HOLDn ECLKOUT TAECLKOUT2
Y5 TEA13 MT48LC4M32B2TG-6
TARDY ARDY DGND
NEAR DSP V12 ASDWE# R48 33 JUMPER3_SMT JUMPER3_SMT
AWEn/SDWEn/SSWEn TSDWEn
W10 ASDRAS# R45 33
AOEn/SDRASn/SSOEn TSDRASn
TEA2 33 RN8H EA2 Y6 V11 ASDCAS# R47 33 JP500 JP501
EA2 AREn/SDCASn/SSADSn TSDCASn
TEA3 33 RN8G EA3 V7 2M x 32 MT48LC2M32B2TG AB AB
TEA4 33 RN8F EA4 EA3 TP TP5
W7 J18
TEA5 33 RN8E EA5 EA4 HOLDAn TP TP4 4M x 32 MT48LC4M32B2TG BC BC
V8 J19
TEA6 33 RN8D EA6 EA5 BUSREQ
W8
TEA7 33 RN8C EA7 EA6 REV C ADDITION TO SUPPORT 2MX32 OR 4MX32
Y8
TEA8 33 RN8B EA8 EA7
V9
TEA9 33 RN8A EA9 EA8 33 RN12D TCE0n C6713 REQUIRES SDRAM MS ADDRESS BITS
Y9 V17
TEA10 33 RN9H EA10 EA9 ACE0n 33 RN12C
V10 W18 TCE1n CONNECT TO SDRAM BANK BITS. THIS
TEA11 33 RN9G EA11 EA10 ACE1n 33 RN7D
W13 W6 TCE2n DIFFERS FROM THE C64xx WHERE THIS IS
TEA12 33 RN9F EA12 EA11 ACE2n 33 RN7C
V14 V6 TCE3n HANDLED INTERNALLY.
TEA13 33 RN9E EA13 EA12 ACE3n
W14
TEA14 33 RN9D EA14 EA13 33 RN12B
Y14 V20 TBE0n
TEA15 33 RN9C EA15 EA14 ABE0n 33 RN12A
W15 U19 TBE1n
TEA16 33 RN9B EA16 EA15 ABE1n 33 RN7B
Y15 Y4 TBE2n
TEA17 33 RN9A EA17 EA16 ABE2n 33 RN7A
V16 V5 TBE3n
TEA18 33 RN12H EA18 EA17 ABE3n
Y16
TEA19 33 RN12G EA19 EA18
W17
TEA20 33 RN12F EA20 EA19
Y18
TEA21 33 RN12E EA21 EA20
U18
EA21 3.3V
CT13 CT5
FLASH & SDRAM & CONFIG
+ 10 + 10 C73 C75 C95 C97 C74 C45
0.1 0.1 0.1 0.1 0.1 0.1 Title

U10A
TMS320C6713 DSK
TMS320C6713GDP Size Document Number Rev
DGND B C
506732
A-5
A-6
5V
R1
DCISO-4.1V
1
1.6K
D1
LM4040DCIM3-4.1
2
DGND
C13 C28
U4 0.1 0.1 U9
16 16
VCC DGND DGND VCC
2 2 DC_CLKS0
DC_CLKS1 1B1 CLKS0 1B1
3 4 4 3
1B2 1A 1A 1B2
5 5 DC_CLKR0
DC_CLKR1 2B1 U10D CLKR0 2B1
BCLK 6 7 7 6
2B2 2A CLKS1 2A 2B2

11 E1 K3 11 DC_DR0
DC_CLKX1 3B1 CLKR1 CLKS/SCL1 CLKS0/AHCLKR0 DR0 3B1
10 9 M1 H3 9 10
3B2 3A CLKX1 CLKR1/AXR0_6 CLKR0/ACLKR0 3A 3B2
14 L3 G3 14 DC_FSR0
DC_DR1 4B1 DR1 CLKX1/AMUTE0 CLKX0/ACLKX0 FSR0 4B1
13 12 12 13
AIC23SDATAOUT 4B2 4A 4A 4B2
M2 J1
DX1 DR1/SDA1 DR0/AXR0_0
1 L2 H2 1
S DX1AXR0_5 DX0/AXR0_1 S
15 8 8 15
OE GND FSR1 GND OE
M3 J3
FSX1 FSR1/AXR0_7 FSR0/AFSR0
L1 H1
SN74CBT3257PW FSX1 FSX0/AFSX0 SN74CBT3257PW
N1
U3 SCL0 U1
N2
SDA0
16 16
VCC VCC
2 2 DC_CLKX0
DC_DX1 1B1 CLKX0 1B1
3 4 TMS320C6713GDP 4 3 CTL_CLKX0
AIC23SDATAIN 1B2 1A 1A 1B2
5 5 DC_DX0
DC_FSR1 2B1 DX0 2B1
6 7 7 6 CTL_DX0
LRCOUT 2B2 2A 2A 2B2
11 11 DC_FSX0
DC_FSX1 3B1 3.3V FSX0 3B1
10 9 9 10 CTL_FSX0
LRCIN 3B2 3A 3A 3B2
14 14
4B1 4B1
13 12 12 13
4B2 4A 4A 4B2
1 1 CPLD_MCBSP0_MUX
CPLD_MCBSP1_MUX S R49 R46 R44 R43 S
15 8 8 15
OE GND 10K 10K 10K 10K GND OE
SN74CBT3257PW SN74CBT3257PW R18

R12 360
360 DGND
DGND
R27 33
SCL0
DGND DGND
R28 33
SDA0
MCBSP
Title
TMS320C6713 DSK
B A
506732

ENDIAN
DEVICE CONFIGURATION
BOOT-1
BOOT-0
HPI_EN
OFF - OPEN
ON - CLOSED 3.3V
SW3
HD8 iPU 1 8 R85 1K
HD4 iPD 2 7 R86 1K
HD3 iPU 3 6 R87 1K
HD14 iPU 4 5 R3 1K
SW DIP-4/SM
PENCIL SWITCH
DGND
HD12 R29 1K
iPU R30 1K
CLKMODE0
HPI DAUGHTER CARD CAN RESET

U10C
DSP VIA THIS SIGNAL. SIGNAL IS
J1
COMBINED WITH OTHER DSP
B14 HD15 1 2
HD15/GP15 1 2 RESET SOURCES.
C14 HD14 3 4
HD14/GP14 HD13 3 4 3.3V
A15 CLKOUT3 5 6
HD13/GP13 HD12 5 6
C15 7 8
HD12/GP12 HD11 HD1 7 8
A16 9 10
HD11/GP11 HD10 HD3 9 10 HD0
B16 11 12
HD10/GP10 HD9 HD5 11 12 HD2 R19
C16 13 14
HD9/GP9 HD8 HD7 13 14 HD4 10K
B17 15 16
HD8/GP8 HD7 15 16 HD6
A18 17 18
HD7/GP3 HD6 HD8 17 18
C17 19 20
HD6/AHCLKR1 HD5 HD10 19 20 HD9
B18 21 22
HD5/AHCLKX1 HD4 HD12 21 22 HD11 HPI_RESET#
C19 23 24
HD4/GP0 HD3 HD14 23 24 HD13
C20 25 26
HD3/AMUTE1 HD2 25 26 HD15
D18 27 28
HD2/AFSX1 HD1 HDS2n 27 28
D20 29 30
HD1/AXR1_7 HD0 29 30 HASn
E20 31 32
HD0/AXR1_4 HDS1n 31 32
33 34
33 34 HCNTL0
35 36
HINTn HCSn 35 36
J20 37 38
HINTn/GP1 HCNTL1 37 38 HHWIL
G19 39 40
HCNTL1/AXR1_1 HCNTL0 HCNTL1 39 40
G18 41 42
HCNTL0/AXR1_3 HHWIL 41 42 HINTn
H20 43 44
HHWIL/AFSR1 HRWn HRDYn 43 44
G20 45 46
HRWn/AXR1_0 HASn 45 46
E18 47 48
HASn/ACLKX1 HCSn HRWn 47 48
F20 49 50
HCSn/AXR1_2 HDS1n 49 50
E19 51 52
HDS1n/AXR1_6 HDS2n 51 52
F18 53 54
HDS2n/AXR1_5 HRDYn 53 54
H19 55 56
HDRYn/ACLKR1 55 56
57 58
57 58
59 60
59 60
61 62
61 62
63 64
63 64
65 66
TMS320C6713GDP 65 66
67 68 SCL0
67 68
69 70
69 70
71 72 SDA0
71 72
73 74
73 74
75 76
75 76
77 78
77 78
79 80 CLKOUT2
79 80
SFM140L2SDLC
DGND DGND
HOST PORT/McASP
Title
TMS320C6713 DSK
B A
506732
A-7
A-8
TEA[2..21]
DC_D[31..0]
3.3V
3.3V
3.3V DC_A[21..2]
TD[0..31]
U17
42 7 R13 U5
Vcc Vcc 10K
31 18 42 7
Vcc Vcc Vcc Vcc
31 18
TD0 DC_D0 Vcc Vcc
47 2
TD1 1A1 1B1 DC_D1 TEA17 DC_A17 3.3V
46 3 47 2
TD2 1A2 1B2 DC_D2 TEA16 1A1 1B1 DC_A16
44 5 46 3
43 6 44 5
TD4 1A4 1B4 DC_D4 TEA14 1A3 1B3 DC_A14 C17 C15 C16 C14
41 8 43 6
40 9 41 8
38 11 40 9 0.1 0.1 0.1 0.1
37 12 38 11
36 13 37 12
35 14 36 13
TD13 2A2 2B2 DC_D13 TEA8 2A1 2B1 DC_A8 DGND
33 16 35 14
32 17 33 16

30 19 32 17
29 20 30 19
27 22 29 20
TD8 2A7 2B7 DC_D8 TEA3 2A6 2B6 DC_A3 3.3V
26 23 27 22
2A8 2B8 TEA2 2A7 2B7 DC_A2
26 23
2A8 2B8
48
1OE C20 C19 C21 C18
1 48
1DIR 1OE
25 1
2OE 1DIR
24 25 0.1 0.1 0.1 0.1
2DIR 2OE
24
2DIR
4 28
GND GND
10 34 4 28
GND GND GND GND DGND
15 39 10 34
GND GND GND GND
21 45 15 39
GND GND GND GND
21 45
GND GND 3.3V
DGND SN74LVTH16245A DGND SN74LVTH16245A
DGND DGND
C116 C115 C94 C96
3.3V 3.3V
0.1 0.1 0.1 0.1
U16 U6
42 7 42 7 DGND
Vcc Vcc Vcc Vcc
31 18 31 18
Vcc Vcc Vcc Vcc
TD16 47 2 DC_D16 TEA21 47 2 DC_A21
TD17 1A1 1B1 DC_D17 TEA20 1A1 1B1 DC_A20 3.3V
46 3 46 3
44 5 44 5
43 6 43 6
TD20 1A4 1B4 DC_D20 1A4 1B4 C118 C98 C99 C117
41 8 TBE3n 41 8 DC_BE3#
TD21 1A5 1B5 DC_D21 1A5 1B5
40 9 TBE2n 40 9 DC_BE2#
TD22 1A6 1B6 DC_D22 1A6 1B6 0.1
38 11 TBE1n 38 11 DC_BE1# 0.1 0.1 0.1
TD23 1A7 1B7 DC_D23 1A7 1B7
37 12 TBE0n 37 12 DC_BE0#
TD31 1A8 1B8 DC_D31 1A8 1B8
36 13 TCE3n 36 13 DC_CE3#
TD30 2A1 2B1 DC_D30 2A1 2B1
35 14 TCE2n 35 14 DC_CE2#
TD29 2A2 2B2 DC_D29 2A2 2B2 DGND
33 16 TSDCASn 33 16 DC_ARE#
TD28 2A3 2B3 DC_D28 2A3 2B3
32 17 TSDRASn 32 17 DC_AOE#
TD27 2A4 2B4 DC_D27 2A4 2B4
30 19 TSDWEn 30 19 DC_AWE#
TD26 2A5 2B5 DC_D26 2A5 2B5
29 20 DC_ARDY 29 20 TARDY
TD25 2A6 2B6 DC_D25 2A6 2B6
27 22 27 22
TD24 2A7 2B7 DC_D24 2A7 2B7 R15 33
26 23 TAECLKOUT2 26 23 DC_ECLKOUT
2A8 2B8 2A8 2B8
48 R14 48
1OE 1K 1OE
1 1
1DIR 1DIR R403
25 25
2OE 2OE 1K 3.3V
24 24
2DIR 2DIR
4 28 DGND 4 28
GND GND GND GND #OE DIR OPERATION
10 34 10 34
GND GND GND GND
15 39 15 39 L L A <-- B
GND GND GND GND
21 45 21 45 L H A --> B
GND GND GND GND
H X ISOLATION
DGND SN74LVTH16245A DGND DGND SN74LVTH16245A DGND
DC_EMIFA_OE#
DAUGHTERCARD BUFFERING
DC_EMIFA_DIR
DC_EMIFA_DIR =1 FOR WRITES
Title
TMS320C6713 DSK
DC_CNTL_OE# B B
506732

DC_D[31..0]
DC_A[21..2]
5V 5V
-12V 12V
3.3V 3.3V 3.3V 3.3V

External Peripheral Interface External Memory Interface
5V J3 5V J4
2 1 2 1
2 1 DC_A20 2 1 DC_A21
4 3 4 3
4 3 DC_A18 4 3 DC_A19
6 5 6 5
6 5 DC_A16 6 5 DC_A17
8 7 8 7
8 7 DC_A14 8 7 DC_A15
10 9 10 9
10 9 10 9
12 11 12 11
12 11 DC_A12 12 11 DC_A13
14 13 14 13
14 13 DC_A10 14 13 DC_A11
16 15 16 15
16 15 DC_A8 16 15 DC_A9
18 17 18 17
18 17 DC_A6 18 17 DC_A7
20 19 20 19
20 19 20 19
22 21 DC_CLKX0 22 21
DC_CLKS0 22 21 DC_A4 22 21 DC_A5
24 23 DC_FSX0 24 23
DC_DX0 24 23 DC_A2 24 23 DC_A3
26 25 26 25
26 25 26 25
28 27 DC_CLKR0 DC_BE2# 28 27 DC_BE3#
28 27 28 27
30 29 DC_FSR0 DC_BE0# 30 29 DC_BE1#
DC_DR0 30 29 30 29
32 31 32 31
32 31 DC_D30 32 31 DC_D31
34 33 DC_CLKX1 34 33
DC_CLKS1 34 33 DC_D28 34 33 DC_D29
36 35 DC_FSX1 36 35
DC_DX1 36 35 DC_D26 36 35 DC_D27
38 37 38 37
38 37 DC_D24 38 37 DC_D25
40 39 DC_CLKR1 40 39
40 39 40 39
42 41 DC_FSR1 42 41
DC_DR1 42 41 DC_D22 42 41 DC_D23
44 43 44 43
44 43 DC_D20 44 43 DC_D21
46 45 DC_TOUT0 46 45
DC_TINP0 46 45 DC_D18 46 45 DC_D19
48 47 48 47
DC_EINT5 48 47 DC_D16 48 47 DC_D17
50 49 DC_TOUT1 50 49
DC_TINP1 50 49 50 49
52 51 52 51
52 51 DC_D14 52 51 DC_D15
54 53 DC_EINT4 54 53
54 53 DC_D12 54 53 DC_D13
56 55 56 55
56 55 DC_D10 56 55 DC_D11
58 57 58 57
58 57 DC_D8 58 57 DC_D9
60 59 DC_RST# 60 59
60 59 60 59
62 61 62 61
62 61 3.3V 3.3V DC_D6 62 61 DC_D7
64 63 DC_CNTL1 64 63
DC_CNTL0 64 63 DC_D4 64 63 DC_D5
DC_STAT0 66 65 DC_STAT1 66 65
66 65 DC_D2 66 65 DC_D3
DC_EINT7 68 67 DC_EINT6 68 67
68 67 R65 R16 DC_D0 68 67 DC_D1
70 69 70 69
70 69 10K 4.7K 70 69
72 71 72 71
72 71 72 71
74 73 DC_AWE# 74 73 DC_ARE#
74 73 74 73
76 75 DC_DET DC_ARDY 76 75 DC_AOE#
76 75 76 75
78 77 DC_CE2# 78 77 DC_CE3#
DC_ECLKOUT 78 77 78 77
80 79 80 79
80 79 80 79
CONNECTOR 40 X 2 CONNECTOR 40 X 2
DGND DGND DGND DGND

R2 0
DAUGHTERCARD I/F
Title
TMS320C6713 DSK
B A
506732
A-9
5V OPTIONAL, POWER SUPPLY
LOAD RESISTORS, 2512
A-10
BODY
Connect at pin 1
Sets Voltage
R346 R347
NU NU 0.025 OHMS FOR POWER
MEASUREMENT R10
3.74K 1%
SYSTEM POWER MEASUREMENT AGND R11 C36

DGND DGND POINTS. R IS 2512 BODY, 6 VIAS R31 3.3 sq in AGND, min 2K 1% 8200pF 3.3V
FROM PAD TO PLANE C65 C66 thermal pad
71.5K 1% C12
0.1uF 0.039uF U7 470pF 3300pF 107 1%
21 C37 R20 R38 TP1
POWERPAD
20 1
RT AGND 10K 1% 10K TP
19 2
SYNC VSENSE R21
POWER INPUT 18 3
5V L4 SS/ENA COMP
17 4 SVS_RST#
J5 0 VBIAS PWRGD C10
5
R99 BOOT 3.3V C127
CENTER 16
VIN3 0.047uF DSPIO_3.3V
SHUNT 15
BLM41P750SPT CT9 VIN2 L3 NO-POP
SLEEVE 14 6
+ CT16 C63 + C64 VIN1 PH1 2.7 uH

R52 7
2.5 MM JACK 47uF 0.1uF PH2 CT4 C11 3.3V @1.5Amp Max
180 13 8 DSPIO_3.3V
RASM712 10uF LESR 0.1uF PGND3 PH3 + D12
12 9
PGND2 PH4 0
11 10
PGND1 PH5
1
2
100uF 4V 1000pF MURS120T3 R66 TP31
TP
TPS54310PWP CT15
JP4 D3 +
NO-POP D13 100 uF
GREEN
MURS120T3 0.025 OHMS FOR POWER
1
2
EMI SUPPRE SION. LOCATE NEAR EACH REGULATOR. NO-POP MEASUREMENT
TP32
6 VIAS FROM PAD TO PLANE OR DIRECT TIE. 1.26V -> 24.3K 1% OPTIONAL CROSS COUPLE
1.2V -> 28.0K 1% DSP POWER MEASUREMENT
1 Connect at pin 1 D14
JP2 POINT S. R IS 2512 BODY, 6 VIAS
TestPoint FROM PAD TO PLANE
DGND MURS120T3
JP1
R6
24.3K 1%
J6 D15
-12V 12V R9 AGND R5 C4
1
2
3.3 sq in AGND, min 1.65K 1% 0.01uF MURS120T3 NO-POP

4 C6 C8 thermal pad DSP_CVDD
+5 TO BE POPULATED BY 71.5K C2 MURS120T3
3
GND 0.1uF 0.039uF U2 560pF D16
2 THE USER IF
-12 C5 R8 0 DSP_CVDD
1 NEEDED. 21
+12 POWERPAD 3300pF 107 1% R4
20 1
RT AGND TP2
19 2
NU SYNC VSENSE R7 SENSE_DSP_CVDD TP
18 3
Molex 53-109-0410 L2 SS/ENA COMP 10K 1% CT1
17 4
VBIAS PWRGD C3 +
5
BOOT 100 uF
16
VIN3 0.047uF 1.26V @1.5Amp Max
WARNI NG: 15
BLM41P750SPT CT3 VIN2 L1
14 6
DO NOT SUPPLY POWER TO BOTH C9 + C7 VIN1 PH1 2.7 uH
7
0.1uF PH2
POWER CONNECTORS AT THE 13 8
10uF LESR 0.1uF PGND3 PH3 + CT2 C1
12 9
SAME TI ME! PGND2 PH4 100uF 4V 1000pF
11 10
PGND1 PH5
TPS54310PWP
EACH REGULATOR CAN SUPPLY UP TO 3A OF

DAUGHTERCARD STANDOFF GROUNDING CURRENT. HOWEVER COMPONENT VALUES
HAVE BEEN SELECTED FOR 1.5A OPERATION.
M1 M2 M3 M4
125_PH 125_PH 125_PH 125_PH VALUES CALCULATED WITH SWIFT DESIGN TOOL 2.0.
KEEP TRACES A MINIMUM FOLLOW TPS54310 EVM LAYOUT

OF 0.070 INCHES FROM
THESE HOLES.
POWER
Title
DGND TMS320C6713 DSK
B B
506732

DSP_CVDD DSPIO_3.3V
U10G U10H U10I
A4 A17 A1 P19
CVDD DVDD VSS VSS
A9 B3 A2 T4
CVDD DVDD VSS VSS
A10 B8 A11 T17
CVDD DVDD VSS VSS
B2 B13 U10J A14 U4
CVDD DVDD VSS VSS
B19 C10 A19 U8
CVDD DVDD VSS VSS
C3 D1 A5 A20 U9
CVDD DVDD RSV VSS VSS
C7 D16 B5 B1 U13
C18 D19 C12 B4 U17
D5 F3 D7 B15 U20
D6 H18 D12 B20 W1
D11 J2 A12 C6 W5
D14 M18 B11 C8 W11
CVDD DVDD R60 RSV VSS VSS
D15 R1 C9 W16
CVDD DVDD 10K VSS VSS
F4 R18 D4 W20
CVDD DVDD VSS VSS
F17 T3 TMS320C6713GDP D8 Y1
CVDD DVDD VSS VSS
K1 U5 D13 Y2
CVDD DVDD VSS VSS
K4 U7 D17 Y13
CVDD DVDD VSS VSS
K17 U12 E2 Y19
CVDD DVDD DGND VSS VSS
L4 U16 E4 Y20
CVDD DVDD VSS VSS
L17 V13 E17
CVDD DVDD VSS
L20 V15 F19
CVDD DVDD VSS
R4 V19 G4
CVDD DVDD VSS DGND
R17 W3 G17
CVDD DVDD VSS
U6 W9 H4
CVDD DVDD VSS
U10 W12 H17
CVDD DVDD VSS
U11 Y7 J4
CVDD DVDD VSS
U14 Y17 J9
CVDD DVDD VSS
U15 J10
CVDD VSS
V3 TMS320C6713GDP J11
CVDD VSS
V18 J12
CVDD VSS
W2 K2
CVDD VSS
W19 K9
CVDD VSS
K10
VSS
TMS320C6713GDP K11
VSS
K12
VSS
K20
All capacitors on this sheet are decoupling capacito rs for the DSP. They should be placed as close as possible to the DSP. VSS
L9
DSP_CVDD VSS
L10
VSS
L11
VSS
L12
DSP_CVDD VSS
M4
CT14 CT11 C30 C32 C105 C108 C50 C46 C23 C25 C34 C58 C88 C112 C110 C104 C101 C52 C54 C56 C85 C83 C81 C27 VSS
M9
+ 10 + 10 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 VSS
M10
VSS
M11
VSS
M12
VSS
M17
VSS
N4
VSS
N17
VSS
P4
DGND C77 C79 VSS
P17
0.1 0.1 VSS
TMS320C6713GDP
DGND
DGND
DSPIO_3.3V
DSPIO_3.3V
CT6 CT8 C24 C29 C33 C62 C90 C109 C35 C100 C106 C103 C102 C78 C80 C47 C48 C59
+ 10 + 10 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1
DGND
C41 C26 C31 C51
0.1 0.1 0.1 0.1
DSP POWER & DECOUPLING

DGND Title
TMS320C6713 DSK
B A
506732
A-11
42 RN2C
DSP_EMU0
A-12
DSP JTAG HEADER 42 RN2D
42 RN2A
DSP_EMU1
42 RN2B
42 RN2E
DSP_EMU2
3.3V 3.3V 42 RN2F
DSP_EMU3
42 RN2G
DSP_EMU4
J8 ROUTE TRACES AS 42 RN2H
DSP_EMU5
1 2 R88
1K
ONE GROUP. MATCH
3 4
XDS_TVD 5 SIGNAL LENGTH.
7 8 3.3V
9 10
11 12
13 14 R94
LOCACTE R-PACK NEAR DSP 30.1K
HEADER 7x2, Emulation DGND J7
C2 A1 HURRICANE_DETn
EMU18 GND
B3 A2
JTAG MULTI PLEXERS EMU17 GND C125
C4 A3
EMU16 GND
C5 A4
5V EMU15 GND
B5 A5 0.1
R93 EMU14 GND
C6 A6
XDS_4.1V EMU13 GND
B6 A7
XDS_4.1V EMU12 GND

C7 A8 DGND
1
1.6K C123 EMU11 TYPE0
C9 A9
D5 EMU10 GND
B9 A10
LM4040DCIM3-4.1 0.1 EMU9 GND
C10 A11
EMU8 GND
B10 A12
EMU7 GND
C11 A13
EMU6 GND
2
DGND HUR_EMU5 B11 A14
HUR_EMU4 EMU5 GND
C12 A15
HUR_EMU3 EMU4 GND
C13
HUR_EMU2 EMU3
B13 D1
HUR_EMU1 EMU2 GND
C14 D2
3.3V DGND HUR_EMU0 EMU1 GND
B14 D3
EMU0 GND
C8 D4
R67 U19 TCKRTN GND
B12 D5
47K TCLK GND
16 B7 D6
XDS_TDO VCC TDO GND
2 B4 D7
T_TDO 1B1 TDI GND
3 4 B2 D8
T_TDO XDS_TDI 1B2 1A TMS TYPE1
5 C3 D9
T_TDI 2B1 TRSTn GND
6 7 C15 D10
T_TDI XDS_TMS 2B2 2A ID3 GND
11 C1 D11
T_TMS 3B1 ID2 GND
10 9 B15 D12
T_TMS XDS_TRST# 3B2 3A 3.3V ID1 GND
14 B1 D13
T_TRSTn 4B1 R91 1K ID0 GND
13 12 B8 D14
T_TRSTn 4B2 4A DSP_TRST# TVD GND
D15
GND
1
3.3V S DSP_TMS HEADER 4x15
15 8
OE GND DGND DGND
SN74CBT3257PW DSP_TDI
U18 DGND R100 3.3V
33 DSP_TDO
5
SN74AHC1G14
U26
HURRICANE_DETn 2 4
5
SN74LVC1G32
1
4 R96
DSP_TCK
3
2 33
3
3.3V
DGND 3.3V C124
U25 .1uF
R90 16
47K XDS_EMU0 VCC DGND
2
T_EMU0 1B1 MUX_EMU0 DGND
3 4
T_EMU0 XDS_EMU1 1B2 1A
5
5
T_EMU1 2B1 MUX_EMU1 U24

6 7
T_EMU1 XDS_TCK 2B2 2A
11 1
T_TCK 3B1 HUR_TCK R92
10 9 4
T_TCK XDS_TCKRET 3B2 3A 33
14 2
T_TCK_RET 4B1 HUR_TCKRTN SN74LVC1G32
13 12
T_TCK_RET 4B2 4A
3
1 DGND
3.3V S
U23 15 8
OE GND C126
5
5
U22 SN74CBT3257PW R95
R89 D4 1 DGND 100 1% DGND
4 4 2
EMULATION
2 SN74AHC1G14 22pF
DGND
C122 150 LTST-C150GKT SN74LVC1G32
3
3
USB IN USE Title
.1uF
TMS320C6713 DSK
DGND Size Document Number Rev
B A
DGND
506732

5 4 3 2 1
3.3V
C67
.1uFDGND
U11
5
D D
1 CLK_12MHZ
R32 4
CODEC_CLK 33 2
SN74LVC1G32
3
DGND
3.3V USB/Emulation 5V
AIC23 Audio 5V
CODEC_SYSCLK 3.3V
T_TRSTn T_TRSTn
3.3V
BCLK DATA_BCLK T_TCK T_TCK
LRCIN DATA_SYNCIN PONRSn T_TMS T_TMS
SVS_RST#
AIC23SDATAIN DATA_DIN AIC3.3V T_TDI T_TDI
C AIC23SDATAOUT DATA_DOUT T_TDO T_TDO C
LRCOUT DATA_SYNCOUT T_EMU0 T_EMU0
T_EMU1 T_EMU1
USB_DSP_RST# USB_DSP_RST#
CTL_DX0 CTL_DATA
CTL_CLKX0 CTL_CLK
CTL_FSX0 CTL_CS GND CLK_12MHZ T_TCK_RET T_TCK_RET
AIC23 Audio
CLK_24MHZ
GND
DGND
USB/Emulation DGND
B B
A A
Hierarcharical Blocks
Title
TMS320C6713 DSK
B A
506732
5 4 3 2 1
A-13
A-14 TMS320C6713 DSK Module Technical Reference

Appendix B
Mechanical Information
This appendix contains the mechanical information about the

TMS320C6713 DSK produced by Spectrum Digital.
B-1
THIS DRAWING IS NOT TO SCALE
B-2 TMS320C6713 DSK Module Technical Reference

Printed in U.S.A., November 2003
506735-0001 Rev. B

dsk6713 TechRef

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

dsk6713 TechRef

Uploaded by

Copyright:

Available Formats

TMS320C6713 DSK

2003 DSP Development Systems

SPECTRUM DIGITAL, INC.

Copyright © 2003 Spectrum Digital, Inc.

1 Introduction to the TMS320C6713 DSK Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1

This document uses the following conventions.

The TMS320C6713 DSK will sometimes be referred to as the DSK.

Information About Cautions

This book may contain cautions.

Texas Instruments TMS320C67xx DSP CPU Reference Guide

Chapter One provides a description of the TMS320C6713 DSK along

Host Port Int

Figure 1-1, Block Diagram C6713 DSK

• A Texas Instruments TMS320C6713 DSP operating at 225 MHz.

• An AIC23 stereo codec

• 16 Mbytes of synchronous DRAM

• 512 Kbytes of non-volatile Flash memory (256 Kbytes usable in default

• 4 user accessible LEDs and DIP switches

• Software board configuration through registers implemented in CPLD

• Configurable boot options

• Standard expansion connectors for daughter card use

• JTAG emulation through on-board JTAG emulator with USB host

• Single voltage power supply (+5V)

1.3 Basic Operation

1) Connect the included power supply to the DSK.

3) Launch Code Composer from its icon on your desktop.

1-4 TMS320C6713 DSK Module Technical Reference

1.4 Memory Map

Figure 1-2, Memory Map, C6713 DSK

1.5 Configuration Switch Settings

Table 1: Configuration Switch Settings

Switch 1 Switch 2 Switch 3 Switch 4 Configuration Description

1.6 Power Supply

1-6 TMS320C6713 DSK Module Technical Reference

This chapter describes the operation of the major board components on

2.1 CPLD (Programmable Logic)

The C6713 DSK uses an Altera EPM3128TC100-10 Complex Programmable Logic

• 4 Memory-mapped control/status registers that allow software

• Control of the daughter card interface and signals.

• Assorted "glue" logic that ties the board components together.

2.1.1 CPLD Overview

2-2 TMS320C6713 DSK Module Technical Reference

2.1.2 CPLD Registers

The 4 CPLD memory-mapped registers allows users to control CPLD functions in

Table 1: CPLD Register Definitions

0 USER_REG USR_SW3 USR_SW2 USR_SW1 USR_SW0 USR_LED3 USR_LED2 USR_LED1 USR_LED0

1 DC_REG DC_DET 0 DC_STAT1 DC_STAT0 DC_RST 0 DC_CNTL1 DC_CNTL0

4 VERSION CPLD_VER[3.0] 0 BOARD VERSION[2.0]

6 MISC SCR_5 SCR_4 SCR_3 SCR_2 SCR_1 FLASH_PAGE McBSP1 McBSP0

2.1.3 USER_REG Register

Table 2: CPLD USER_REG Register

Bit Name R/W Description

7 USER_SW3 R User DIP Switch 3(1 = Off, 0 = On)

2.1.4 DC_REG Register

Table 3: DC_REG Register

Bit Name R/W Description

7 DC_DET R Daughter Card Detect (1= Board detected)

2.1.5 VERSION Register

Table 4: Version Register Bit Definitions

Bit # Name R/W Description

7 CPLD_VER3 R Most Significant CPLD Version Bit

2-4 TMS320C6713 DSK Module Technical Reference