Scaling of High Aspect Ratio Current

Limiters for the Individual Ballasting of

Large Arrays of Field Emitters
Stephen A. Guerrera
Luis F. Velasquez-Garcia
Akintunde I. Akinwande
guerrera@mit.edu
RQE Presentation
11/01/2011
RQE - 11/1/2011
Overview

Introduction and Motivation

Modeling and Simulation

Device Fabrication

Device Characterization and Analysis

Conclusions
2
RQE - 11/1/2011
Overview

Introduction and Motivation

Modeling and Simulation

Device Fabrication

Device Characterization and Analysis

Conclusions
3
RQE - 11/1/2011
Motivation
Many applications require compact, efcient electron sources
4
!"#$ %& ()*+ ,-.+ /000
1,2,+ 1345 63+ 7889
5* :;<=>()%+ ?* #@ A)(=B#C
D$%)> 3E$==$#F !#;G#;(&$#F
CCC*%H%(E>%I$J%=*J#E
Multi e-beam lithography Portable Vacuum Sources X-rays
Displays Terahertz Devices Ionizers/
Neutralizers
RQE - 11/1/2011
Physics of Electron
Sources
5
E
F

e
-
metal vacuum
E
F
e
-
metal
vacuum
E
x
x
V(x>0) = -qFx
(a) (b)
W

0 0
E
x
E
x
x = 0 x
Thermionic or Photoemisssion Field Emisssion
RQE - 11/1/2011
Physics of Electron
Sources
6
E
F

e
-
metal vacuum
E
F
e
-
metal
vacuum
E
x
x
V(x>0) = -qFx
(a) (b)
W

0 0
E
x
E
x
x = 0 x
Thermionic or Photoemisssion Field Emisssion
RQE - 11/1/2011
Field Emission Physics:
A two step process

Spindt Approximations to the Fowler-Nordheim Model:

7
2D Fermi sea of electrons
J=qnv

F
E
f

e-
E
c

Flux of electrons
to the surface


Transmission of
electrons through
the barrier

!
J = q N(E
x
)D(F, E
x
)
E
C
!
"
dE
x
J =
AF
2
1.1!
exp
B!1.14"10
7
!
1/2
#
$
%
&
'
(
exp )
0.95! B! !
3/2
F
#
$
%
&
'
(
RQE - 11/1/2011
Schematic Cross-section of a
Microfabricated Field Emitter
8

Sharp emitter tips are

required for emission because
of the large electric elds
required for eld emission

Field enhancement results at

the tip from solutions to
Laplaces equation

In general, a self-aligned
structure is preferred for
maximum transmission
Emitter
Cone
Si
Substrate
Poly-Si
extraction
gate
Anode
Emitted
Electrons
RQE - 11/1/2011
Ball-In-Sphere
Electrostatics Model
9

Simple analytical model to describe the

electrostatics of a eld emitter with a
proximal gate

Boundary value problem readily evaluated

in spherical coordinates to obtain the
magnitude of the electric eld:

From this, an expression for the eld

factor, !, is obtained:
Emitter
Cone
D
R
Poly-Si
extraction
gate
F(r) =V
0
D! R
D" R
1
r
2
! =
D
D! R
1
R
RQE - 11/1/2011
Scaling
10

All dimensions reduced by

scaling factor s

Assume current density

constant

Cross-sectional area
decreases

Packing density increases by

same amount

To rst order, no net change

in current density for the
array
RQE - 11/1/2011
Benets of Scaling
FEA Dimensions

Denser packing of eld emitters

More redundancy for a given array size

Higher current density and overall emission

current possible by increasing doping

More uniform emission current

Smaller aperture, allowing for higher eld

factor, lower turn on voltage

Smaller energy distribution

11
RQE - 11/1/2011 RQE - 11/1/2011
Tip Radii Statistical
Distribution
12
0 100 200 300 400 500
10
14
10
12
10
10
10
8
GatetoEmitter Voltage, V
GE
[Volts]
E
m
i
s
s
i
o
n

C
u
r
r
e
n
t
,

I
E

[
A
]


Burn out limit
r
o
=40 nm

M. Ding et al, TED 2002
Tip radii follow a log-
normal or Gaussian
distribution (long tails)
Array sub-utilization and
damage due to Joule
heating and burnout
RQE - 11/1/2011
Tip Radii Statistical
Distribution
13
M. Ding et al, TED 2002
0 100 200 300 400 500
10
14
10
12
10
10
10
8
GatetoEmitter Voltage, V
GE
[Volts]
E
m
i
s
s
i
o
n

C
u
r
r
e
n
t
,

I
E

[
A
]


Burn out limit
r
o
=10 nm
o=1.25 nm
Tip radii follow a log-
normal or Gaussian
distribution (long tails)
Array sub-utilization and
damage due to Joule
heating and burnout
RQE - 11/1/2011
Individual Current Limiters
Allow Higher Overall Current
14
RQE - 11/1/2011
Load-Line Analysis of
Supply Control
15
tip radius: r
1
< r
2
< r
3
V
I
I
V
I
V
I
Passive Resistance
Dynamic Resistance
tip radius: r
1
< r
2
< r
3
V
I
V
Slope = 1 / R
Slope = 1 / R
o

Pure resistors ! Simultaneous high current and low current

dispersion not possible (or at least very hard)

Current sources ! Simultaneous high current and low current

dispersion possible
RQE - 11/1/2011
V
I
V
I
I
Passive Resistance
Dynamic Resistance
V
I
V V
I
Scaling
Load-Line Analysis of
Supply Control
16

Pure resistors ! Simultaneous high current and low current

dispersion not possible (or at least very hard)

Current sources ! Simultaneous high current and low current

dispersion possible
RQE - 11/1/2011
Individually Ballasted
FEA-FET Structure
17


VCT
n-Silicon Substrate


V
G
= V
GE
+ V
DS
Si Pillar
Ungated
FET
Si Field
Emitter
D
S
V
GE
V
DS
E
G
A
Gate
Anode
V
GS
V
AS
Oxide Dielectric
Fill / Void

In the linear regime, the potential varies linearly along the

length of the channel

A linear conductance can be dened

Above a critical eld, the velocity of electrons saturates, and

a depletion region forms at the drain end of the channel

Additional voltage applied is dropped across the depletion

region

Output conductance arises from channel length modulation

RQE - 11/1/2011
Vertical Ungated FET
Operation
18
I
D
= qAn
e
dV (x)
dx

qAn
e
V
DS
L
G
LIN
=
qAn
e
L
Anode
Gate
Field
Emitter
Ungated
FET
V
DS
V
GE
V
GS
V
AS
+

+
+

S
D
G
E Emitter
Drain
Source
Anode
Gate
n-type Silicon Substrate
x = 0
x = L
S
i
l
i
c
o
n

P
i
l
l
a
r
O
x
i
d
e

/

D
i
e
l
e
c
t
r
i
c

F
i
l
l
Emitter
(a) (b)
I
D

= I
DSS
[1 +V
DS
] = I
DSS
+G
OUT
V
DS
I
D
=
qA(x)n
e

1 +

e
v
sat

dV (x)
dx

2
dV (x)
dx
RQE - 11/1/2011
Prior Work
19
!
"!
#!
$!
%!
&!!
&"!
&#!
&$!
&%!
"!!
! "!! #!! $!! %!! &!!! &"!! &#!! &$!!
E
m
i
s
s
i
o
n

C
u
r
r
e
n
t

I
E
[
m
A
]
Gate VoItage V
G
[V]
(Linear) IV - 3kV Power SuppIy / 1k Resistor
&$!!'
&#!!'
&"!!(
Geometry
Parameters:
Pillar dimensions:
1!m x 1!m x 100
!m
Pitch: 10!m
Tip radius: <50nm
N
D
: 2.5x10
13
cm
-3
Pulse
Parameters:
10!s pulse width
and 10s period
Velsquez-Garca et al. TED 2011
RQE - 11/1/2011
Overview

Introduction and Motivation

Modeling and Simulation

Device Fabrication

Device Characterization and Analysis

Conclusions
20
RQE - 11/1/2011
Scaled Vertical Ungated
FET Simulation Results

Geometry:

100 nm x 100 nm x 10 !m

N
D
= 5x10
14
cm
-3

L ! " I
DSS
#, r
lin
!, r
o
!

Simulations performed using SILVACO

toolset

Full Si Process Simulator (ATHENA)

Poisson equation and continuity

equation solver in Silicon (ATLAS)
21
RQE - 11/1/2011
Scaled Vertical Ungated
FET Simulation Results

Geometry:

100 nm x 100 nm x 10 !m

100:1 Aspect Ratio

N
D
! " I
DSS
!, r
lin
#, r
o
#
22
RQE - 11/1/2011
Scaled Vertical Ungated
FET Simulation Results

Doping density: 2x10

14
cm
-3

Aspect ratio: 100:1 (100 nm x 100 nm x 10 !m)

Chosen to yield 1 nA/tip

Thus 0.1-1.0 A/cm

2
for 1 um pitch
23
RQE - 11/1/2011
Overview

Introduction and Motivation

Modeling and Simulation

Device Fabrication

Device Characterization and Analysis

Conclusions
24
RQE - 11/1/2011
Fabrication of Si
FEA-FETs
25
Photolithography
to define dots
a)

b)

c)

SiO
2

Si PR
e)
PR Removal,
oxidation sharpening
and oxide removal
d)

Rough tip formation and
pillar formation
Grow oxide
hardmask
RIE
to pattern hardmask
RQE - 11/1/2011
Completed FEA-FET
Structure
26
100 nm
Pillar Height: 10!m
Pillar Diameter: 0.11!m
Tip Radius: < 10nm
Pitch: 5!m
RQE - 11/1/2011
Overview

Introduction and Motivation

Modeling and Simulation

Device Fabrication

Device Characterization and Analysis

Conclusions
27
RQE - 11/1/2011
Current-Voltage Characterization
of Ungated FETs Without Emitters
28
# of
Pillars
I
DSS
/pillar
[pA]
V
DSS
[V]
G
LIN
/pillar
[pS]
G
O
/pillar
[pS]
1 8.5 0.057 150 0.33
4M 4.65 0.047 100 0.065
Single FET 4M FET Array
RQE - 11/1/2011
Field Emission
Characterization Setup
29
Ball anode
Insulating
polymer
spacer
Device
under
test
Clamp
Probe
Perforated
extraction grid
Schematic
Cross-section
Device
Photo
+1100 V
+V
GS
0 V
RQE - 11/1/2011
Field Emission I-V
Characterization
30
1.0E-13
1.0E-11
1.0E-09
1.0E-07
1.0E-05
1.0E-03
0 100 200 300 400 500 600 700
I

(
A
)

V
G
(V)
y = -2942.6x - 19.204
R = 0.9907
y = -3142.5x - 23.588
R = 0.98148
-35
-33
-31
-29
-27
-25
-23
-21
0.001 0.002 0.003 0.004 0.005 0.006
L
N
(
I
/
V
G
2
)

1/V
G
Anode Gate
b
FN
3143 2942
(cm
-1
) 1.69x10
5
1.80x10
5
r (nm) 59 nm 55 nm
-b
FN
Gate
Anode Anode
Gate
r
1

0.95 6.8310
7

3/2
b
FN
V
A
= +1100 V
4.05 eV
RQE - 11/1/2011
Field Emission I-V
Characterization
31
-35
-33
-31
-29
-27
-25
-23
-21
0.001 0.002 0.003 0.004 0.005 0.006 0.007
L
N
(
I
/
V
G
2
)

1/V
G
1.0E-13
1.0E-11
1.0E-09
1.0E-07
1.0E-05
1.0E-03
0 100 200 300 400 500 600 700 800 900
I

(
A
)

V
G
(V)
Gate
Ballasting?
Anode Gate
b
FN
3143 2942
(cm
-1
) 1.69x10
5
1.80x10
5
r (nm) 59 nm 55 nm
Anode
Anode
Gate
r
1

0.95 6.8310
7

3/2
b
FN
V
A
= +1100 V
4.05 eV
RQE - 11/1/2011
Analysis of Field
Emission Data

Array size: 1.36 M emitters

! (from 2-D electrostatic simulations of the structure in COMSOL):

1.34x104 cm
-1
.

Sensitivity analysis:

! (spacing reduced to 12.5 !m): 5.84x10

4
cm
-1

! (tip radius reduced to 2.5 nm): 1.81x10

4
cm
-1

Saturation current (expected), I

sat
: ~1.3 mA (current of ~1 nA/emitter)

Current saturation voltage, V

GSS
, extrapolated from F-N curve: ~1.5
kV

Upper bound on array burnout current (from failure analysis of

individual vertical ungated FETs and heating analysis): ~10 A
32
RQE - 11/1/2011
Overview

Introduction and Motivation

Modeling and Simulation

Device Fabrication

Device Characterization and Analysis

Conclusions
33
RQE - 11/1/2011
Conclusions

Successfully demonstrated the fabrication of

vertical ungated FETs with dimensions of
100nm x 100nm x 10um with 1 micron pitch

This is the smallest, most dense array of

vertical ungated FETs ever reported

Demonstrated eld emission and ballasting

from Si emitters on top of scaled vertical
ungated FETs with ve micron pitch, with
current density greater than 100 !A/cm
2
.
34
RQE - 11/1/2011 35
RQE - 11/1/2011
Backup Slides
36
RQE - 11/1/2011
Future Work

Devices with higher doping density should be built to

ensure higher currents can be obtained.

Better planarization / trench-lling techniques need

to be explored

A process for integrated, self-aligned gates needs to

be adapted and developed for the FET-FEA structure

More complete analysis of the tip radius distribution

Lifetime analysis

Adapting the FEA-FET structure to real applications

37
RQE - 11/1/2011
Field Emission Requires
Large Electric Fields
38
10
7
10
8
10
9
10
10
10
8
10
6
10
4
10
2
10
0
F [V/cm]
T
r
a
n
s
m
i
s
s
i
o
n

P
r
o
b
a
b
i
l
i
t
y
RQE - 11/1/2011
Preliminary Tip Radius
Distribution
39
RQE - 11/1/2011
Additional Hi Res Tip
SEMs
40
RQE - 11/1/2011 41
!"#"$%&%# '"()%
!
"
#$%&
%'
)*
+,
- %& .*
/ !01& 2*3
#
4
"55
&6#7% 2/
8
"55
&6&,9 8
:
-4!
;67, 25
:
<=>
#61? @5
Axisymetric Simulation
of Vertical Ungated FETs
RQE - 11/1/2011
Thermal Failure
Analysis
42
!
"
#!
#"
$!
$"
%!
%"
&!
&"
"!
#'!!()#% #'!!()#$ #'!!()## #'!!()#! #'!!()!* #'!!()!+ #'!!()!, #'!!()!-
I
D
(A)
V
D
S

(
V
)
!"!!#$!!
%"!!#&'(
'"!!#&')
'"%!#&')
)"!!#&')
)"%!#&')
("!!#&')
("%!#&')
! !") !"* !"+ !", ' '") '"* '"+ '", )
!
"
#
$
%
&"' #&%
!"#$$%!"&
!'#$$%!"(
$#$$%)$$
'#$$%!"(
"#$$%!"&
"#'$%!"&
&#$$%!"&
$ " & ( * ' + , - . "$
Before Stressing
After Stressing
Failure
i
max
= (2T
m
ok)
1/2
/h (A/cm
2
)
I
max
(theoretical) = 1x10
-7
A
(approach based on Utsumi IVMC '91)
~
Microscope image afer stressing
RQE - 11/1/2011
Field Emission
Characterization Setup
43
Ball anode
Insulating
polymer
spacer
Device
under test
Perforated
extraction
grid
RQE - 11/1/2011
Field Emission
44
( )
( )
2
7
3/ 2
2
1/ 2
1.44*10
0.95
exp exp
1.1
n
n
TIP G
G
k
A
B
B r
r
I V
kV
o


~
| |
| |
| | = ~
| |
| |
| |
| |

!
2D Fermi sea of electrons
J=qnv

F
E
f

e-
E
c

Flux of electrons
to the surface


Transmission of
electrons through
the barrier
RQE - 11/1/2011
Electrostatics Simulations:
! for devices with 1"m Pitch
45
0
500
1000
1500
2000
2500
3000
3500
0
2000
4000
6000
8000
10000
12000
14000
16000
18000
20000
0 2 4 6 8 10
Distance Above Substrate [microns]
[cm
-1
]
Turn on voltage [V]
RQE - 11/1/2011
COMSOL Field
Enhancement Simulation
46
Zero charge / symmetry boundary
+V
G
GND
Example Simulation Result

Solving the Laplace

equation

Field emitter: 30 cone

angle with 5 nm or
2.5 nm radius

Pillar width: 100 nm

Pillar height: 10 !m

Pitch: 5 !m

# of Emitters: 5

Anode separation: 25 nm,

12.5 nm

Maximum eld measured

at right-most eld
emitter
RQE - 11/1/2011
COMSOL Field
Enhancement Simulation
47

Solving the Laplace

equation

Field emitter: 30 cone

angle with 5 nm or
2.5 nm radius

Pillar width: 100 nm

Pillar height: 10 !m

Pitch: 5 !m

# of Emitters: 5

Anode separation: 25 nm,

12.5 nm

Maximum eld measured

at right-most eld
emitter
Tip Meshing Detail
(a) (b)
RQE - 11/1/2011
Energy Distribution of
Emitted Electrons
48
!=12.5x10
5
/r
0.7
r
o
=30x10
-7
d
r
=3x10
-7

RQE - 11/1/2011
Energy Distribution of
Emitted Electrons
49
!=62.5x10
5
/r
0.7
r
o
=30x10
-7
d
r
=3x10
-7