Chapter 5.

Arithmetic Circuits

Representation of signed numbers of base r

1) Signed magnitude (aka, sign & magnitude) 2) rs complement (2s complement in binary) 3) (r-1)s ( 1)s complement mpl m t (1s complement mpl m t in i binary) bi )

Signed magnitude
Hum n f i ndl way: Human-friendly : + 14 - 56
sign (+,-) magnitude

Generally, MSB (Most Significant Bit) is used as the sign Generally bit (0 = plus, 1 = minus) n-bits n bits number
-(2n-1 - 1) ~ +(2n-1 - 1) two p presentations of zero (+0, -0)

Representation
magnitude
2

sign bit

(ex) 4 bit numbers

Signed magnitude it d 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Decimal +0 +1 +2 +3 +4 4 +5 +6 +7 -0 -1 1 -2 -3 -4 -5 -6 6 -7
3

(r-1)s complement
n-digit di it positive iti number b Ni in b base r (r-1)s complement of N= (rn 1) - N ( ) 9 (ex) 9s complement l t of f 52520
99999 105 -1 -52520 52520 47479

1s complement (for binary number system)

1s 0s 1 s are changed to 0 s and 0s 0 s to 1s 1s

(ex) 1s complement of 101100

111111 -101100 010011

Representation

sign i bit

m nitud (1s magnitude (1 s c complement mpl m nt if negative) n tiv )

n-bit numbers
-( 2n-1- 1 ) ~ +( 2n-1 - 1 ) two representations of zero (+0, -0)

(ex) 4 bit numbers

1s complement 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Decimal +0 +1 +2 +3 +4 +5 +6 +7 -7 -6 -5 -4 -3 -2 -1 -0

symmetric

rs complement
n-digit positive number N in base r rs complement of N = rn N for N 0 (ex) 10s complement of 52520
100000 105 -52520 47480

for N = 0

2s complement (for binary number system)

(1s (1 s complement) mpl m nt) + 1

(ex) 2s complement of 101100 = 010011 + 1 =010100

100000 -101100 010100
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Representation

sign i bit

m nitud (2s magnitude (2 s complement c mpl m nt if negative) n tiv )

n-bit numbers
-(2n-1) ~ +(2n-1 - 1) Only one zero (+0) 1 no positive Extra E t negative ti # : - 2n-1 iti counterpart t t

(ex) 4 bit numbers

2s complement 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Decimal +0 +1 +2 +3 +4 +5 +6 +7 -8 -7 -6 -5 -4 -3 -2 -1
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1) Signs Si are the h same

Signed magnitude addition

Add the magnitudes Give the result same sign Compare magnitudes (l (larger one) ) (smaller ( ll one) ) Give the result sign of the larger

1100 (-4) + 1011 (-3) 1111 ( (-7) )

( 4) 1100 (-4) + 0011 (+3) 1001 (-1)

2) Signs are different

Signed magnitude subtraction

Change sign of subtrahend Add with minuend addition ( ) (ex)
0011 (+3) 0011 (+3) 1100 (-4) + 0100 (+4) 0111 (+7) 0011 (+3) 0011 (+3) 0100 (+4) + 1100 (-4)
Additi rule Addition l
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complicated

Very complicated

1s complement addition
Add i including l di sign i bit Take the carry out and add it to the sum
(ex) 4 bit
3 +4 7

0011 0100 0111

4 + -7 -3

0100 1000 1100

5 + -5 0

0101 1010 1111

0 + -0 0

0000 1111 1111

cf: x + (-x) = -0, (+0) + (+0) = +0

-2 + -3 -5

1101 1100 11001 1 1010

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If a carry out of MSB, MSB add it to the sum

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Overflow is said to occur if an addition produces a result that exceeds the range of the number system Overflow occurs when two numbers of the same sign are added and the result has wrong sign bit
0 1

0 1

or

1 0

In general, overflow occurs if carries into and out of MSB are different
-4 +5 1

1011 0101 10000 1 0001

-3 + -4 7 -7

1111

4 + -5 -1
10

00

correct

0100 1010 1110

4 +5 9

01

incorrect (overflow)

-4 0100 0101 + -5 1001 (-6) -9

1011 1010 10101 1 0110 (+6)

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(exception)

1100 1011 10111 Check sign bit (-) ( )+( (-) )( (+) ) 1 (+) + (+) (-) 1000 (-7)

incorrect (overflow)

OF
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1s complement subtraction
Complement the subtrahend Add (A) ) B = ( A) )+( (-B) ) (A) (-B) = (A) + (B)

2s complement addition
Add including g sign g bit Ignore any g y carry y out of the MSB Overflow occurs if carries into and out of MSB are different
3 +4 7

0011 0100 0111

6 + -3 3

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0110 1101 10011

5 + -5 0

0101 1011 10000

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the only y0

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-6 +3 3 -3

correct -3 3 -4 -7
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1010 0011 (-3) ) 1101 (

-6 + -3 9 -9

1010 1101 (+7) ) 10111 (

incorrect (overflow)

10

6 +3 9

01

0110 0011 ) (-7) 1001 (

incorrect (overflow)

(cf)

1101 1100 11001 (-7)

correct V Cout t Cin i +

V = Cin

Cout
V = 0 no overflow V = 1 overflow

if

2s complement subtraction

Complement the subtrahend Add

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(cf) comparison
1s complement - easier to complement 2s complement - simpler addition (no end-around-carry) - one zero representation

2s complement is preferred for most digital systems

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Half-adder (two 1-bit numbers addition)

Simplest adder that adds two 1-bit inputs producing two outputs, sum and carry
A B 0 0 0 1 1 0 1 1 C S 0 0 0 1 0 1 1 0
A B S

S = AB + AB = A B C = AB

But what we really need to do is add three bits: the augend and addend, addend and the carry in from the right. right
1 + 1 1 1 1 1 1 0 1 0 0 1 1 0 1 0 1

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Full-adder (two multi-bit numbers addition)

Adds 3 inputs, Add i t t two 1 1-bit bit inputs i t and d a carry f from th the previous lower significant position, producing two outputs, sum and carry carry-out out
ABCin 000 001 010 011 100 101 110 111 CoutS 00 01 01 10 01 10 10 11

BC 0 1

S 00 01 0 1 1 0 11 0 1 10 1 0

Cout BC 00 01 11 A 0 0 0 1 1 0 1 1

10 0 1

ABCin ABCin ABCin S=A B Cin + A BCin + AB Cin + ABCin

= (AB + AB)Cin + (AB + AB)Cin ) ) (AB + AB)Cin +( (AB + AB)Cin =( = A B Cin Cout = AB + BCin + ACin or Cout = AB + ABCin + ABCin = AB + (A B) Cin
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A B S C Cin

Can build a full adder by putting together two HAs

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Binary parallel adder (ripple adder)

(ex) 4 bit ripple adder
B3 A3 C4 C3 B2 A2 C2 B1 A1 C1 B0 A0 C0 = 0 HA can be used for LSB FA

FA

FA

FA

FA

S3 overflow detecting V

S2

S1

S0

slow since a carry must propagate from least significant FA to most significant FA

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When you add two 4-bit numbers the carry in is always 0, so why h does d the th 4-bit 4 bit adder dd h have a CI input? i t? One reason is so we can put 4-bit adders together to make even larger adders This is just like how we put four full adders together to make the 4-bit adder in the first f rst place. CI is also useful for subtraction Here is an 8 8-bit bit adder, for example.

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Binary parallel subtractor (ripple subtractor)

2 complement 2s l t subtraction bt ti
X Y = X + (-Y) = X + Y + 1
2s 2 s complement = Y Y + 1

(ex) 4 bit ripple subtractor

bit-by-bit complement of Y

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Binary parallel adder/subtractor

A3 B 3 B3 0 1 Sel A2 B2 B2 0 1 Sel A 1 B1 B1 0 1 Sel A 0 B 0 B0 0 1 Sel

A CO + S

B CI

A CO + S

B CI

A CO + S

B CI

A CO + S

B CI Add/Subtract

S3

S2

S1

S0

Overflow

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Carry lookahead adder

carry propagation delay of ripple adder is a limiting factor on the speed most t widely id l used d technique t h i f for reducing d i th delay the d l : principle of carry look-ahead

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Define two variables

Pi = Ai Bi -> carry propagate Gi = Ai Bi -> carry generate
Ci+1 = Ci if one of Ai and Bi is 1 while the other is 0 (Ai Bi = 1)

Gi = 1 if Ai and Bi are both 1, independent of Ci

Si = Ai Bi Ci = Pi Ci Ci+1 = AiBi + Ci (Ai Bi ) = Gi + PiCi C1 = G0 + P0C0 C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0 C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0 C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

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25

CF: Comparison (n-bit adder)

# of f gates t needed d d
carry lookahead adder 3n + (i+2) = 3n+ [(n-1)n]/2 + 2n
i=0 n-1

= n2/2 n/2 + 5n = n2/2 + 9/2 n O(n2) ripple adder : 5n -> O(n)

# of fl levels l (d (delay) l )
lookahead :4 ripple : 2n or 3n
Cout=AB+BC+AC XOR

Trade-off between complexity and performance

Ripple pp carry y adders are simpler, p but slower Carry lookahead adders are faster but more complex.
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BCD adder
(ex)
6 + 3 9

0110 0011 1001

Binary sum = BCD sum

6 +7 13

0110 0111 1101 + 0110 10011

13 in binary sum, but not used in BCD 13 in BCD

3 1 or carry-out

max BCD sum = 9 + 9 + 1 = 19 input c carry

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Decimal K
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1

Binary Sum Z3 Z2 Z1 Z0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

BCD Sum C
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1

S3 S2 S1 S0
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Binary y Sum = BCD Sum

Bin Binary Sum + 0110 BCD Sum

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When (binary sum) 1010, (BCD sum) = (Binary sum) + 0110 C = K + Z3 Z2 + Z3 Z1

addend Cout

augend

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Binary multiplier
M lti li ti is Multiplication i just j t repeated t d addition. dditi AND operation is equivalent to multiplication on two bits
a 0 0 1 1 b 0 1 0 1 ab 0 0 0 1 a 0 0 1 1 b 0 1 0 1 ab 0 0 0 1

x 1 1 0 0

1 0 0 1 0 0 1

1 1 0 0 1 1

0 1 0 1

1 0 0

Multiplicand (m bit) Multiplier (n bit) Partial products

+ 0

0 1

1 0 0

Product (m+n bit)

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Since we always multiply by either 0 or 1, the partial products are always either 0000 or the multiplicand (1101 in this example). Ex: 2x2 binary multiplier

x + C3 A1B1 C2

B1 A1 A0B1 A1B0 C1

B0 A0 A0B0 C0

HA

HA

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4x4 binary multiplier

B3 A3 B3 A0

B2 A2 B2 A0 B1 A1 B0 A2

B1 A1 B1 A0 B0 A1

B0 A0 B0 A0
AND gate adder

B3 A1 B3 A2 B3 A3 C7 C6 B2 A3 C5 B2 A2 B1 A3 C4

B2 A1 B1 A2 B0 A3 C3

C2

C1

C0

When multiplying an m-bit number (multiplicand ) by an nbi number b ( l i li ) bit (multiplier)

There are n partial products We need (mxn) AND gates and mx(n-1) mx(n 1) bit adders (FAs) This requires (n-1) adders, each of which can add m bits (the size of the multiplicand).

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B3 B 1A B 1A B AB B2A B B2A B A33 A B3 B A1 B1 A B 0A B A0 B 0A B A0 A B2 B3 A B1 B2 A B0 B B B B A0A B1 B 3A 1 0 33 33 A 3A 1 A 1B 3A 2 3 22 B 2 A2 3 1 0 A2 B 1 A1 2 A0 3 A2 B 0 A1 1 A0 1 A1 0 A0 B 0

FA FA FA HA FA FA FA

HA FA

HA

HA

FA

S7

S6

S5

S4

S3

S 2

S1

S0

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Arithmetic m Logic g Unit (ALU) ( )

Combinational network that performs both arithmetic and logic g operations p The heart of a processor you could say that everything else in the CPU is there to support the ALU.

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The basic four-bit adder always computes S = A + B + CI.

But by changing what goes into the adder inputs A, B and CI, we can change the adder output S. This is also what we did to build the combined addersubtractor circuit. circuit So we have one adder performing two separate functions. Sub Sub acts like a function select input which determines whether the circuit performs addition or subtraction.
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By following the same approach, we can use an adder to compute t other th functions f ti as well. ll

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Here are some of the different possible arithmetic operations. operations

Selection code S2 S1 S0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Desired arithmetic operation p G (A + B + CI) X X+1 X+Y X+Y+1 X + Y X + Y + 1 X1 X (transfer) (increment) ( ) (add) ( subtraction) (1C ) (2C subtraction) (decrement) (transfer) (tran f r) Required q adder inputs p A B CI 0000 0000 Y Y Y Y 1111 1111 X X X X X X X X 0 1 0 1 0 1 0 1

Adder input CI is always the same as selection code bit S0. B is always set to X. X A depends only on S2 and S1.

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All we need to do is compute the adder input A, given the arithmetic unit input Y and the function select code S (actually just S2 and S1). Here is a truth table:
S2 0 0 1 1 S1 0 1 0 1 A 0000 Y Y 1111

S2 0 0 0 0 1 1 1 1

S1 0 0 1 1 0 0 1 1

Yi 0 1 0 1 0 1 0 1

Ai 0 0 0 1 1 0 1 1

S2 S1 Yi 0 1

0 0

1 1

0 1

Ai = S2Yi + S1Yi

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This completes our arithmetic unit.

S0

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A logic unit supports different logical functions on two multi bit inputs X and Y, multi-bit Y producing an output G G. Four possible functions We ll just use multiplexers and some primitive gates to Well implement this. We need one multiplexer for each bit of X and Y

S1 0 0 1 1

S0 0 1 0 1

Output Gi Gi Gi Gi = = = = XiYi Xi + Yi Xi Yi Xi

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Now we have two pieces:

An arithmetic h unit that h can compute eight h functions f A logic unit that can perform four functions.

We can combine these together into a single circuit circuit, ALU

S3 0 0 0 0 0 0 0 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Operation p G=X G=X+1 G=X+Y G=X+Y+1 G = X + Y G = X + Y Y +1 G=X1 G=X

1 1 1 1

x x x x

0 0 1 1

0 1 0 1

G = X and Y G = X or Y G=XY G = X
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A complete ALU circuit

4

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This ALU is a good example of hierarchical design.

With W h the h 12 inputs, the h truth h table bl would ld have h had h d 212 = 4096 lines. Instead, we were able to use components that weve we ve seen before to construct the entire circuit from a couple of easy-to-understand components.
4 4 4 4

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Cf: 74181 4-bit ALU selection l ti i inputs t : M (0/1 = A/L selection) l ti ) S0-S3 : function selection

19 21 23 2 18 20 22 1

A3 A2 A1 A0 B3 B2 B1 B0 7 Cn 8 M

181

F3 F2 F1 F0

13 11 10 9

A=B 14 Cn+4 16 G 17 P 15

S3 S2 S1 S0 3 4 5 6

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S3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Selection S2 S1 S0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

M=1 Logic Function F = not A F = A nand B F = (not A) + B F=1 F = A nor B F = not B F = A xnor B F = A + not B F = (not A) B F = A xor B F=B F=A+B F=0 F = A (not B) F=AB F=A

M = 0, Arithmetic Functions Cn = 0 Cn = 1 F = A minus 1 F=A F = A B minus 1 F=AB F = A (not B) minus 1 F = A (not B) F = minus i 1 F = zero F = A plus (A + not B) F = A plus (A + not B) plus 1 F = A B plus (A + not B) F = A B plus (A + not B) plus 1 F = A minus B minus 1 F = (A + not B) plus 1 F = A + not B F = A minus B F = A plus (A + B) F = (A + not B) plus 1 F = A plus B F = A plus (A + B) plus 1 F = A (not B) plus (A + B) F = A (not B) plus (A + B) plus 1 F = (A + B) F = (A + B) plus 1 F=A F = A plus A plus 1 F = A B plus A F = AB plus A plus 1 F= A (not B) plus A F = A (not B) plus A plus 1 F=A F = A plus 1

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