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Intelligence for the Desktop NanoBoard NB2DSK01 is provided courtesy of firmware running in the board's NanoTalk Controller. This application note describes how to update this firmware, which gets loaded into the NanoTalk Controller at power-up.
The Desktop NanoBoard NB2DSK01 uses a Xilinx Spartan-3 device (XC3S1500-4FG676C) as the controller for the board. Referred to as the NanoTalk Controller, this device (designated U5) communicates with the host PC using Altium's NanoTalk communications protocol. It is responsible for managing JTAG communications with the following: Parallel and USB PC interfaces System JTAG header FPGA daughter board Peripheral boards Master/Slave daisy-chain User Board headers Host status LEDs 1-Wire memory devices (used for identification) on motherboard, daughter board, peripheral boards and Desktop Stereo Speaker Assembly NB2DSK-SPK01 TFT LCD panel Touch Screen Digitizer SPI Master clock SPI Flash memory Real-Time Clock (RTC) SPI resources on peripheral boards SPI-compatible LED drivers on the attached Desktop Stereo Speaker Assembly NB2DSK-SPK01
The NanoTalk Controller also manages/communicates with the following areas of the board:
It is the NanoTalk Controller into which the intelligence for the system the NanoBoard firmware is programmed. This upgradeable firmware is stored in a Xilinx Platform Flash Configuration PROM device (XCF08PFS48C), designated U7 on the board. On power-up, the firmware is automatically loaded from the Configuration PROM into the NanoTalk Controller. Note: The version of firmware currently loaded into the Configuration PROM can be identified in two places. Firstly, underneath the icon for the NanoBoard in the NanoBoard chain of the Devices view (View Devices View). Secondly, from the TFT LCD panel on the NB2DSK01 motherboard itself. For detailed information on the Desktop NanoBoard NB2DSK01, refer to the document TR0143 Technical Reference Manual for Altium's Desktop NanoBoard NB2DSK01.
Pre-update Preparation
Before the new version of firmware can be downloaded to the Configuration PROM, the Desktop NanoBoard NB2DSK01 must first be prepared as follows: 1. Turn off the NB2DSK01. 2. Connect from the PC to the 'SYSTEM JTAG' header on the NB2DSK01 (at the left-hand edge of the board). This is a fixed function header which, when used, switches control of the NB2DSK01 from the NanoTalk Controller to a simple hardware chain, which involves the NanoTalk Controller and the Configuration PROM. Connection to the 'SYSTEM JTAG' header involves the use of Altium's Universal JTAG Interface, to convert from parallel or USB cabling to 10-way IDC JTAG cabling. This interface device, along with various connection cables, is shipped with the Altium Designer software. Note: The selector switch on the Universal JTAG Interface is used only when programming a JTAG device from Altera Quartus II or Xilinx ISE tools directly, and via their associated parallel cabling. The switch position has no relevance when programming the Configuration PROM from Altium Designer. 3. Power-up the NB2DSK01.
Figure 1. The Universal JTAG Interface facilitates connection to the 'SYSTEM JTAG' header.
The configuration for the device is stored in a PROM file, using the Intel MCS-86 format. This is an ASCII hex file with extension .mcs. To download the new configuration: 4. Right-click on the icon for the Configuration PROM in the Hard Devices chain of the Devices view and select Choose File and Download from the pop-up menu. 5. The Choose Programming File For Xilinx XCF XCF08PFS48C dialog appears. Use this dialog to navigate to the required programming file ( *.mcs) and click Open. By default, this file is located in the \System folder of the installation.
Figure 3. Successful detection of Desktop NanoBoard NB2DSK01 and target FPGA device.
7. Open an FPGA project that includes one or more Nexus-enabled devices (e.g. processors, counters, logic analyzers) and that is appropriately configured to target the FPGA device on the DB30 daughter board. Go ahead and program the FPGA on the daughter board. This will test that the Soft Devices JTAG chain is functioning correctly (presented as the bottom chain in the Devices view, once the design is downloaded into the target physical device).
Figure 4. Successful communications with a Nexus-enabled device in the Soft Devices JTAG chain.
8. With the chosen design running in the FPGA, double-click on the icon for the NB2DSK01 (in the NanoBoard chain of the Devices view). The Instrument Rack NanoBoard Controllers panel will appear. Use the instrument panel to change the system clock frequency. This will write the new clock frequency to the system clock, which, being an SPI device, will test that communication to SPI devices is working correctly.
As well as writing the new frequency to the clock, the value will also be stored in the common-bus Flash memory and read back by the NanoTalk Controller to verify the change. As the new frequency is stored in the Flash memory, it is persistent across both design sessions and hardware sessions. Therefore, closing Altium Designer, relaunching and opening an FPGA project (or cycling the NB2DSK01's power) will result in the last clock frequency entered being used.
Revision History
Date 17-Oct-2007 17-Dec-2007 15-May-2008 Version No. 1.0 1.1 2.0 Revision Initial release Updated for Altium Designer 6.9 Updated for Altium Designer Summer 08
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